JP2006343962A - Data processing device, power saving control method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processing device, capable of quickly, surely and easily attaining power saving, and a power saving control method and a program therefor. <P>SOLUTION: A reconfigurable processor 1000 comprises a CPU core 1001, a control circuit 1002, a plane 1003 to which a circuit configuration for functioning in a general mode is written; a plane 1004 to which a circuit configuration necessary for return to the general mode in a power-saving mode is written, and a control circuit 1005. In the general mode, the plane 1003 is connected to the CPU core 1001 and the outside by the control circuits 1002 and 1005 to perform power supply and clock supply to the plane 1003, while the connection of the plane 1004 to the CPU core 1001 and the outside is separated. In the power saving mode, the plane 1004 is connected to the CPU core 1001 and the outside by the control circuits 1002 and 1005 to perform power supply and clock supply to the plane 1004, while the connection of the plane 1003 to the CPU core 1001 and the outside is separated. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data processing device, a power saving control method, and a program that enable power saving at a device level when a reconfigurable processor is used.

  In recent years, technology related to dynamically reconfigurable processors, so-called dynamic reconfigurable technology, has been developed that can instantly switch the circuit configuration as needed when executing application programs (hereinafter referred to as applications). Has been. With reconfigurable technology, it is possible to create an environment in which software can easily realize performance equivalent to that of dedicated logic, with little awareness of the hardware structure.

  Along with this, a mechanism that simplifies complicated design work as in the case of designing an ASIC (Application Specific Integrated Circuit) as in the past and shortens the development period of ICs, LSIs, and the like is being prepared. As long as the simulation during application development passes, the execution of the reconfigurable processor on the actual chip is completely guaranteed. For this reason, code optimization and reversion of the development process, such as those seen in development for FPGAs (Field Programmable Gate Arrays) and DSPs (Digital Signal Processors), do not occur, and the ASIC verification work is complicated. You won't be swayed by the work.

  In the reconfigurable technology, the circuit configuration can be switched at high speed, so that the same chip can be instantly changed into various dedicated LSIs. That is, it is possible to switch to a necessary circuit configuration from time to time, like a virtual memory of a computer.

  In the conventional ASIC, the circuit once created cannot be changed, and the sample chip that has been taped out (design data submitted from the manufacturer to the user) often does not work, so the design work can be re-executed again. It wasn't unusual. On the other hand, since the reconfigurable processor can easily and instantaneously switch the circuit configuration simply by exchanging the configuration information, it can solve the problem such as the re-execution of the design work as described above in the conventional ASIC. It has become to.

The reconfigurable technology described above is disclosed in various documents (for example, see Non-Patent Document 1).
Nikkei Electronics 2003.1.6

  However, in the above reconfigurable technology, in addition to the flexibility that the circuit configuration can be switched instantaneously, studies have also been made on power saving to reduce power consumption. The interior of the reconfigurable processor is mainly composed of two parts, that is, a CPU core and a data processing unit in which arithmetic units are arranged in a matrix. By supplying the clock only to the arithmetic units required for the circuit configuration and gating the so-called clock for the arithmetic units that are not used, it is possible to suppress wasteful power consumption by operating the device (chip). Yes.

  Even with the above-described method of supplying a clock only to a portion necessary for the circuit configuration, it is possible to obtain a certain amount of power saving effect. However, even in the environment where the device is operated, for example, when driving the battery by supplying power to the device from the battery, it is possible to further reduce power consumption when the standby power consumption must be suppressed as low as possible. There is a need to do that.

  An object of the present invention is to provide a data processing device, a power saving control method, and a program that can realize power saving quickly, reliably, and easily.

  In order to achieve the above object, a data processing device of the present invention includes a first circuit assembly in which a circuit configuration for functioning in the normal mode is written, and a circuit necessary for returning to the normal mode in the power saving mode. In the normal mode, the second circuit assembly to which the configuration is written and the first circuit assembly are supplied with power and clocks, and the connection between the second circuit assembly and the outside is disconnected to save power. In the mode, the power supply and the clock are supplied to the second circuit assembly, and control means for performing control for disconnecting the connection between the first circuit assembly and the outside is provided.

  In order to achieve the above-described object, the power saving control method of the present invention requires a first circuit assembly in which a circuit configuration for functioning in the normal mode is written, and a return to the normal mode in the power saving mode. A power saving control method for a data processing device including a second circuit assembly in which a circuit configuration is written, and in the normal mode, supplies power and clocks to the first circuit assembly, and Control for disconnecting the connection between the first circuit assembly and the outside while disconnecting the connection between the second circuit assembly and the outside and supplying power and a clock to the second circuit assembly in the power saving mode. It is characterized by performing.

  In order to achieve the above-described object, the program of the present invention includes a first circuit assembly in which a circuit configuration for functioning in the normal mode is written, and a circuit configuration necessary for returning to the normal mode in the power saving mode. A program for causing a computer to execute a power saving control method for a data processing device including a second circuit assembly to be written, and for supplying power and a clock to the first circuit assembly in a normal mode. A module for controlling the connection between the second circuit assembly and the outside, and a power supply and a clock supply to the second circuit assembly in the power saving mode, and the first circuit assembly. And a module for performing control for disconnecting the connection with the outside.

  According to the present invention, the power and clock are supplied to the first circuit assembly in the normal mode, the external connection is disconnected from the second circuit assembly, and the second circuit assembly is disconnected in the power saving mode. A power source and a clock are supplied to the first circuit assembly and the external connection is disconnected from the first circuit assembly. In other words, it is possible to stop not only the clock supply but also the power supply for the plane that is not necessary for the operation, and it is possible to rewrite the circuit configuration optimally considering power saving in accordance with the operating mode. . Thereby, it is possible to realize power saving quickly, surely and easily.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a block diagram showing a configuration of a reconfigurable processor as a data processing device according to the first embodiment of the present invention.

  1, the reconfigurable processor 1000 includes a CPU core 1001, a control circuit 1002, circuit configuration planes 1 and 1003, circuit configuration planes 2 and 1004, and a control circuit 1005. In the following description, the circuit configuration planes 1 and 1003 and the circuit configuration planes 2 and 1004 are abbreviated as a plane 1003 and a plane 1004, respectively.

  The CPU core 1001 is a core part excluding a circuit for transmitting and receiving signals to and from the outside. The plane 1003 and the plane 1004 are aggregates in which a plurality of arithmetic units are arranged in a matrix. A control circuit 1002 is connected between the CPU core 1001 and the planes 1003 and 1004, and a control circuit 1005 is connected between the planes 1003 and 1004 and the outside. The control circuits 1002 and 1005 supply / shut off power from the power source, supply / shut off clock from the clock generator, and input / output of signals between the reconfigurable processor 1000 and an external circuit (not shown). Etc. are controlled.

  The circuit configuration of both the plane 1003 and the plane 1004 can be rewritten. However, in the plane 1003, a circuit configuration for functioning in the normal mode (usually supporting all functions) is written, and in the plane 1004, a circuit configuration is written in the power saving mode. Note that a circuit configuration necessary for returning from the power saving mode to the normal mode is written in the plane 1004.

  In the normal mode, the plane 1003 is connected to the CPU core 1001 via the control circuit 1002 and is connected to the outside via the control circuit 1005. Accordingly, power supply and clock supply are performed from a power supply unit and a clock generation unit (not shown) to the reconfigurable processor 1000, respectively. The plane 1004 is not connected to the CPU core 1001 and the outside by the control circuit 1002 and the control circuit 1005 at all.

  On the other hand, in the power saving mode, contrary to the normal mode, the plane 1004 is connected to the CPU core 1001 via the control circuit 1002 and is connected to the outside via the control circuit 1005. Accordingly, power supply and clock supply are performed from a power supply unit and a clock generation unit (not shown) to the reconfigurable processor 1000, respectively. The plane 1003 is not connected to the CPU core 1001 and the outside by the control circuit 1002 and the control circuit 1005 at all. This makes it possible to easily realize power saving at the device level.

  In the present embodiment, the plane 1004 can be configured such that the size of the plane 1004 (specifically, the number of arithmetic units constituting the plane, etc.) can be arbitrarily set. The plane 1004 is intended to rewrite the circuit configuration of only the return circuit that performs the return processing from the power saving mode to the normal mode, and is not a specification that requires a processing speed but considers low power consumption. ing.

  In this embodiment, when rewriting the circuit configuration to the plane, it is not necessary to turn on the power again and switch the reset signal, and the rewriting of the circuit configuration is completed in a short time (for example, about 1 clock). Is possible. The same applies to second to fourth embodiments described later.

  As described above, according to the present embodiment, in the normal mode, the plane 1003 is connected to the CPU core 1001 and the outside by the control circuits 1002 and 1005 to supply power and clock, and the plane 1004 and CPU core 1001 are connected. Disconnect the external connection. In the power saving mode, the plane 1004 is connected to the CPU core 1001 and the outside by the control circuits 1002 and 1005 to perform power supply and clock supply, and the connection between the plane 1003 and the CPU core 1001 and the outside is disconnected.

  In other words, it is possible to stop not only the clock supply but also the power supply for the plane that is not necessary for the operation, and it is possible to rewrite the circuit configuration optimally considering power saving in accordance with the operating mode. . Thereby, it is possible to realize power saving quickly, surely and easily.

[Second Embodiment]
The second embodiment of the present invention is different from the above-described first embodiment in that the reconfigurable processor has the configuration shown in FIG. Since the other elements of the present embodiment are the same as the corresponding ones of the first embodiment (FIG. 1) described above, the description is omitted or simplified.

  FIG. 2 is a block diagram showing a configuration of a reconfigurable processor as a data processing device according to the present embodiment.

  In FIG. 2, a reconfigurable processor 2000 includes a CPU core 1001, a control circuit 1002, circuit configuration planes 1 and 1003, circuit configuration planes 2 and 1004, circuit configuration planes 3 and 1006, circuit configuration planes 4 and 1007, circuit configuration planes 5 and 1008, and a control circuit 1005 are provided. In the following description, the circuit configuration planes 1 and 1003 to the circuit configuration planes 5 and 1008 are abbreviated as a plane 1003 to a plane 1008, respectively.

  The CPU core 1001 is a core part excluding a circuit for transmitting and receiving signals to and from the outside. The planes 1003, 1006, 1007, 1008, and the plane 1004 are aggregates in which a plurality of arithmetic units are arranged in a matrix. A control circuit 1002 is connected between the CPU core 1001 and the planes 1003, 1004, 1006, 1007, 1008, and a control circuit 1005 is connected between the planes 1003, 1004, 1006, 1007, 1008 and the outside. Has been. The control circuits 1002 and 1005 supply / shut off power from the power source, supply / shut off clock from the clock generator, and input / output of signals between the reconfigurable processor 1000 and an external circuit (not shown). Etc. are controlled.

  All of the planes 1003 and 1006 to 1008 and the plane 1004 can be rewritten in circuit configuration. However, in the planes 1003 and 1006 to 1008, a circuit configuration for functioning in the normal mode (usually supporting all functions) is written, and in the plane 1004, a circuit configuration is written in the power saving mode. Become. The plane 1004 is written with a circuit configuration necessary for returning from power saving to normal operation.

  In the normal mode, the configuration of the functional circuit is written in the planes 1003 and 1006 to 1008. However, when the processing speed is not required in the functional circuit, the circuit configuration is written by sequentially switching one plane at a time, such as plane 1003 → plane 1006 → plane 1007 → plane 1008 → plane 1003 →. There is always one plane in operation.

  One plane is connected to the CPU core 1001 via the control circuit 1002 and is connected to the outside via the control circuit 1005. Accordingly, power supply and clock supply are performed from the power supply unit and the clock generation unit (not shown) to the reconfigurable processor 2000, respectively. The plane 1004 is not connected to the CPU core 1001 and the outside by the control circuit 1002 and the control circuit 1005 at all.

  On the other hand, in the power saving mode, contrary to the normal mode, the plane 1004 is connected to the CPU core 1001 via the control circuit 1002 and is connected to the outside via the control circuit 1005. Accordingly, power supply and clock supply are performed from the power supply unit and the clock generation unit (not shown) to the reconfigurable processor 2000, respectively. The planes 1003 and 1006 to 1008 are not connected to the outside of the CPU core 1001 by the control circuit 1002 and the control circuit 1005 at all. Thereby, power saving at the device level can be easily realized.

  In the present embodiment, as in the first embodiment, the plane 1004 can be configured so that the size of the plane 104 can be arbitrarily set. The plane 1004 is intended to rewrite the circuit configuration of only the return circuit that performs the return processing from the power saving mode to the normal mode, and is not a specification that requires a processing speed but considers low power consumption. ing.

  As described above, according to the present embodiment, when the processing speed is not required in the normal mode, the circuit configuration is written by sequentially switching the planes 1003 and 1006 to 1008 one by one. One plane is connected to the CPU core 1001 and the outside by the control circuits 1002 and 1005 to perform power supply and clock supply, and disconnect the connection between the plane 1004 and the CPU core 1001 and the outside. In the power saving mode, the plane 1004 is connected to the CPU core 1001 and the outside by the control circuits 1002 and 1005 to perform power supply and clock supply, and the plane 1003 and 1006 to 1008 are disconnected from the CPU core 1001 and the outside.

  In other words, it is possible to stop not only the clock supply but also the power supply for the plane that is not necessary for the operation, and it is possible to rewrite the circuit configuration optimally considering power saving in accordance with the operating mode. . Thereby, it is possible to realize power saving quickly, surely and easily.

[Third Embodiment]
The third embodiment of the present invention is different from the above-described second embodiment in that the processing speed is required in the functional circuit. The other elements of the present embodiment are the same as the corresponding ones of the second embodiment (FIG. 2) described above, and a description thereof will be omitted. In the present embodiment, the operation in the normal mode and the power saving mode will be mainly described.

  In the normal mode, the configuration of the functional circuit is written in the planes 1003 and 1006 to 1008. However, in the case of processing requiring a processing speed in the functional circuit, writing of the circuit configuration and switching of the plane are performed using all of the planes 1003 and 1006 to 1008. By using a plurality of operating planes, high speed can be achieved.

  The planes 1003 and 1006 to 1008 are connected to the CPU core 1001 via the control circuit 1002 and are connected to the outside via the control circuit 1005. Accordingly, power supply and clock supply are performed from the power supply unit and the clock generation unit (not shown) to the reconfigurable processor 2000, respectively. The plane 1004 is not connected to the CPU core 1001 and the outside by the control circuit 1002 and the control circuit 1005 at all.

  On the other hand, in the power saving mode, contrary to the normal mode, the plane 1004 is connected to the CPU core 1001 via the control circuit 1002 and is connected to the outside via the control circuit 1005. Accordingly, power supply and clock supply are performed from the power supply unit and the clock generation unit (not shown) to the reconfigurable processor 2000, respectively. The planes 1003 and 1006 to 1008 are not connected to the outside of the CPU core 1001 by the control circuit 1002 and the control circuit 1005 at all. Thereby, power saving at the device level can be easily realized.

  In the present embodiment, as in the first embodiment, the plane 1004 can be configured so that the size of the plane 104 can be arbitrarily set. The plane 1004 is intended to rewrite the circuit configuration of only the return circuit that performs the return processing from the power saving mode to the normal mode, and is not a specification that requires a processing speed but considers low power consumption. ing.

  As described above, according to the present embodiment, when the processing speed is required in the normal mode, the circuit configuration is written using all the planes 1003 and 1006 to 1008. The planes 1003 and 1006 to 1008 are connected to the CPU core 1001 and the outside by the control circuits 1002 and 1005 to perform power supply and clock supply, and disconnect the plane 1004 from the CPU core 1001 and the outside. In the power saving mode, the plane 1004 is connected to the CPU core 1001 and the outside by the control circuits 1002 and 1005 to perform power supply and clock supply, and the plane 1003 and 1006 to 1008 are disconnected from the CPU core 1001 and the outside.

  In other words, it is possible to stop not only the clock supply but also the power supply for the plane that is not necessary for the operation, and it is possible to rewrite the circuit configuration optimally considering power saving in accordance with the operating mode. . Thereby, it is possible to realize power saving quickly, surely and easily.

[Fourth Embodiment]
The fourth embodiment of the present invention shows a specific example of the power saving operation transition process with respect to the first to third embodiments described above. The other elements of the present embodiment are the same as the corresponding ones of the first to third embodiments (FIGS. 1 and 2) described above, and thus description thereof is omitted.

  FIG. 3 is a flowchart showing the flow of the power saving operation transition process in the reconfigurable processor as the data processing device according to the present embodiment. This processing is executed by the CPU core 1001 based on the program.

  In FIG. 3, first, when power is supplied to the reconfigurable processor and activated, the CPU core 1001 writes a circuit configuration for functioning in the normal mode to the plane (step S300). The writing of the circuit configuration to the plane is the same as that described in the first to third embodiments. When the writing process of the circuit configuration to the plane is completed, the CPU core 1001 switches the plane, the power source, and the signal line, and shifts to the normal mode (step S301).

  Next, after the writing process of the circuit configuration for functioning in the normal mode is completed, the CPU core 1001 shifts to the standby mode (step S302), shifts to the sleep mode (step S303), battery drive mode (Step S304) is determined. When shifting to the power saving mode (sleep mode, battery drive mode), the CPU core 1001 returns to the normal mode from the power saving mode corresponding to each mode for the plane provided for power saving. Only the circuit configuration is written (step S306).

  After the writing process of the circuit configuration is completed, the CPU core 1001 switches the plane, the power source, and the signal line, and shifts to the power saving mode (sleep mode, battery drive mode) (step S307). Next, when returning to the normal mode (YES in step S308), the CPU core 1001 writes the circuit configuration for functioning in the normal mode again into the normal plane.

  On the other hand, when not shifting to the power saving mode (sleep mode, battery drive mode), the CPU core 1001 performs the normal operation of the written functional circuit (step S305). Thereafter, when writing a circuit for functioning in the next normal mode (YES in step S309), the CPU core 1001 writes the circuit configuration in the plane again (step S300).

  In this embodiment, the sleep mode and the battery drive mode are exemplified as the power saving mode, but an idle mode may be added.

  As described above, according to the present embodiment, after the writing process of the circuit configuration for functioning in the normal mode is completed, when shifting to the power saving mode, for the plane provided for power saving, Only the circuit configuration for returning from the power saving mode to the normal mode is written.

  In other words, it is possible to rewrite the circuit configuration in consideration of power saving in accordance with the operating mode. Thereby, it is possible to realize power saving quickly, surely and easily.

[Other embodiments]
In addition, an object of the present invention is to supply a storage medium storing software program codes for realizing the functions of the embodiments to a system or apparatus, and a computer (or CPU, MPU, etc.) of the system or apparatus as a storage medium. This can also be achieved by reading and executing the stored program code.

  In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the program code and the storage medium storing the program code constitute the present invention.

  Examples of the storage medium for supplying the program code include a floppy (registered trademark) disk, a hard disk, a magneto-optical disk, a CD-ROM, a CD-R, a CD-RW, a DVD-ROM, a DVD-RAM, and a DVD. -RW, DVD + RW, magnetic tape, nonvolatile memory card, ROM, etc. can be used. Alternatively, the program code may be downloaded via a network.

  Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an OS (operating system) running on the computer based on the instruction of the program code. This includes a case where part or all of the actual processing is performed and the functions of the above-described embodiments are realized by the processing.

  Further, after the program code read from the storage medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the function expansion is performed based on the instruction of the program code. This includes the case where the CPU or the like provided in the board or the function expansion unit performs part or all of the actual processing, and the functions of the above-described embodiments are realized by the processing.

  Further, by executing the program code read out by the computer, not only the functions of the above-described embodiments are realized, but also the OS running on the computer based on the instruction of the program code is actually Needless to say, the present invention also includes a case in which the functions of the above-described embodiments are realized by performing part or all of the processing and the processing.

  In this case, the program is supplied by downloading directly from a storage medium storing the program or from another computer or database (not shown) connected to the Internet, a commercial network, a local area network, or the like.

  The form of the program may be in the form of object code, program code executed by an interpreter, script data supplied to an OS (operating system), and the like.

It is a block diagram which shows the structure of the reconfigurable processor as a data processing device which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the structure of the reconfigurable processor as a data processing device concerning the 2nd and 3rd Embodiment of this invention. It is a flowchart which shows the flow of the power saving operation | movement transition process in the reconfigurable processor as a data processing device concerning the 4th Embodiment of this invention.

Explanation of symbols

1000, 2000 Reconfigurable processor (data processing device)
1001 CPU core (control means)
1002, 1005 Control circuit 1003 Plane 1 (first circuit aggregate)
1004 Plane 2 (second circuit aggregate)
1006 Plane 3 (first circuit aggregate)
1007 Plane 4 (first circuit aggregate)
1008 Plane 5 (first circuit aggregate)

Claims (11)

A first circuit assembly in which a circuit configuration for functioning in the normal mode is written;
A second circuit assembly in which a circuit configuration necessary for returning to the normal mode in the power saving mode is written;
In the normal mode, power is supplied to the first circuit assembly and a clock is supplied, and the connection between the second circuit assembly and the outside is disconnected. In the power saving mode, the second circuit assembly is supplied with power. Control means for performing supply and clock supply, and performing control for disconnecting the connection between the first circuit assembly and the outside;
A data processing device comprising: A plurality of the first circuit assemblies;
2. The circuit configuration according to claim 1, wherein when the processing speed is not required in the normal mode, the control means writes the circuit configuration by sequentially switching and operating the plurality of first circuit aggregates one by one. Data processing devices. A plurality of the first circuit assemblies;
2. The data processing device according to claim 1, wherein when the processing speed is required in the normal mode, the control means writes the circuit configuration using all of the plurality of first circuit aggregates.   2. The data processing device according to claim 1, wherein when the control unit shifts to the power saving mode, the circuit configuration necessary for returning from the power saving mode to the normal mode is written in the second circuit aggregate. 3. .   The data processing device according to claim 4, wherein the power saving mode includes a sleep mode, an idle mode, and a battery drive mode.   At the time of rewriting the circuit configuration to the first circuit assembly and the second circuit assembly, it is not necessary to turn on the power again and switch the reset signal, and rewriting of the circuit configuration can be completed in a short time. The data processing device according to claim 1.   The data processing device according to claim 1, wherein the first circuit aggregate and the second circuit aggregate are aggregates in which a plurality of arithmetic units are arranged in a matrix.   The data processing device according to claim 1, wherein the size of the second circuit aggregate can be arbitrarily set.   The data processing device according to claim 1, wherein the data processing device is applied to a processor using a reconfigurable technology. A data processing device comprising a first circuit assembly in which a circuit configuration for functioning in a normal mode is written, and a second circuit assembly in which a circuit configuration necessary for returning to the normal mode is written in the power saving mode Power saving control method
In the normal mode, power is supplied to the first circuit assembly and a clock is supplied, and the connection between the second circuit assembly and the outside is disconnected. In the power saving mode, the second circuit assembly is supplied with power. A power saving control method characterized by performing supply and clock supply, and performing control to disconnect the connection between the first circuit assembly and the outside. A data processing device comprising a first circuit assembly in which a circuit configuration for functioning in a normal mode is written, and a second circuit assembly in which a circuit configuration necessary for returning to the normal mode is written in the power saving mode A program for causing a computer to execute the power saving control method of
A module for performing power supply and clock supply to the first circuit assembly during normal mode, and for controlling the connection between the second circuit assembly and the outside;
A module that performs power supply and clock supply to the second circuit assembly during power saving mode, and controls to disconnect the connection between the first circuit assembly and the outside;
A program comprising:

Images