JP3666744B2 - Power-off control device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power cutoff control device capable of reducing power consumption of an LSI, and more particularly to a power cutoff control device for reducing a static power supply current in a system LSI using a fine process.
[0002]
[Prior art]
In recent years, semiconductor integrated circuits have become system LSIs, and the number of transistors mounted on one LSI chip is increasing. Along with this, a finer process has been used as a measure for reducing current consumption and cost. However, in a fine process of 0.25 μm or less, the leakage current of each transistor increases, and an increase in static power supply current when LSI operation is stopped (stop mode) has become a value that cannot be ignored.
[0003]
In particular, in a battery-driven portable terminal device, the LSI is normally in the stop mode during standby, but due to the increase in the stationary power supply current, there is a problem in driving time and current consumption as a set. For this reason, in an LSI for a portable terminal device, it is necessary to reduce current consumption in the stop mode as well as current consumption during normal operation (normal mode). In addition, system LSIs are becoming more difficult to control and software development is becoming very difficult as system complexity and circuit scale increase significantly.
[0004]
A configuration example of a conventional system LSI incorporating a processor is shown in a block diagram of FIG. In FIG. 5, reference numeral 501 denotes a control circuit for controlling circuit operation stop and clock supply stop in the stop mode, 502 a system circuit 1 related to a specific system function, 503 a system circuit 2 related to another specific system function, Reference numeral 505 denotes a processor circuit block, and reference numerals 507, 508, and 509 denote a processor core, a peripheral circuit, and a memory built in the processor circuit block 505, respectively.
[0005]
In the configuration of FIG. 5, the control circuit 501 is connected to the system circuit 1, the system circuit 2, and the processor circuit block by a signal line a, a signal line b, and a signal line c each composed of input and output signals. In addition, the system circuit 1 and the system circuit 2 are connected to the processor circuit block by a signal line d and a signal line e, which are input and output signals, respectively. In this way, the system circuit 1 is connected to the processor circuit block to realize a specific system function, and the system circuit 2 is connected to the processor circuit block to realize another specific system function.
[0006]
In such a configuration, at the time of standby, the processor issues a stop mode command to the control circuit 501, and stops the circuit operations of the peripheral functional circuit blocks controlled by the processor. That is, the circuit operation is stopped by resetting the target functional circuit block or stopping the supply of the clock.
[0007]
[Problems to be solved by the invention]
The conventional measures for reducing the quiescent power supply current are merely to reduce the current consumption by stopping the circuit, so there is no measure against the increase in the leakage current of the transistor due to the fine process. Before the fine process of 0.25 μm or less was adopted, the leakage current of the transistor was negligible and no countermeasure was required. However, the progress of the process in recent years is remarkable, and further miniaturization of the process is progressing, and it is an urgent task to reduce the quiescent power supply current resulting from the increase in the leakage current of the transistor due to the micro process.
[0008]
There is also an LSI in which a plurality of system functions are built in one system LSI. In such an LSI, since the control relationship of the system is complicated, it is difficult to control the quiescent power supply current by shutting off the power supply of each individual system circuit block, and even if it can, it is difficult to obtain a great effect. In addition, software development has become very difficult due to the complexity of the system, and the development man-hours are increasing.
[0009]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a power shutdown control device capable of reducing the quiescent power supply current in the stop mode in a system LSI using a finer process. To do. Another object of the present invention is to provide an LSI configuration method capable of reducing the software development man-hours or period.
[0010]
[Means for Solving the Problems]
In order to solve this problem, the present invention Power of Each of the source cutoff control devices includes a processor (processor 1: processor 2), and any function is provided for a plurality of functional circuit blocks (system circuit 1, processor 104: system circuit 2, processor 104) that can operate independently. When the operation of the circuit block is stopped, a control circuit (control circuit 101) is provided that individually performs power-off control for the function block whose operation has been stopped.
[0011]
the above According to the power-off control device, even a complicated system LSI having a plurality of system functions is configured so that a system circuit block that realizes each system function includes a processor as much as possible, and the operation is Since the power cut-off control circuit capable of stopping the operation of the system having unnecessary system functions and individually shutting off the power supply thereof is provided, the quiescent power supply current in the stop mode can be reduced to the maximum.
[0012]
In addition, because each system function is equipped with a processor and can handle individual processing, not only power-off control is easy, but there is also a secondary effect that the development man-hour or period can be reduced in software development. Can be obtained.
[0013]
The present invention Power of The source cutoff control device further A system state transition register for displaying the operation state of the functional circuit block, a power cutoff register for instructing the functional circuit block to perform processing at power shutdown, and an external computer for the system state transition register and the power shutdown register And an interface for performing register control from an external computer to control the power shutdown from the external computer using the power shutdown register for the functional circuit block indicated by the system state transition register as being in an operation stop state. Is possible.
[0014]
the above According to the power-off control device, each system circuit block and each processor in the stop mode (when no operation is required) by performing register control from an external computer such as a microcomputer via the system state transition register and the power-off control register. The power cutoff of the circuit block can be easily controlled, and the static power supply current of the functional circuit block when no operation is required can be reduced. Further, by performing the register control, there is an effect that no malfunction occurs even when the power supply is resumed (when the operation is restored).
[0015]
The present invention Power of The source cutoff control device further Leakage current that flows through the interface circuit of the functional circuit block that is not subject to power shutdown when the power of the functional circuit block that can be powered off is shut off between the functional circuit block that can be powered off and the functional circuit block that is not subject to power shutdown. A leakage current control circuit for preventing is interposed.
[0016]
the above According to the power cutoff control device, a signal at the interface of both circuit blocks is provided by interposing a leakage current control circuit between the circuit block to which power is supplied in the LSI and the circuit block to which power is cut off. Since unnecessary leakage current due to indefiniteness can be prevented, the quiescent power supply current in the stop mode can be reduced to the maximum.
[0017]
The present invention Power of The source cutoff control device further , All power supplied by the power supply circuit in set terminal equipment, etc. Includes functional circuit block A system state transition register and a power shut-off register are provided in the integrated circuit and the power supply circuit, all of which are configured to be connected to an external computer via an interface for register control, and a power supply for each functional circuit block It is possible to control the shut-off of an external computer from a register.
[0018]
the above According to the power shutoff control device, power shutoff for each functional circuit block in each integrated circuit can be controlled by a register from an external computer using a power supply circuit. The operating power supply current can be easily reduced.
[0019]
The present invention Power of The source cutoff control device further A download circuit is provided that enables data to be downloaded from the external memory when the power supply is resumed after the power is shut off.
[0020]
the above According to the power shutdown control device, data including instruction codes can be downloaded from the external memory to the memory in the processor when the system operation is restored, so that no malfunction occurs when the power supply to the LSI is resumed. System operation can be resumed.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0022]
(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a power shutoff control device according to Embodiment 1 of the present invention. In FIG. 1, 101 is a control circuit, 102 is a system circuit 1, 103 is a system circuit 2, and 104 is a combined processor. In the processor 104, 105 is a single processor 1, and 106 is a single processor 2. Reference numerals 107, 108, and 109 denote a core circuit 1, a peripheral circuit 1, and a memory 1 included in the processor 1, respectively. Reference numerals 110, 111, and 112 denote a core circuit 2, a peripheral circuit 2, and a memory 2 included in the processor 2, respectively. Further, 113 and 114 are a processor control circuit and a shared memory included in the processor 104, respectively.
[0023]
1 will be described. The control circuit 101 includes a system circuit 1, a system circuit 2, and a processor 104, and a signal line a, a signal line b, and a signal line c each including input and output signals. It is connected. Here, the signal line c is a signal line mainly connected between the processor control circuit 113 and the shared memory 114. The system circuit 1 is connected to the processor 1 by a signal line d composed of input and output signals, and the system circuit 2 is connected to the processor 2 by a signal line e composed of input and output signals. Although not shown, the processor control circuit 113 and the shared memory 114 are connected to the processor 1 and the processor 2, respectively.
[0024]
The power shutdown control operation in the first embodiment configured as described above will be described below. The system circuit 1 is controlled by the processor 1 and the control circuit 101, and the system circuit 2 is controlled by the processor 2 and the control circuit 101. The system circuit 1 realizes the respective system functions and can operate independently of each other. When the system circuit 1 and the system circuit 2 are operated in parallel, the processor 1 and the processor 2 are controlled using the control circuit 101, the processor control circuit 113, and the shared memory 114.
[0025]
When the system circuit 1 system is operated and the system circuit 2 system operation is unnecessary, the system circuit 2 and the processor 2 stop the circuit operation and enter the stop mode, shut off the power of these circuit blocks, The leakage current of the transistor can be reduced. In addition, data that is desired to be prevented from disappearing when the power is turned off can be saved in the shared memory 114 when the power is turned off. The return of the operation when the power supply is resumed is controlled by the control circuit 101 and the processor control circuit 113.
[0026]
The same applies to the case where the system circuit 2 system is operated and the system circuit 1 system operation is unnecessary. Further, when the operation of both the system circuit 1 and the system circuit 2 is not required, power is supplied only to the control circuit 101, the processor control circuit 113, and the shared memory 114, and the power of other functional circuit blocks is supplied. Can be blocked. At this time, data desired to be eliminated can be saved in the shared memory 114 when the power is shut off. The return of the operation when the power supply is resumed is controlled by the control circuit 101 and the processor control circuit 113.
[0027]
As described above, according to the circuit configuration of the power shutoff control device of the first embodiment, each system function compared to a conventional system LSI configured by a single processor and a system circuit that realizes each system function. In the stop mode, the system circuit is configured to include a processor, and has a power shutdown control circuit that can shut down the system functions that do not require operation and shut off the power individually. The quiescent power supply current can be reduced to the maximum.
[0028]
In particular, control that requires consideration of operation timing, such as power shutdown, cannot be performed properly without a processor that can cope with the control. In order to restore the system from power shutdown in a short time, a functional circuit block to which power is always supplied is required in the processor. At this time, the operating processor on one side can also be used for control and processing.
[0029]
Further, with the configuration of the present embodiment, since the performance and memory scale of the processor included in the system circuit that realizes each system function can be set to an optimum circuit scale suitable for each system function, the chip The increase in size can be minimized.
[0030]
In particular, LSIs used in mobile phones that periodically repeat the stop mode and normal mode, LSIs with multiple communication systems, and set terminal devices facilitate LSI power control and reduce static power supply current In addition to the effects, the system circuit that implements each system function is configured to include a processor, thereby providing an environment for facilitating software development and reducing the development man-hours or period.
[0031]
(Embodiment 2)
FIG. 2 is a block diagram showing the configuration of the power shutdown control apparatus according to Embodiment 2 of the present invention. In FIG. 2, 201 is a control circuit, 202 is a system circuit, 204 is a processor, 205 is an internal processor unit, 213 is a processor control circuit, and 214 is a shared memory. 102, processor 104, processor 1 (105), processor control circuit 113, and shared memory 114.
[0032]
Further, as a component of the control circuit 201, 215 is a bus interface circuit, 216 is a power-off control register, 217 is a system state transition register, and 218 is a control circuit unit. Reference numeral 219 denotes a leak control circuit, which constitutes a part of the processor 204. Reference numeral 220 denotes a power cutoff control register, and reference numeral 221 denotes a leak control circuit.
[0033]
The bus interface circuit 215 is connected to the power shut-off control register 216 and the system state transition register 217 via the signal line f and the signal line g, respectively. Connected by an external bus n. The system state transition register 217 is also connected to the output of the processor control circuit 213 by a signal line m.
[0034]
The output of the power shutoff control register 216 is connected to the control circuit unit 218 and the leak control circuit 219 through a signal line h. The input of the leak control circuit 219 is connected to the output of the system circuit 202 by the signal line j, and further connected to the power supply potential VDD or VSS. The output of the leak control circuit 219 is connected to the input of the control circuit unit 218 through the signal line k, and the output of the control circuit unit 218 is connected to the system circuit 202 through the signal line i.
[0035]
The power cutoff control operation in the second embodiment configured as described above will be described below. The control circuit unit 201 and the leak control circuit 219 are circuit blocks to which power is always supplied. In the processor 204, an internal processor unit 205 (core, peripheral circuit, memory) is a circuit block that is turned off when no operation is required, and includes a processor control circuit 213 that controls a plurality of processors and functional circuit blocks, a shared memory 214, The power cutoff control register 220 is a circuit block to which power is always supplied. The system circuit 202 is also a block in which the power is cut off when no operation is required.
[0036]
In the LSI, the processor 204 or the like corresponding to each system circuit can usually know whether the system circuit 202 or the like is in the stop mode (operation unnecessary state) including information from the outside. For this purpose, the current information of the system circuit 202 is transferred from the processor control circuit 213 to the system state transition register 217.
[0037]
The microcomputer refers to the system state transition register 217 through the bus interface circuit 215 at every certain timing. When a specific system system is in the stop mode (operation unnecessary state) in the system LSI, the microcomputer uses the bus interface 215 to execute power-off control of the unnecessary system circuit and the corresponding processor unit. Then, an instruction is written into the power-off control registers 216 and 220 to prepare for execution of power-off.
[0038]
Actually, since the power shutdown is executed by the external power IC, the instruction is written in the power shutdown control register, so that each functional circuit block executes pre-processing necessary for power shutdown. For example, in the processor 204, data that is not desired to be erased needs to be transferred to the shared memory 214. Since the shared memory 214 is a circuit block to which power is always supplied, data can be held when the power is shut off. Further, the system circuit 202 can be prepared for power shutdown by the control signal line i from the control circuit unit 218.
[0039]
After the power is cut off, it may be necessary to take measures against a leakage current of a signal connected between the circuit block where the power is cut off and the circuit block supplied with the power. In that case, for example, the leakage control circuit 219 is controlled by the control signal line h from the power cutoff control register 216, and the potential of the input signal line k to the control circuit 201 which is a circuit block supplied with power is set to VDD or VSS. To be fixed. The leak control circuit 221 in the processor 204 also performs the same function.
[0040]
As described above, according to the power-off control device of the second embodiment, each system circuit and each processor in the stop mode (when no operation is required) by the power-off control from the microcomputer via the power-off control register. Can be easily controlled, and the static power supply current of the functional circuit block can be reduced when no operation is required. Further, there is an effect that no malfunction occurs even when the power supply is resumed (when the operation is restored).
[0041]
FIG. 3 is a block diagram illustrating a system configuration example of a set terminal device or the like using the power shutoff control device of the second embodiment. 3, 322 is a microcomputer, 323 is a power shutdown control register and system state transition register in the microcomputer 322, 324 is a system LSI1, 325 is a power shutdown control register and a system state transition register in the system LSI1, and 326 is a system LSIs 2 and 327 are a power-off control register and system state transition register in the system LSI 2, 328 are a power supply IC and 329 are a power-off control register and system state transition register in the power supply IC 328.
[0042]
3 is described. A plurality of VDD-side power supplies (VDD1 to VDD6) of the microcomputer 322, the system LSI1, and the system LSI2 are supplied from the power supply IC 328. The registers 325, 327, and 329 are controlled (read / write) by the microcomputer 322 via the external bus.
[0043]
The operation of the system configured as described above will be described. First, when the system is started, power is supplied to each LSI from the power supply IC 328, and each LSI starts operation. Thereafter, when the set terminal enters the stable state of the system, the system LSI 1 and the system LSI 2 having a plurality of system controls determine the operation mode to be changed based on input data and the like, and set the requested operation mode to the system in 325 and 327, respectively. Write to state transition register.
[0044]
The microcomputer 322 managing the set terminal system reads the information written in the system state transition registers in 325 and 327, and writes the respective control information in the power-off control registers in 325 and 327. Each LSI prepares the operation unnecessary circuit unit for power supply shutdown by the control information written in the power supply shutdown control register. For example, data that is not desired to be erased is transferred to a memory that is not powered off. At the same time, the microcomputer 322 writes the control information in the power cutoff control register in the power source IC 328. The power supply IC 328 controls the power supplies VDD1 to VDD6 of the microcomputer 322, the system LSI1, and the system LSI2 based on the control information, and shuts off the power supply to the LSI circuits that do not require operation.
[0045]
As described above, according to the system of this configuration example, it is possible to easily realize the power shutoff control of the internal circuits of each LSI in the set terminal, shut off the LSI internal circuit power supply in the stop mode (no operation required), and Current can be reduced. In addition, the system can be restored without any problem even when the power supply is resumed.
[0046]
(Embodiment 3)
FIG. 4 is a block diagram showing a configuration of a power shutoff control device according to Embodiment 3 of the present invention. In FIG. 4, 422 is a microcomputer, 431 is an external memory, and 424 is a system LSI. In the system LSI 424, 401 is a control circuit, 430 is a download circuit, 425 is a power shutdown control register, 402 is a system circuit 1, 403 is a system circuit 2, and 404 is a combined processor. Further, in the processor 404, 405 is a single processor 1, 406 is a single processor 2, 413 is a processor control circuit, and 414 is a shared memory.
[0047]
4 will be described. The microcomputer 422, the external memory 431, and the system LSI 424 are connected to each other by external buses o, p, and q. The connection inside the system LSI 424 is equivalent to the connection form in the first and second embodiments, and the details are omitted. However, the newly added download circuit 430 is connected to the 422 micro via the bus interface of the control circuit 401. The computer and the external memory of 431 are connected, and the processor control circuit 413 and the shared memory 414 are also connected via the internal bus c.
[0048]
The power cutoff control operation in the third embodiment configured as described above will be described below. When the power source of the processor 1 or the processor 2 is cut off, the data in the memory is lost if the memory 1 or the memory 2 is a RAM. As a countermeasure, in the above-described embodiment, necessary data is stored in the shared memory.
[0049]
However, not all necessary data can be stored in the shared memory for the convenience of the system. In addition, there are parameters whose values change with the passage of time. If the data is an instruction code, normal system operation is not always possible even if the power supply to the functional circuit block whose power is shut off is resumed.
[0050]
In order to deal with these, data to be transferred to the system LSI when the power is restored is stored in the external memory 431 in advance. The external memory is a separate chip, and the power is not shut off. When restarting the power supply to the LSI, first, the processor 424 is reset, and data required for the operation is downloaded from the external memory to the system LSI 424 by the download control circuit. The data transfer destination may be the shared memory 414 or the memory 1 or the memory 2. While downloading, the core 1 and peripheral circuit 1 of the processor 1 and the core 2 and peripheral circuit 2 of the processor 2 are kept in a reset state.
[0051]
As described above, according to the power shutdown control device in the third embodiment, data including instruction codes can be downloaded from the external memory to the memory in the processor when the system operation is restored. When resuming, the system operation can be resumed without causing a malfunction.
[0052]
【The invention's effect】
As described above, according to the present invention, a system circuit block that realizes a plurality of system functions is configured to include a processor as much as possible, and the operation of the system function system that does not need to be operated is stopped. By providing a power cutoff control circuit that can shut off those power supplies, it is possible to easily control the power cutoff of individual functional circuit blocks, and to reduce the quiescent power supply current in the stop mode to the maximum The effect of being able to be obtained.
[0053]
Furthermore, since each system function is provided with a processor and can handle individual processing, not only power-off control is easy, but also the effect of reducing the development man-hours or period in software development can be obtained.
[0054]
Furthermore, according to the present invention, each system circuit block and each processor circuit is provided in stop mode (when operation is not required) by performing register control from an external computer such as a microcomputer via a system state transition register and a power-off control register. The block power supply can be easily controlled, the static power supply current of the functional circuit block can be reduced when no operation is required, and malfunctions can be achieved even when power supply is resumed (returning operation) by performing register control. The effect that there is nothing is obtained.
[0055]
Further, according to the present invention, the signal indefinite at the interface of both circuit blocks is provided by interposing a leakage current control circuit between the circuit block to which power is supplied in the LSI and the circuit block to which power is cut off. As a result, it is possible to prevent unnecessary leakage current caused by the above-described problem, and to obtain the effect that the quiescent power supply current in the stop mode can be reduced to the maximum.
[0056]
Furthermore, according to the present invention, the power supply to each functional circuit block in each integrated circuit can be controlled by a register from an external computer using a power supply circuit. The effect that the power supply current can be easily reduced is obtained.
[0057]
Furthermore, according to the present invention, when system operation is restored, data can be downloaded from the external memory to the memory in the processor. Therefore, when power supply to the LSI is resumed, system operation can be resumed without causing malfunction. The effect that it can be obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a power shutoff control device according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a power shutoff control device according to a second embodiment of the present invention.
FIG. 3 is a block diagram showing a system configuration example of a set terminal device or the like using the power shutoff control device according to the second embodiment of the present invention.
FIG. 4 is a block diagram showing a configuration of a power shutoff control device according to a third embodiment of the present invention.
FIG. 5 is a block diagram illustrating a configuration example of a system LSI including a conventional processor.
[Explanation of symbols]
101, 201, 401, 501 Control circuit
102, 202, 402, 502 System circuit 1
103, 403, 503 System circuit 2
104, 204, 404, 505 processor
105, 405 Processor 1
106, 406 Processor 2
107, 110, 507 Core circuit
108, 111, 508 peripheral circuit
109, 112, 509 memory
113, 213, 413 Processor control circuit
114, 214, 414 Shared memory
205 Internal processor
215 Bus interface
216 Power-off control register
217 System state transition register
218 Control circuit section
219 Leakage current control circuit
220 Power-off control register in processor
221 Leakage current control circuit in processor
322 microcomputer
323, 325, 327, 329 Register control registers
324 System LSI1
326 System LSI2
328 Power IC
424 System LSI
425 System state transition register and power control register
430 download circuit
431 External memory

Claims (4)

A plurality of functional circuit blocks each including a processor, and a control circuit that individually performs power-off control for the functional blocks that have stopped operating when the operation of any of the functional circuit blocks is stopped; A system state transition register for displaying an operation state of the functional circuit block; a power-off register for instructing the functional circuit block to execute a process at power-off; and an external computer for the system state transition register and the power-off register And an interface for performing register control from an external computer to the functional circuit block indicated by the system state transition register to indicate that the operation is stopped using the power cutoff register It is that power cutoff control device, characterized in that. Connected between a functional circuit block that can be powered off and a functional circuit block that is not subject to power shutdown, and flows to the interface circuit of the functional circuit block that is not subject to power shutdown when the functional circuit block capable of power shutdown is turned off power shutoff control device according to claim 1 Symbol mounting, characterized in that it comprises a leakage current control circuit for preventing leakage current. An integrated circuit including all functional circuit blocks to which power is supplied by a power supply circuit, and the system state transition register and the power cutoff register in the power supply circuit, and the system state transition register and the power cutoff register are all controlled by registers. the via an interface for performing is adapted to be connected to an external computer, according to claim 2 Symbol placing the power shutoff control device and controls the interruption of power supply to each function circuit block from the external computer. Power shutoff control device as claimed in any one of the preceding claims, characterized in that it comprises a download circuit power is downloading data from the external memory power supply resumption time after being shut off 3.

Images