JP2003114742A - Controller for breaking electric power source - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a rest power source current in a stop mode, in a system LSI using a micro-fine process. SOLUTION: In the LSI constituted of a plurality of functional circuit blocks comprising a system circuit and a processor 104, the processors are built in two or more of the functional circuit blocks to serve as the functional circuit blocks operable independently respectively, an electric power source breaking register is provided to command processing in power source breaking to a system condition transition register for displaying the functional circuit block and the functional circuit block, and the power source breaking to the functional circuit block under an operation-stopped condition is controlled individually from an external computer by register control from the external computer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power cutoff control device capable of reducing the power consumption of an LSI, and more particularly to a power cutoff control device for reducing a static power supply current in a system LSI using a fine process. It is a thing.

[0002]

2. Description of the Related Art In recent years, system LSIs have been developed in semiconductor integrated circuits, and the number of transistors mounted on one LSI chip has been increasing more and more. Along with this, finer processes have been used as measures for lowering current consumption and lowering prices. However, 0.25
In a fine process of μm or less, the leak current of each transistor increases, and the increase of the static power supply current when the operation of the LSI is stopped (stop mode) has become a non-negligible value.

Particularly in battery-powered portable terminal equipment, the LSI is normally in the stop mode during standby, but due to the increase in the static power supply current, driving time as a set and current consumption become a problem. There is.
Therefore, in the LSI for mobile terminal devices, not only is the current consumption reduced during normal operation (normal mode),
It is necessary to reduce the current consumption in stop mode. Further, in the system LSI, control is complicated and software development is becoming very difficult due to the complexity of the system and the remarkable increase in the circuit scale.

Conventional system LS with a built-in processor
An example of the configuration of I is shown in the block diagram of FIG. In FIG.
Reference numeral 501 is a control circuit for controlling stop of circuit operation and supply of clock in the stop mode, 502 is a system circuit 1 related to a specific system function, 503 is a system circuit 2 related to another specific system function, and 505 is a processor circuit. Blocks 507, 508, and 509 are a processor core, a peripheral circuit, and a memory built in the processor circuit block 505, respectively.

In the configuration of FIG. 5, the control circuit 501 is
The system circuit 1, the system circuit 2, and the processor circuit block are connected to each other by a signal line a, a signal line b, and a signal line c that are composed of input and output signals, respectively. Also,
The system circuit 1 and the system circuit 2 are connected to the processor circuit block by a signal line d and a signal line e, which are input and output signals, respectively. In this way, the system circuit 1 is connected to the processor circuit block to realize a specific system function, and the system circuit 2 is connected to the processor circuit block to realize another specific system function.

In such a configuration, the processor issues a stop mode command to the control circuit 501 during standby,
The circuit operation of the peripheral functional circuit block controlled by the processor is stopped. That is, the circuit operation is stopped by resetting the target functional circuit block or stopping the clock supply.

[0007]

Since the conventional measures for reducing the quiescent power supply current are merely to reduce the current consumption by stopping the circuit, measures against the increase in the leakage current of the transistor due to the fine process are taken. There was no 0.
Before the fine process of 25 μm or less was adopted, the leak current of the transistor was negligible.
No measures were needed. However, the progress of the process in recent years is remarkable, and further miniaturization of the process is progressing, and it is an urgent task to reduce the static power supply current due to the increase of the leak current of the transistor due to the fine process.

There is also an LSI in which a plurality of system functions are built in one system LSI. Such L
In SI, since the control relationship of the system is complicated, it is difficult to cut off the power supply of the individual system circuit blocks to control the quiescent power supply current, and even if it is possible, it is difficult to obtain a large effect. In addition, software development has become extremely difficult due to the complexity of the system, and the number of development man-hours is increasing.

The present invention has been made in view of the above circumstances, and provides a power shutoff control device capable of reducing the quiescent power supply current in the stop mode in a system LSI using a finer process. With the goal. Another object of the present invention is to provide an LSI configuration method capable of reducing the number of software development steps or period.

[0010]

In order to solve this problem, a power shutoff control device according to claim 1 of the present invention comprises a plurality of processors (processor 1: processor 2), each of which is capable of independent operation. A control circuit that individually controls power supply to the functional circuit blocks (system circuit 1, processor 104: system circuit 2, processor 104) when the operation of any of the functional circuit blocks is stopped. It is provided with (control circuit 101).

According to the power cutoff control device of the first aspect, even in a complicated system LSI having a plurality of system functions built therein, the system circuit blocks for realizing the respective system functions are provided with processors within a possible range. It is configured to include the power supply cutoff control circuit that can stop the operation of the system function system that does not need to operate and cut off the power supply individually, thus maximizing the quiescent power supply current in the stop mode. It can be reduced to the limit.

Furthermore, since a processor is provided for each system function and individual processing can be supported, not only power cutoff control is easy, but also development man-hours or period can be reduced in software development. It is possible to obtain various effects.

According to a second aspect of the present invention, there is provided a power shutoff control device according to the first aspect, in which the system state transition register for displaying the operating state of the functional circuit block and the power source for the functional circuit block are provided. A power shutoff register for instructing processing at shutoff, and an interface for register control of the system state transition register and the power shutoff register from an external computer may be provided, and the system state transition register may suspend the operation. With respect to the displayed functional circuit block, the power cutoff can be controlled from an external computer by using the power cutoff register.

According to another aspect of the power shutoff control device of the present invention, register control is performed from an external computer such as a microcomputer via the system state transition register and the power shutoff control register, so that the stop mode (when no operation is required) is performed. The power supply to each system circuit block and each processor circuit block can be easily controlled, and the quiescent power supply current of the functional circuit block when the operation is unnecessary can be reduced. Further, by performing the register control, it is possible to obtain an effect that no malfunction occurs even when the power supply is restarted (when the operation is restored).

According to a third aspect of the present invention, there is provided a power shutoff control device according to the first or second power shutoff control device, wherein the functional circuit block capable of shutting off the power supply and the functional circuit block not subject to power shutoff. A leak current control circuit for preventing a leak current flowing through an interface circuit of a functional circuit block that is not the target of power shutdown is interposed when the power of the functional circuit block capable of power shutdown is shut off.

According to the power cutoff control device of the third aspect, by interposing the leak current control circuit between the circuit block in which power is supplied and the circuit block in which power is cut off in the LSI, Since it is possible to prevent an unnecessary leak current due to an uncertain signal in the interfaces of both circuit blocks, it is possible to reduce the quiescent power supply current in the stop mode to the maximum.

According to a fourth aspect of the present invention, there is provided a power shutoff control device according to the second or third aspect, wherein all integrated circuits to which power is supplied by a power source circuit in a set terminal device and the like. The circuit is equipped with a system state transition register and a power cutoff register, and these registers are all configured to be connected to an external computer through an interface for register control. It is possible to control the register from.

According to the power cutoff control device of the present invention, since the power cutoff of each functional circuit block in each integrated circuit can be controlled by a register from an external computer using the power supply circuit, set terminal equipment is provided. With such a configuration, the static power supply current and the operating power supply current can be easily reduced.

According to a fifth aspect of the present invention, in the power shutoff control device according to any one of the first to fourth aspects, when the power supply is restarted after the power is shut down, an external memory is used. It is provided with a download circuit that makes it possible to download data.

According to the power shutoff control device of the fifth aspect, when the system operation is restored, the data including the instruction codes can be downloaded from the external memory to the memory in the processor, so that the power supply to the LSI is restarted. At times, system operation can be resumed without causing a malfunction.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of a power interruption control device according to Embodiment 1 of the present invention. In FIG. 1, 101 is a control circuit, 102 is a system circuit 1, 103 is a system circuit 2, and 104 is a combined processor. 1 in the processor 104
Reference numeral 05 is a single processor 1, and reference numeral 106 is a single processor 2. Further, 107, 108, and 109 denote a core circuit 1, a peripheral circuit 1, and a peripheral circuit 1 included in the processor 1, respectively.
The memory 1. Further, 110, 111, and 112 are a core circuit 2, a peripheral circuit 2, and a memory 2 included in the processor 2, respectively. Further, 113 and 114 are a processor control circuit and a shared memory included in the processor 104, respectively.

Explaining the connection relationship between the respective constituent elements of FIG. 1, the control circuit 101 includes a system circuit 1, a system circuit 2, and a processor 104, and a signal line a, a signal line b, and a signal which are input and output signals, respectively. Connected by line c. Here, the signal line c is a signal line mainly connected between the processor control circuit 113 and the shared memory 114. The system circuit 1 is connected to the processor 1 by a signal line d including input and output signals, and the system circuit 2 is connected to the processor 2 by a signal line e including input and output signals. Although not shown, the processor control circuit 113 and the shared memory 114 are respectively
It is connected to the processor 1 and the processor 2.

The power cutoff control operation in the first embodiment configured as described above will be described below. The system circuit 1 is controlled by the processor 1 and the control circuit 101, and the system circuit 2 is controlled by the processor 2 and the control circuit 101.
It is possible to realize each system function and operate independently of each other. When operating the system circuit 1 and the system circuit 2 in parallel, the control circuit 101
The processor 1 and the processor 2 are controlled by using the processor control circuit 113 and the shared memory 114.

When the system circuit 1 is operated and the system circuit 2 is not required to operate, the system circuit 2 is operated.
The processor 2 can stop the circuit operation and enter the stop mode to cut off the power supply to these circuit blocks and reduce the leak current of the transistor. Further, data that is desired to be prevented from disappearing due to the power shutdown can be saved in the shared memory 114 when the power is shut down. The control circuit 101 and the processor control circuit 113 control the return of the operation when the power supply is restarted.

The same applies when the system of the system circuit 2 is operated and the operation of the system of the system circuit 1 is unnecessary. Further, when the operation of both systems of the system circuit 1 and the system circuit 2 is unnecessary, power is supplied only to the control circuit 101, the processor control circuit 113, and the shared memory 114, and the power of other functional circuit blocks is supplied. It can be shut off. At this time, the data that should be prevented from disappearing can be saved in the shared memory 114 when the power is cut off. The control circuit 101 and the processor control circuit 113 control the return of the operation when the power supply is restarted.

As described above, according to the circuit configuration of the power shutoff control device of the first embodiment, compared with the conventional system LSI configured by a single processor and a system circuit for realizing each system function, Because it is configured to include a processor in the system circuit that realizes the system function of, the operation of the system of the system function that does not require operation is stopped, and the power cutoff control circuit that can individually cut off the power supply is provided, The static power supply current in the stop mode can be reduced to the maximum.

In particular, control such as power-off, which requires consideration of operation timing, cannot be properly controlled without a processor that can handle it. In order to recover the system from power interruption in a short time, a functional circuit block in which power is always supplied in the processor is required. At this time, the operating one side processor can also be used for control and processing.

Further, with the configuration of the present embodiment, the performance and memory scale of the processor included in the system circuit that realizes each system function can be set to the optimum circuit scale that suits each system function. Therefore, the increase in chip size can be suppressed to a minimum.

In particular, in the case of an LSI that is used in a mobile phone and that repeats a stop mode and a normal mode periodically, or an LSI and a set terminal device that include a plurality of communication systems, the power control of the LSI is facilitated and the static power supply current is reduced. Not only the effect of reducing the cost, but also by providing a processor in the system circuit that realizes each system function, providing an environment that facilitates software development and reducing the development man-hour or period. You can

(Embodiment 2) FIG. 2 is a block diagram showing a configuration of a power shutoff control device according to Embodiment 2 of the present invention. In FIG. 2, 201 is a control circuit, 202 is a system circuit, 204 is a processor, 205 is an internal processor unit, 213 is a processor control circuit, and 214 is a shared memory.
01, system circuit 102, processor 104, processor 1 (105), processor control circuit 113, and shared memory 114.

Further, as a component of the control circuit 201, 215 is a bus interface circuit, 216 is a power cutoff control register, 217 is a system state transition register, and 218 is a control circuit section. Reference numeral 219 is a leak control circuit, and 220 is a power cutoff control register and 221 is a leak control circuit as a part of the processor 204.

Explaining the connection relationship between the respective constituent elements of FIG. 2, the bus interface circuit 215 includes a power cutoff control register 216 and a system state transition register 217.
Signal lines f and g are connected to each other, and are connected to a microcomputer (not shown) by an external bus n. The system state transition register 217 is also connected to the output of the processor control circuit 213 by a signal line m.

The output of the power shutoff control register 216 is output from the control circuit section 218 and the leak control circuit 2 by the signal line h.
It is connected to 19. The input of the leak control circuit 219 is connected to the output of the system circuit 202 by the signal line j, and further connected to the power supply potential VDD or VSS. The output of the leak control circuit 219 is connected to the input of the control circuit section 218 by the signal line k, and the output of the control circuit section 218 is connected to the system circuit 202 by the signal line i.

The power cutoff control operation in the second embodiment configured as described above will be described below. The control circuit unit 201 and the leak control circuit 219 are circuit blocks to which power is always supplied. In the processor 204, the internal processor unit 205 (core, peripheral circuit, memory) is a circuit block whose power is cut off when operation is unnecessary, and includes a processor control circuit 213 for controlling a plurality of processors and functional circuit blocks, a shared memory 214, The power shutdown control register 220 is a circuit block to which power is always supplied. The system circuit 202 is also a block whose power is cut off when the operation is unnecessary.

Whether or not the system circuit 202 or the like is in the stop mode (operation unnecessary state) in the LSI,
Usually, the processor 204 or the like corresponding to each system circuit can be known including information from the outside. for that reason,
The current information of the system circuit 202 is transferred from the processor control circuit 213 to the system state transition register 217.

The microcomputer refers to the system state transition register 217 through the bus interface circuit 215 at every certain timing. System LSI
When a specific system system is in the stop mode (operation unnecessary state), the microcomputer executes via the bus interface 215 in order to execute the power supply cutoff control of the unnecessary system circuit and the corresponding processor unit. An instruction is written in the power shutoff control registers 216 and 220 to prepare for power shutoff.

Actually, the power supply is cut off by the external power supply IC. Therefore, by writing the instruction in the power supply cut-off control register, the preprocessing required for the power supply cutoff is executed in each functional circuit block. For example, within the processor 204, data that is not desired to be erased needs to be transferred to the shared memory 214. Shared memory 214
Is a circuit block that is always supplied with power,
It is possible to retain data when the power is cut off. Further, for the system circuit 202, the control circuit unit 218
It is possible to prepare for the power-off by the control signal line i from.

After the power is cut off, it may be necessary to take measures against the leak current of the signal connected between the power-off circuit block and the power-supplied circuit block. At that time, for example, the leak control circuit 219 is controlled by the control signal line h from the power cutoff control register 216, and the potential of the input signal line k to the control circuit 201 which is a circuit block to which power is supplied becomes VDD or VSS. Make it fixed. The leak control circuit 221 in the processor 204 has a similar function.

As described above, according to the power shutdown control apparatus of the second embodiment, each system circuit is controlled in the stop mode (when no operation is required) by the power shutdown control from the microcomputer via the power shutdown control register. It is possible to easily control the power-off of each processor and reduce the quiescent power supply current of the functional circuit block when the operation is unnecessary. Further, there is an effect that no malfunction occurs even when the power supply is restarted (when the operation is restored).

FIG. 3 is a block diagram showing an example of the system configuration of a set terminal device or the like using the power shutoff control device of the second embodiment. In FIG. 3, 322 is a microcomputer, 323 is a power-off control register and system state transition register in the microcomputer 322,
Reference numeral 24 is a system LSI 1, 325 is a power shutdown control register and system state transition register in the system LSI 1,
326 is the system LSI 2 and 327 is the system LSI 2
A power cutoff control register and a system state transition register 328, a power supply IC 328, and a power cutoff control register and a system state transition register 329 in the power supply IC 328.

The connection relationship between the respective constituent elements of FIG. 3 will be described. The microcomputer 322, the system LSI 1,
A plurality of VDD side power supplies (VD
D1 to VDD6) are supplied from the power supply IC 328. The registers 325, 327, and 329 are controlled by the microcomputer 322 via the external bus (Re
ad / Write).

The operation of the system configured as above will be described. First, when starting up the system, power supply I
Power is supplied to each LSI from C328, and each LSI starts operation. After that, when the set terminal enters the stable state of the system, a system LSI having a plurality of system controls
1. The system LSI 2 determines the operation mode in which the state transition should be performed based on the input data and writes the requested operation mode in the system state transition registers in 325 and 327, respectively.

The microcomputer 322 which manages the system of the set terminal reads the information written in the system state transition register in 325 and 327, and 3
Each control information is written in the power cutoff control register in 25 and 327. Each LSI prepares for power-off of the operation unnecessary circuit section according to the control information written in the power-off control register. For example, the data which is not desired to be erased is transferred to the memory whose power is not shut off. At the same time, the microcomputer 322 writes the control information in the power cutoff control register in the 329 of the power IC 328. The power supply IC 328 controls the power supplies VDD1 to VDD6 of the microcomputer 322, the system LSI 1, and the system LSI 2 according to the control information, and shuts off the power supply to the LSI circuits that do not require operation.

As described above, according to the system of this configuration example, the power supply cutoff control of the internal circuit of each LSI in the set terminal can be easily realized, and the LSI internal circuit power supply is cut off in the stop mode (no operation is required). The LSI static power supply current can be reduced. Moreover, the system can be restored without any problem even when the system is restored by restarting the power supply.

(Embodiment 3) FIG. 4 is a block diagram showing the configuration of a power interruption control device according to Embodiment 3 of the present invention. In FIG. 4, 422 is a microcomputer,
Reference numeral 431 is an external memory, and 424 is a system LSI.
In the system LSI 424, 401 is a control circuit,
430 is a download circuit, 425 is a power shutoff control register, 402 is a system circuit 1, 403 is a system circuit 2 and 404 is a combined processor. Further, in the processor 404, 405 is a single processor 1, 406 is a single processor 2, 413 is a processor control circuit, and 414 is a shared memory.

The connection relationship between the components shown in FIG. 4 will be described. The microcomputer 422, the external memory 431,
The system LSIs 424 are connected to each other by external buses o, p, and q. The connection inside the system LSI 424 is the same as the connection form in the first and second embodiments, and therefore the details thereof will be omitted. However, the newly added download circuit 430 is connected to the control circuit 401 via the bus interface, and the 422 micro Computer and 43
1 is also connected to the external memory, and is also connected to the processor control circuit 413 and the shared memory 414 via the internal bus c.

The power shutoff control operation in the third embodiment configured as described above will be described below. If the power of the processor 1 or the processor 2 is cut off, the data in the memory is lost if the memory 1 or the memory 2 is a RAM. As a countermeasure, in the above-described embodiment, necessary data is stored in the shared memory.

However, not all necessary data can be stored in the shared memory due to the convenience of the system. There are also parameters whose values change with the passage of time, and if the data is instruction codes, normal system operation may not always be possible even if the power supply to the functional circuit block whose power is cut off is restarted.

In order to deal with these problems, the data to be passed to the system LSI when the power is restored is stored in the external memory 431 in advance. The external memory is a separate chip and the power is never shut off. When the power supply to the LSI is restarted, first, the processor 424 is reset, and the download control circuit downloads the data necessary for the operation from the external memory to the system LSI 424. The data transfer destination may be the shared memory 414, the memory 1 or the memory 2. During the download, the core 1 and the peripheral circuit 1 of the processor 1 and the core 2 and the peripheral circuit 2 of the processor 2 are reset.

As described above, according to the power shutoff control device of the third embodiment, data including instruction codes can be downloaded from the external memory to the memory in the processor when the system operation is restored. When the power supply is restarted, the system operation can be restarted without causing a malfunction.

[0052]

As described above, according to the present invention,
Power supply cutoff that configures the system circuit block that realizes multiple system functions to include the processor as much as possible, stops the operation of the system function system that does not require operation, and cuts off the power supply individually By providing the control circuit, it is possible to easily perform the power supply cutoff control of the individual functional circuit blocks, and it is possible to obtain the effect that the static power supply current in the stop mode can be reduced to the maximum extent.

Further, since a processor is provided for each system function and individual processing can be supported, not only power shutoff control is easy, but also development man-hours or period can be reduced in software development. To be

Further, according to the present invention, by performing register control from an external computer such as a microcomputer via the system state transition register and the power cutoff control register, each system circuit block in the stop mode (when no operation is required), The power supply to each processor circuit block can be easily controlled, the quiescent power supply current of the functional circuit block can be reduced when operation is unnecessary, and register control can be performed to restart power supply (when operation is restored). It is possible to obtain the effect that there is no malfunction.

Further, according to the present invention, by interposing the leak current control circuit between the circuit block in which power is supplied and the circuit block in which power is cut off in the LSI, the interface of both circuit blocks is provided. It is possible to prevent an unnecessary leak current due to the signal indefiniteness in 1), and it is possible to obtain the effect of maximally reducing the quiescent power supply current in the stop mode.

Furthermore, according to the present invention, since the power supply to each functional circuit block in each integrated circuit can be controlled by a register from an external computer using a power supply circuit, a stationary power supply is used in the configuration of a set terminal device or the like. The effect is that the current and the operating power supply current can be easily reduced.

Further, according to the present invention, when the system operation is restored, the data can be downloaded from the external memory to the memory in the processor. Therefore, when the power supply to the LSI is restarted, the system operation is restarted without causing a malfunction. The effect of being able to do is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a power shutdown control device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a power shutdown control device according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a system configuration example of a set terminal device or the like using the power shutdown control device according to the second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a power shutdown control device according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration example of a conventional system LSI having a built-in processor.

[Explanation of symbols]

101, 201, 401, 501 Control circuit 102, 202, 402, 502 System circuit 1 103, 403, 503 System circuit 2 104, 204, 404, 505 Processor 105, 405 Processor 1 106, 406 Processor 2 107, 110, 507 Core circuit 108, 111, 508 Peripheral circuit 109, 112, 509 Memory 113, 213, 413 Processor control circuit 114, 214, 414 Shared memory 205 Internal processor section 215 Bus interface 216 Power shutdown control register 217 System state transition register 218 Control circuit 219 Leakage current control circuit 220 Power cutoff control register 221 in processor Leakage current control circuit 322 in processor Microcomputer 323, 325, 327, 329 Register for register control 324 System LSI1 326 System LSI2 328 Power supply IC 424 System LSI 425 System state transition register and power supply control register 430 Download circuit 431 External memory

Claims (5)

[Claims] 1. A plurality of functional circuit blocks each of which is capable of operating independently, and when any one of the functional circuit blocks stops operating, the power-off control is individually performed on the stopped functional block. A power shutoff control device comprising a control circuit. 2. A system state transition register for displaying an operation state of the functional circuit block, a power shutoff register for instructing the functional circuit block to perform processing at power shutoff, the system state transition register and the power shutoff. An interface for controlling registers from an external computer, and shutting off power to the functional circuit blocks indicated by the system state transition register by the power shutoff register. 2. The power cutoff control device according to claim 1, wherein the power is cut off from an external computer. 3. A functional circuit block that is connected between a functional circuit block capable of power shutdown and a functional circuit block not subject to power shutdown, and is not subject to power shutdown when the functional circuit block capable of power shutdown is powered off. 3. The power interruption control device according to claim 1, further comprising a leak current control circuit for preventing a leak current flowing through the interface circuit. 4. An integrated circuit to which power is supplied by a power supply circuit and the system state transition register and the power cutoff register are provided in the power supply circuit, and the system state transition register and the power cutoff register are all register controlled. 4. The power shutoff control device according to claim 2, wherein the power shutoff control device is configured to be connected to an external computer via an interface for performing the above, and shuts off power to each functional circuit block from the external computer. 5. The power cutoff control device according to claim 1, further comprising a download circuit that downloads data from an external memory when power supply is restarted after the power is cut off. .