JP2006337099A - Testing arrangement - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a testing arrangement supplying test signal of proper voltage accordingly to the specification of the input terminal of a tested device. <P>SOLUTION: The testing arrangement comprises a pattern generator generating the first and the second test pattern supplying to the device to be tested at every test period, the first and the second delay parts for outputting the first and the second delay signals in which the signals based on the first and the second test patterns are delayed for the specified time, a selector for selecting whether multiplex signals that the first testing signal based on the first delay signal and the second testing signal based on the second delay signal is multiplexed are output or the first testing signal of normal voltage based on the first delay signal and the second testing signal of high voltage based on the second delay signal are supplied, and a signal input/output part supplying the input terminal in connection end with the first and the second testing signals at the voltages according to the selection result. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a test apparatus. In particular, the present invention relates to a test apparatus that supplies a test signal having an appropriate voltage level according to the specifications of an input terminal of a device under test.

  In general, the input terminal of the semiconductor device has a specification for inputting one of a predetermined high level voltage VIH and low level voltage VIL. Therefore, the conventional test apparatus allocates hardware resources capable of generating two voltage levels for each input terminal of the device under test for the purpose of testing such a semiconductor device as the device under test. More specifically, for each input terminal, a test pattern is generated by a pattern generation circuit, a test pattern is waveform-shaped by a waveform shaping circuit, a binary test signal that changes at a predetermined timing is generated, and a test is performed by a driver. The signal is amplified and supplied to the device under test as a level signal having a predetermined voltage level.

  On the other hand, in addition to the first high level voltage VIH and the low level voltage VIL, a second high level voltage VIHH higher than the first high level voltage VIH is input to the input terminal of a memory device such as a flash memory. There are things that take specifications. In testing such a semiconductor device, the test apparatus must generate one of three voltage levels depending on the test pattern.

  In the conventional test apparatus, two sets of pattern generation circuits and waveform shaping circuits for generating a binary test signal are prepared for each input terminal for the purpose of corresponding to the input terminals having such specifications. Whether to supply the first high level voltage VIH and whether to supply the second high level voltage VIHH is controlled.

  In addition, since the presence of a prior art document is not recognized at this time, the description regarding a prior art document is abbreviate | omitted.

  Assuming various devices under test, a conventional test apparatus needs to include the above two sets of pattern generation circuits and waveform shaping circuits corresponding to at least some of the input terminals. Therefore, the hardware scale of the test apparatus is larger than when only binary input terminals are targeted. When the input terminal is connected to a binary input, the second pattern generation circuit and waveform shaping circuit are not required and are not effectively used.

  Accordingly, an object of the present invention is to provide a test apparatus that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

  According to a first aspect of the present invention, there is provided a test apparatus for testing a device under test, wherein the pattern generator generates a first test pattern and a second test pattern to be supplied to the device under test for each test cycle. A first delay unit that outputs a first delay signal obtained by delaying a signal based on the first test pattern for a specified time, and a second delay signal obtained by delaying the signal based on the second test pattern for a specified time A second delay unit that outputs a multiplexed signal obtained by multiplexing the first test signal based on the first delayed signal and the second test signal based on the second delayed signal within the test period, or A first selector for selecting whether to output the first test signal based on a first delay signal; and a second selector based on the second delay signal when the first selector outputs the multiplex signal. A second selection unit that outputs the test signal, and outputs a signal for supplying a low level voltage to the device under test when the first selection unit outputs the first test signal; A first driver that amplifies the signal output from the first selection unit so as to be a predetermined first high-level voltage and supplies the amplified signal to a predetermined input terminal of the device under test; and the second selection When the second test signal is output from the unit, the second test signal is amplified so that the high level voltage becomes a second high level voltage higher than the first high level voltage, and the device under test There is provided a test apparatus including a second driver that supplies the predetermined input terminal.

  The second driver at a test cycle end timing, provided that a high voltage mode is selected in which the first test signal is supplied from the first driver and the second test signal is supplied from the second driver. In response to the output of the second test pattern for outputting the second high-level voltage from the pattern generator, the signal supplied to the second delay unit is transmitted at the end timing of the test cycle. You may further provide the waveform shaper which changes the output of a driver into the signal which switches to a low level voltage.

  The waveform shaper includes a first set signal indicating whether to set the first test signal to a high level and a first reset signal indicating whether to set the low level based on the first test pattern. , A second set signal indicating whether or not the second test signal is set to a high level based on the second test pattern, and a second indicating whether or not the second test signal is set to a low level. And a second waveform shaping circuit that outputs a reset signal, wherein the first delay unit includes a delay time of the set signal and a delay time of the reset signal in which the first set signal and the first reset signal are designated. The delayed first delay set signal and the first delay reset signal are output, and the second delay unit includes a delay time and a reset signal of the set signal in which the second set signal and the second reset signal are designated. A second delay set signal and a second delay reset signal delayed by a delay time are output, and the first selection unit becomes a logical value H when the high voltage mode is selected, and the high voltage mode is selected. A first AND gate that outputs a logical product of a logical negation of a high voltage selection signal that becomes a logical value L when not present and the second delay set signal; a logical negation of the high voltage selection signal and the second delayed reset signal; A second AND gate that outputs a logical product of the first AND gate, a first OR gate that outputs a logical sum of the output of the first delay set signal and the output of the first AND gate, the output of the first delay reset signal, and the A second OR gate that outputs a logical sum of the outputs of the second AND gate, and an output connected to the first driver and set by the output of the first OR gate; A first flip-flop that is reset by an output, wherein the second selection unit outputs a third AND gate that outputs a logical product of the high voltage selection signal and the second delay set signal, and the high voltage selection. A fourth AND gate that outputs a logical product of a signal and the second delayed reset signal, and an output connected to the second driver, set by the output of the third AND gate, and output by the fourth AND gate And a second flip-flop to be reset.

  The above summary of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

  ADVANTAGE OF THE INVENTION According to this invention, the test apparatus which supplies the test signal of a suitable voltage according to the specification of the input terminal of a device under test can be provided.

  Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the scope of claims, and all combinations of features described in the embodiments are included. It is not necessarily essential for the solution of the invention.

  FIG. 1 shows a configuration of a test apparatus 10 according to this embodiment together with a DUT 100. The DUT 100 (Device Under Test: device under test) may be a memory device such as a flash memory, and may be a logic IC or a logic LSI. The test apparatus 10 according to the present embodiment tests the DUT 100 and includes a plurality of sets of PDSs 118, a waveform shaping circuit 124, a delay unit 130, and a selection unit 140 corresponding to at least one input terminal of the DUT 100. . Then, the test apparatus 10 supplies the DUT 100 with a high voltage mode that supplies three or more voltage levels including the first high level voltage VIH and the low level voltage VIL, and the second high level voltage VIHH higher than the first high level voltage VIH. The first set supplies the first high level voltage VIH or the low level voltage VIL, and the second set supplies the second high level voltage VIHH or the low level voltage VIL. On the other hand, in the operation mode in which either the first high level voltage VIH or the low level voltage VIL is supplied to the input terminal, the test apparatus 10 outputs a test signal by interleaving two sets of hardware resources. Accordingly, the test apparatus 10 can supply test signals at high speed by effectively using two sets of hardware resources. This operation mode is hereinafter referred to as “high speed mode”.

  The test apparatus 10 includes a period generator 112, a pattern generator 114, a waveform shaping unit 120, a signal input / output unit 160, and a determination unit 170 as hardware resources that can operate in a high-speed mode or a high-voltage mode. Corresponding to one input terminal of the DUT 100. The period generator 112 generates a test rate clock that serves as a reference for operating each unit in the test apparatus 10 during the test of the DUT 100. Thereby, the period generator 112 determines the period (test period) of each test cycle included in the test. The cycle generator 112 may have the same length for each test cycle, or a different length for each test cycle.

The pattern generator 114 generates a first test pattern and a second test pattern to be supplied to the DUT 100 at each test cycle determined by the cycle generator 112. The pattern generator 114 outputs a high voltage selection signal HVMODE that specifies whether or not to supply a signal to the corresponding input terminal in the high voltage mode. The high voltage mode signal has a logical value H when the high voltage mode is selected, and has a logical value L when the high voltage mode is not selected and the high speed mode is selected. As an example, the high voltage selection signal HVMODE is specified by writing a set value in the mode register of the pattern generator 114 in the test program of the test apparatus 10.
Further, the pattern generator 114 generates an expected value of the output signal of the DUT 100 and supplies it to the determination unit 170.

  The pattern generator 114 includes an APLG 116 and PDS 118 (118a, b). An APLG 116 (Algorithmic Pattern Generator) generates pattern data that is a source of a test signal supplied to the DUT 100 based on a predetermined algorithm for each test cycle. When the DUT 100 is a memory device, the APLG 116 generates pattern data including a bit string such as a memory address, memory data, and a control signal value, for example.

  A PDS 118a (Pattern Data Selector) selects a bit to be supplied to a corresponding input terminal from a bit string of pattern data for each test cycle, and outputs the selected bit to the waveform shaping unit 120 as a first test pattern. For example, when supplying a test signal to the address terminal A0, the PDS 118 selects and outputs a bit corresponding to the address A0 from the pattern data generated by the APLG 116. The PDS 118b has the same function and configuration as the PDS 118a, selects a bit to be supplied to the corresponding input terminal for each test cycle, and outputs the selected bit to the waveform shaping unit 120 as a second test pattern.

  The waveform shaping unit 120 includes a waveform shaper 122, delay units 130a and 130b, a delay setting memory 136, and selection units 140a and 140b. The waveform shaper 122 shapes the test pattern input from the pattern generator 114 and outputs a waveform-shaped signal based on the test pattern to the delay units 130a and 130b. The waveform shaper 122 includes waveform shaping circuits 124a-b.

  The waveform shaping circuit 124a shapes the first test pattern and outputs a signal based on the first test pattern. The waveform shaping circuit 124a according to the present embodiment, based on the first test pattern, the first set signal indicating whether or not the first test signal is set to the high level and the first indicating whether or not the first test signal is set to the low level. A reset signal is output. More specifically, the waveform shaping circuit 124a sets the first set signal to a logical value H when the first test signal is set to a high level, and sets the first reset signal to a logical value when the first test signal is set to a low level. Let H be. Further, the waveform shaping circuit 124a sets the timing for setting the first test signal to the high level and the timing for setting the first test signal to the low level to the timing information designated by the pattern generator 114 and / or the waveform shaper 122 in advance. Determine based on the set timing information and output. In the present embodiment, the waveform shaping circuit 124a determines which delay data the first set signal is delayed from among a plurality of delay data stored in the delay setting memory 136 based on the timing information, and Each delay data is designated based on which delay data.

  The waveform shaping circuit 124b shapes the second test pattern and outputs a signal based on the first test pattern. The waveform shaping circuit 124b according to the present embodiment, based on the second test pattern, a second set signal indicating whether or not the second test signal is at a high level and a second signal indicating whether or not the second test signal is at a low level. A reset signal is output. Since the waveform shaping circuit 124b has the same function and configuration as the waveform shaping circuit 124a, description thereof will be omitted except for the following differences.

  The delay unit 130a outputs a first delay signal obtained by delaying a signal based on the first test pattern for a specified time. The delay unit 130a includes a set side delay circuit 132a and a reset side delay circuit 134a. The set-side delay circuit 132a outputs a first delay set signal obtained by delaying the first set signal by the delay time of the set signal designated by the waveform shaping circuit 124a. More specifically, the delay unit 130a reads the delay data selected for the set signal by the waveform shaping circuit 124a from the delay setting memory 136, and delays the first set signal by a delay time corresponding to the delay data. The reset delay circuit 134a outputs a first delay reset signal obtained by delaying the first reset signal by the delay time of the reset signal designated by the waveform shaping circuit 124a. More specifically, the delay unit 130b reads the delay data selected for the reset signal by the waveform shaping circuit 124a from the delay setting memory 136 in the same manner as the delay unit 130a, and sets the first delay time corresponding to the delay data. 1 Delay the reset signal.

  The delay unit 130b outputs a second delay signal obtained by delaying a signal based on the second test pattern for a specified time. The delay unit 130b has the same function and configuration as the delay unit 130a, and the set side delay circuit 132b and the reset side delay circuit 134b in the delay unit 130b correspond to the set side delay circuit 132a and the reset side delay circuit 134a, respectively. Therefore, the description will be omitted except for the following differences.

  The selection unit 140a outputs a multiplexed signal obtained by multiplexing the first test signal based on the first delay signal and the second test signal based on the second delay signal to the DUT 100 within the test cycle, or selects the first delay signal as the first delay signal. It is selected whether to output the first test signal based on it. That is, when the high voltage mode is selected, the selection unit 140a generates and outputs a first test signal from the first delay signal including the first delay set signal and the first delay reset signal. On the other hand, when the high-speed mode is selected, the selection unit 140a generates a multiplexed signal by superimposing the first test signal corresponding to the first delay signal and the second test signal corresponding to the second delay signal. Output. Thereby, the selection unit 140a includes the first test signal based on the first delay signal generated by the PDS 118a, the waveform shaping circuit 124a, and the delay unit 130a, the PDS 118b, the waveform shaping circuit 124b, and the delay within one test cycle. Two test signals, which are the second test signal based on the second delay signal generated by the unit 130b, can be supplied to the input terminal of the DUT 100.

  The selection unit 140a includes an AND gate 142, an AND gate 144, an OR gate 146, an OR gate 148, and an FF 150a. The AND gate 142 is a logic element that outputs a logical product of the logical negation of the high voltage selection signal and the second delay set signal. Accordingly, the AND gate 142 outputs the second delay set signal when the high speed mode is selected, and outputs the logical value L while masking the second delay set signal when the high voltage mode is selected. The AND gate 144 is a logic element that outputs a logical product of the logical negation of the high voltage selection signal and the second delayed reset signal. As a result, the AND gate 144 outputs the first delay reset signal when the high-speed mode is selected, and outputs the logical value L while masking the first delay reset signal when the high-voltage mode is selected.

  The OR gate 146 is a logic element that outputs a logical sum of the output of the first delay set signal and the output of the AND gate 142. Accordingly, the OR gate 146 outputs a signal in which the first delay set signal and the second delay set signal are superimposed when the high speed mode is selected, and outputs the first delay set signal when the high voltage mode is selected. .

  The OR gate 148 is a logic element that outputs a logical sum of the output of the first delay reset signal and the output of the AND gate 144. Accordingly, the OR gate 146 outputs a signal in which the first delay reset signal and the second delay reset signal are superimposed when the high speed mode is selected, and outputs the first delay reset signal when the high voltage mode is selected. .

  The output of the FF 150 a is connected to the driver 162 a in the signal input / output unit 160, is set by the output of the OR gate 146, and is reset by the output of the OR gate 148. As a result, the FF 150a outputs the logical value H from when the set signal having the logical value H is input from the OR gate 146 to when the reset signal having the logical value H is input from the OR gate 148. Further, the logic value L is output from the time when the reset signal having the logic value H is input from the OR gate 148 to the time when the set signal having the logic value H is input from the OR gate 146.

  The selection unit 140b outputs a second test signal based on the second delay signal when the selection unit 140a outputs a multiplexed signal, and outputs a low level voltage to the DUT 100 when the selection unit 140a outputs the first test signal. Outputs a signal to supply. That is, when the high voltage mode is selected, the selection unit 140b generates and outputs a second test signal from the second delay signal including the second delay set signal and the second delay set signal. On the other hand, when the high speed mode is selected, the selection unit 140b outputs a logical value L so that the second high level voltage VIHH is not output from the driver 162b in the signal input / output unit 160.

  The selection unit 140b includes an AND gate 152, an AND gate 154, and an FF 150b. The AND gate 152 is a logic element that outputs a logical product of the high voltage selection signal and the second delay set signal. Thereby, the AND gate 152 outputs the second delay set signal when the high voltage mode is selected, and outputs the logical value L when the high speed mode is selected. The AND gate 154 is a logic element that outputs a logical product of the high voltage selection signal and the second delay reset signal. Thereby, the AND gate 154 outputs the second delay reset signal when the high voltage mode is selected, and outputs the logical value L when the high speed mode is selected.

  The output of the FF 150b is connected to the driver 162b, is set by the output of the AND gate 152, and is reset by the output of the AND gate 154. As a result, the FF 150 b outputs the logic value H from when the set signal having the logic value H is input from the AND gate 152 to when the reset signal having the logic value H is input from the AND gate 154. Further, the logic value L is output from the input of the reset signal of the logic value H from the AND gate 154 to the input of the set signal of the logic value H from the AND gate 152.

  The signal input / output unit 160 inputs and outputs signals with the DUT 100. Signal input / output unit 160 includes drivers 162a-b and comparators 164a-b. The driver 162a is provided to output a normal level voltage, amplifies the signal input from the FF 150a in the waveform shaping unit 120, and supplies the amplified signal to the connection destination input terminal. Here, the driver 162a amplifies the signal output from the selection unit 140a so that the high level voltage becomes the predetermined first high level voltage VIH, and supplies the amplified signal to a predetermined input terminal of the DUT 100. More specifically, the driver 162a supplies the low level voltage VIL to the input terminal when the logical value L is input, and supplies the first high level voltage VIH to the input terminal when the logical value H is input. To do.

  The driver 162b is provided to output a high voltage, amplifies the signal input from the FF 150b in the waveform shaping unit 120, and supplies the amplified signal to the connection destination input terminal. Here, when the second test signal is output from the selection unit 140b, the driver 162b amplifies the second test signal so that the high level voltage becomes the second high level voltage VIHH higher than the first high level voltage VIH. Then, the signal is supplied to a predetermined input terminal of the DUT 100. More specifically, the driver 162b supplies the low level voltage VIL to the input terminal when the logical value L is input, and supplies the second high level voltage VIHH to the input terminal when the logical value H is input. To do.

  The comparators 164a and 164b receive the output signal output from the DUT 100 in response to the test signal, and compare it with the high level threshold voltage VthH and the low level threshold voltage VthL, respectively.

  The determination unit 170 receives the comparison results of the comparators 164a and 164b, and compares the output signal of the DUT 100 with the expected value input from the pattern generator 114.

FIG. 2 shows an operation example of the high-speed mode of the test apparatus 10 according to the present embodiment.
In this example, the pattern generator 114 sets the high voltage selection signal HVMODE to a logical value L. Then, a first test pattern and a second test pattern are generated so that a signal obtained by superimposing the first test signal n and the second test signal n is input to the input terminal of the DUT 100 in the test cycle n.

  The waveform shaping circuit 124a has a first set signal indicating that the first test signal is set to the high level at the timing t1 in the test cycle n, and a first reset signal indicating that the first test signal is set to the low level at the timing t2. Is output. Further, the waveform shaping circuit 124b has a second set signal indicating that the second test signal is set to the high level at the timing t3 in the test cycle n, and a second signal indicating that the second test signal is set to the low level at the timing t4. A reset signal is output. In this example, t1 <t2 <t3 <t4.

  Next, the set-side delay circuit 132a in the delay unit 130a delays the first set signal by t1 to generate the first delay set signal (SET1 in the figure). Similarly, the reset-side delay circuit 134a, the set-side delay circuit 132b, and the reset-side delay circuit 134b delay the first reset signal, the second set signal, and the second reset signal by t2, t3, and t4, respectively. The first delay reset signal (RESET1 in the figure), the second delay set signal (SET2 in the figure), and the second delay reset signal (RESET2 in the figure) are generated.

  Since the high voltage selection signal HVMODE has a logical value L, the AND gate 142 and the OR gate 146 in the selection unit 140a receive a set signal (SET1 ′ in the figure) obtained by multiplexing the first delay set signal and the second delay set signal. Generate. Similarly, the AND gate 144 and the OR gate 148 generate a reset signal (RESET1 'in the figure) obtained by multiplexing the first delay reset signal and the second delay reset signal.

  On the other hand, the AND gate 152 and the AND gate 154 in the selection unit 140b mask the second delay set signal and the second delay reset signal and output the logic value L because the high voltage selection signal HVMODE has the logic value L. .

  The FF 150a is set when the set signal SET1 'becomes a logical value H, and is reset when the reset signal RESET1' becomes a logical value H. As a result, the FF 150a can output a signal in which the RZ (Return to Zero) waveform of the first test signal n and the RZ waveform of the second test signal n are superimposed in this example. On the other hand, the FF 150b receives a set signal and a reset signal having a logic value L, and outputs a signal having a logic value L.

  The driver 162a outputs a high level voltage VIH when the signal output from the FF 150a is a logical value H, and outputs a low level voltage VIL when the signal is a logical value L. On the other hand, the driver 162b does not output the second high level voltage VIHH as a result of inputting the signal of the logical value L.

  As described above, in the high-speed mode, the test apparatus 10 uses the PDS 118b, the waveform shaping circuit 124b, and the delay unit 130 that are used to output the second high-level voltage VIHH in the high-voltage mode, and uses the test cycle. A plurality of test signals can be superimposed and supplied to the DUT 100. Further, as shown in the test cycle n + 1 in the figure, when only one test signal is output within the test cycle, a set of the PDS 118a, the waveform shaping circuit 124a, the delay unit 130a, and the selection unit 140a, or Any hardware resource of the set of the PDS 118b, the waveform shaping circuit 124b, the delay unit 130b, and the selection unit 140b can be used.

FIG. 3 shows an operation example in the high voltage mode of the test apparatus 10 according to the present embodiment.
In this example, the pattern generator 114 sets the high voltage selection signal to a logical value H. Then, in the test cycle n, a first test pattern and a second test pattern are generated so that the high level voltage VIH based on the first test signal n and the second high level voltage VIHH based on the second test signal n are input to the DUT 100.

  The waveform shaping circuit 124a and the waveform shaping circuit 124b, and the delay unit 130a and the delay unit 130b are set to the first delay set signal SET1 so as to have the logical value H at the timings t1, t2, t3, and t4, as in FIG. The first delay reset signal RESET1, the second delay set signal SET2, and the second delay reset signal RESET2 are output. In this example, t1 <t3 <t4 <t2.

  The AND gate 142 and the OR gate 146 in the selection unit 140a output the first delay set signal SET1 because the high voltage selection signal HVMODE has a logical value H. Similarly, the AND gate 144 and the OR gate 148 output the first delay reset signal RESET1. On the other hand, the AND gate 152 and the AND gate 154 in the selection unit 140b output the second delay set signal SET2 and the second delay reset signal RESET2 because the high voltage selection signal HVMODE has a logical value H.

  The FF 150a is set when the first delay set signal SET1 becomes the logic value H, and is reset when the reset signal RESET1 becomes the logic value H. As a result, the output Q1 of the FF 150a outputs a logical value H from the timing t1 to t2 in the test cycle n. On the other hand, the FF 150b is set when the second delay set signal SET2 becomes the logic value H, and is reset when the reset signal RESET2 becomes the logic value H. As a result, the output Q2 of the FF 150b outputs a logical value H from the timing T3 to T4 in the test cycle n.

  The driver 162a outputs a high level voltage VIH when the signal output from the FF 150a is a logical value H, and outputs a low level voltage VIL when the signal is a logical value L. On the other hand, the driver 162b outputs the second high-level voltage VIHH when the signal output from the FF 150b is the logical value H, and outputs the low-level voltage VIL when the signal is the logical value L. As a result, the output voltage of the signal input / output unit 160 becomes a higher voltage among the outputs of the driver 162a and the driver 162b. Therefore, in this example, the high level voltage VIH is input to the input terminal between the timings t1 and t2 of the test cycle n, and the second high level voltage VIHH is input to the input terminals between the timings t2 and t3. The high level voltage VIH is input to the input terminal between timings t3 and t4.

  As described above, in the high voltage mode, the test apparatus 10 includes the first test signal having the normal high level voltage VIH and the second high level voltage VIHH higher than the high level voltage VIH in each test cycle. 2 test signals can be supplied. Further, as shown in the test cycle n + 1 in the figure, the set of the PDS 118a, the waveform shaping circuit 124a, the delay unit 130a, and the selection unit 140a has the normal high level voltage VIH, and the second high level voltage VIHH. It is also possible to supply a test signal without

  As described above, the waveform shaper 122 generates the second set signal and the second reset signal so that the output of the driver 162b is always set to the low level voltage VIL at the end timing of the test cycle in the high voltage mode. Good. That is, the waveform shaper 122 indicates that the high voltage mode in which the high voltage selection signal HVMODE is a logical value H, the first test signal is supplied from the driver 162a, and the second test signal is supplied from the driver 162b is selected. As a condition, it operates as follows.

  The waveform shaper 122 is supplied to the delay unit 130b in response to the output of the second test pattern for outputting the second high level voltage VIHH from the driver 162b at the end timing of the test cycle. The two set signals and the second reset signal are changed to signals for switching the output of the driver 162b to a low level voltage at the end timing of the test cycle. As an example, the waveform shaping circuit 124b in the waveform shaper 122 sets the FF 150b at the timing t3, and a second test pattern instructing not to reset the FF 150b until the end timing of the test cycle, that is, an NRZ (Non Return to Zero) waveform. When a second test pattern for designating a signal is input, a second reset signal that resets the FF 150b at a timing later than the timing t3 and closer to the end timing of the test cycle is output to change to the RZ waveform. More specifically, the waveform shaping circuit 124b is designated by the delay data of the latest timing among the plurality of delay data stored in the delay setting memory 136 and selectable by the reset-side delay circuit 134b. At this timing, a second reset signal and timing information that sets the second delayed reset signal to the logic value H are generated and supplied to the delay unit 130b.

  Accordingly, the test apparatus 10 can prevent the second high level voltage VIHH from being continuously supplied to the input terminal of the DUT 100 after the end of each test cycle. Therefore, the test apparatus 10 can prevent the life of the DUT 100 from being shortened as a result of the second high level voltage VIHH being continuously supplied to the input terminal even when there is an error in the test program.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

1 shows a configuration of a test apparatus 10 according to an embodiment of the present invention. The operation example of the high-speed mode of the test apparatus 10 which concerns on embodiment of this invention is shown. The operation example of the high voltage mode of the test apparatus 10 which concerns on embodiment of this invention is shown.

Explanation of symbols

10 Test equipment 100 DUT
112 period generator 114 pattern generator 116 APLG
118a-b PDS
120 Waveform shaping unit 122 Waveform shapers 124a-b Waveform shaping circuits 130a-b Delay units 132a-b Set-side delay circuits 134a-b Reset-side delay circuits 136 Delay setting memories 140a-b Selectors 142, 144 AND gates 146, 148 OR gate 150a-b FF
152, 154 AND gate 160 signal input / output unit 162a-b driver 164a-b comparator 170 determination unit

Claims (3)

A test apparatus for testing a device under test,
A pattern generator for generating a first test pattern and a second test pattern to be supplied to the device under test for each test period;
A first delay unit that outputs a first delayed signal obtained by delaying a signal based on the first test pattern by a specified time;
A second delay unit that outputs a second delayed signal obtained by delaying a signal based on the second test pattern for a specified time;
Within the test period, a multiplexed signal obtained by multiplexing the first test signal based on the first delay signal and the second test signal based on the second delay signal is output, or the first signal based on the first delay signal is output. A first selection unit for selecting whether to output a test signal;
When the first selection unit outputs the multiplexed signal, the second test signal based on the second delay signal is output, and when the first selection unit outputs the first test signal, the device under test is output. A second selection unit that outputs a signal for supplying a low-level voltage to the device;
A first driver that amplifies the signal output from the first selection section so that the high level voltage becomes a predetermined first high level voltage, and supplies the amplified signal to a predetermined input terminal of the device under test; ,
When the second test signal is output from the second selection unit, the second test signal is amplified so that a high level voltage becomes a second high level voltage higher than the first high level voltage, and And a second driver that supplies the predetermined input terminal of the device under test.   The second driver at a test cycle end timing, provided that a high voltage mode is selected in which the first test signal is supplied from the first driver and the second test signal is supplied from the second driver. In response to the output of the second test pattern for outputting the second high-level voltage from the pattern generator, the signal supplied to the second delay unit is transmitted at the end timing of the test cycle. The test apparatus according to claim 1, further comprising a waveform shaper that changes a driver output to a signal for switching to a low level voltage. The wave shaper
Based on the first test pattern, a first waveform for outputting a first set signal indicating whether or not the first test signal is at a high level and a first reset signal indicating whether or not the first test signal is at a low level. Molding circuit,
Based on the second test pattern, a second waveform that outputs a second set signal indicating whether or not the second test signal is at a high level and a second reset signal indicating whether or not the second test signal is at a low level. A molding circuit and
The first delay unit outputs a first delay set signal and a first delay reset signal obtained by delaying the first set signal and the first reset signal by a delay time of a designated set signal and a delay time of the reset signal. ,
The second delay unit outputs a second delay set signal and a second delay reset signal obtained by delaying the second set signal and the second reset signal by a specified set signal delay time and a reset signal delay time. ,
The first selection unit includes:
A logical product of a logical negation of a high voltage selection signal that becomes a logical value H when the high voltage mode is selected and a logical value L when the high voltage mode is not selected and the second delay set signal. A first AND gate to output;
A second AND gate that outputs a logical product of the logical negation of the high voltage selection signal and the second delayed reset signal;
A first OR gate that outputs a logical sum of the output of the first delay set signal and the output of the first AND gate;
A second OR gate that outputs a logical sum of the output of the first delay reset signal and the output of the second AND gate;
A first flip-flop connected to the first driver, set by the output of the first OR gate, and reset by the output of the second OR gate;
The second selection unit includes:
A third AND gate that outputs a logical product of the high voltage selection signal and the second delay set signal;
A fourth AND gate that outputs a logical product of the high voltage selection signal and the second delayed reset signal;
The test apparatus according to claim 2, further comprising: a second flip-flop that has an output connected to the second driver, set by the output of the third AND gate, and reset by the output of the fourth AND gate.

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