JP2006332405A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with a more stable configuration wherein increase in the resistance of hole connected parts for contact holes and via-holes is suppressed independently of the density of a hole pattern and variations in the resistance values are eliminated, and to provide a manufacturing method thereof. <P>SOLUTION: In the semiconductor device, holes 12 each are formed for reaching an optional connection region 10 under an insulation layer 11. A wiring member 13 is embedded to each hole 12 and extended on the insulation layer 11. A wiring member 14 is formed on the wiring member 13 together with upper parts of the holes 12. The wiring members 14 and 13 configure a wiring pattern 16 on the insulation layer 11. The wiring member 13 on the holes 12 is made of, e.g. W, and keeps a prescribed thickness on the insulation layer 11 so as to avoid the occurrence of recess. Thus, the upper part of the holes 12 has a structure wherein a recess is hardly caused. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device having an integrated circuit wiring with a conductive plug formed through a CMP (Chemical Mechanical Polishing) process, and a manufacturing method thereof.

A W (tungsten) plug is known as a wiring embedded in a contact hole or a via hole in a semiconductor integrated circuit. The W plug is formed using a CVD (Chemical Vapor Deposition) method and is excellent in filling a high aspect ratio hole due to high integration. In the W plug, there is a concern that an oxide of a reactive organism at the time of the flattening treatment may increase the resistance of the contact portion with the upper layer wiring. As a conventional countermeasure, a technique of adding a step of removing by reverse sputtering before forming an aluminum layer of an upper wiring is disclosed (for example, see Patent Document 1).
JP 2001-77193 A (page 3, FIG. 1)

  The CMP process is used for the flattening process of the W plug. At this time, depending on the density of holes (contact holes or via holes) that require W plugs, the W embedding pattern differs. For example, in the dense pattern region, the upper portion of the W plug is at the same level as the flattened surface, but in the sparse pattern region, the upper portion of the W plug is lower than the flattened surface and a recess (dent) occurs.

  There is a possibility that slurry or shavings from the CMP process may remain in the recess portion of the W plug. Moreover, there is a fear that the above-mentioned reactive biological oxides cannot be completely removed. In such a situation, the W plug does not solve the concern that the resistance of the contact portion with the upper layer wiring increases and the resistance variation due to pattern density.

  The present invention has been made in consideration of the above-described circumstances. With respect to the hole connection portion of the contact hole or via hole, a rise in resistance is suppressed regardless of the density of the pattern, and a more stable configuration with no resistance variation is provided. It is an object of the present invention to provide a semiconductor device having the same and a manufacturing method thereof.

  The semiconductor device according to the present invention includes an insulating layer, a hole reaching an arbitrary connection region below the insulating layer, a first wiring member embedded in the hole and extending on the insulating layer, and the upper portion of the hole And a second wiring member formed on the first wiring member and forming a wiring pattern on the insulating layer together with the first wiring member.

  According to the semiconductor device of the present invention, the first wiring member embedded in the hole extends on the insulating layer. Thereby, it is not necessary to pay attention to each of the embedded states of the first wiring members in the plurality of holes provided. That is, the first wiring member above the hole is held on the insulating layer at a predetermined thickness so that it cannot be recessed. The second wiring member constitutes a substantial wiring pattern, but the first wiring member is present under the second wiring member.

The semiconductor device according to the present invention has any of the following features, and contributes to prevention of high resistance of the semiconductor integrated circuit wiring and improvement of reliability.
The first wiring member is smaller in thickness than the second wiring member on the insulating layer and has a pattern integrated with the second wiring member in a self-aligning manner.
The first wiring member includes a buried metal made of tungsten, and a barrier film provided between the buried metal, the inner wall of the hole, and the insulating layer.
The second wiring member includes a main wiring metal mainly composed of aluminum, a barrier film provided between the main wiring metal and the first wiring member, and a protective metal film on the main wiring metal. It is characterized by having.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a hole penetrating an insulating layer and reaching an arbitrary connection region under the insulating layer in the method of manufacturing a semiconductor device constituting a semiconductor integrated circuit wiring, Forming a first wiring member on the insulating layer while filling a hole; planarizing an upper surface of the first wiring member; and uniformly leaving the first wiring member on the insulating layer; Forming a second wiring member on the first wiring member; forming a mask pattern on the second wiring member; and isolating the second wiring member and the first wiring member according to the mask pattern. And etching to form a wiring pattern.

  According to the semiconductor device manufacturing method of the present invention, the first wiring member on the insulating layer embedded in the hole is uniformly left on the insulating layer even after planarization. This eliminates the need to pay attention to the state of the first wiring member with respect to the upper portion of each hole in filling the plurality of holes with the first wiring member. In other words, the first wiring member is left on the insulating layer with a predetermined thickness so that the upper portion of the hole cannot be recessed regardless of the density of the hole pattern. Thereafter, the second wiring member forms a wiring pattern on the insulating layer together with the first wiring member.

Further, the semiconductor device manufacturing method according to the present invention contributes to the prevention of high resistance of the semiconductor integrated circuit wiring and the improvement of reliability by having any of the following characteristics.
The first wiring member is planarized by chemical mechanical polishing so that the first wiring member has a smaller thickness than the second wiring member on the insulating layer.
The first wiring member is characterized in that tungsten is formed on the insulating layer through a barrier film covering the connection region and the inner wall of the hole.
In the first wiring member, tungsten is formed on the insulating layer, and the connection region and the inner wall of the hole are covered with a barrier film, and the film thickness of the tungsten on the insulating layer is measured in advance. It is characterized by controlling the time of chemical mechanical polishing for planarizing the upper surface of tungsten.
The upper surface of the first wiring member is tungsten, and the tungsten is controlled to remain uniformly on the insulating layer by a plurality of stepwise chemical mechanical polishing processes.
In the second wiring member, a main wiring metal mainly composed of aluminum is formed through a barrier film coating on the first wiring member, and a protective metal film is coated on the main wiring metal. It is characterized by.

BEST MODE FOR CARRYING OUT THE INVENTION

1 and 2 are cross-sectional views showing the main part of the semiconductor device according to the first embodiment of the present invention, which are part of the semiconductor integrated circuit wiring. Each figure is explained in common.
The insulating layer 11 is, for example, an interlayer insulating film with the lower connection region 10. A hole 12 reaching an arbitrary connection region 10 under the insulating layer 11 is formed. It is conceivable that the connection region 10 is an impurity diffusion region or a lower wiring member.

  The wiring member 13 is embedded in the hole 12 and extends on the insulating layer 11. The wiring member 13 includes a plug metal such as W (tungsten). Here, the wiring member 13 includes a buried metal 132 made of W, and a barrier film 131 provided between the buried metal 132 and the inner wall of the hole 12 and the insulating layer 11. The barrier film 131 may be a TiN film, a Ti / TiN laminated film, a film containing a TaN film, or the like.

  A wiring member 14 is formed on the wiring member 13 including above the hole 12. The wiring member 14 constitutes a wiring pattern 16 on the insulating layer 11 together with the wiring member 13. The wiring member 14 constitutes a substantial wiring layer on the insulating layer 11, and its film thickness is larger than that of the wiring member 13 on the insulating layer 11. In the wiring member 14, a main wiring member 142 is formed on the covering of the barrier film 141, and the uppermost surface is covered with a protective metal film (cap film) 143. The barrier film 141 may be a TiN film, a Ti / TiN laminated film, or the like. The main wiring member 142 may contain Al and Cu or Si. The protective metal film (cap film) 143 may be a TiN film or a Ti / TiN laminated film, for example, and is provided as a film that enhances antireflection and stress microphone resistance.

  According to the configuration of the above embodiment, W as the wiring member 13 embedded in the hole 12 extends on the insulating layer 11. The wiring member 13 is thinner than the wiring member 14 on the insulating layer 11 and has a pattern integrated with the wiring member 14 in a self-aligning manner. Even if a plurality of holes 12 are provided, it is not necessary to pay attention to the embedded state of W in each hole 12. That is, W at the top of the hole 12 is held on the insulating layer 11 to a predetermined thickness so that the recess cannot be made. Therefore, regardless of the density of the hole pattern, the upper portion of the hole 12 has a structure that is extremely difficult to be recessed, and resistance increase and resistance variation due to foreign matters accumulated in the recessed portion are almost eliminated. The wiring member 14 constitutes a substantial part of the wiring pattern 16 with the main wiring member 142. The wiring member 13 is thinly formed under the wiring member 14 in a self-aligning pattern with the wiring pattern 16.

3 to 6 are cross-sectional views showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps. The sparse pattern and the dense pattern are illustrated. The same parts as those in the first embodiment will be described with the same reference numerals as those in FIG.
As shown in FIG. 3, a mask pattern (not shown) is formed on the insulating layer 11 which is an interlayer insulating film through a photolithography process, and etching is performed according to this mask pattern. Thereby, each hole 12 which penetrates the insulating layer 11 and reaches the lower connection region 10 is formed. It is conceivable that the connection region 10 is an impurity diffusion region or a lower wiring member. For example, when the connection region 10 is an impurity diffusion region, the hole 12 is called a contact hole, and when the connection region 10 is a lower wiring member, the hole 12 is called a via hole.

  Next, the wiring member 13 is formed on the insulating layer 11 while filling the hole 12. The wiring member 13 first coats the connection region 10 and the inner wall of the hole with the Ti / TiN laminated film as the barrier film 131 on the insulating layer 11 by using a sputtering method. In addition, as the barrier film 131, it is possible to use only a TiN film or a film containing a TaN film. Thereafter, W (tungsten) serving as the buried metal 132 is formed on the insulating layer 11 while being buried in the hole 12 by using a thermal CVD method.

  Next, as shown in FIG. 4, the upper surface (embedded metal 132) of the wiring member 13, that is, W is flattened using CMP (Chemical Mechanical Polishing) technique, and W remains uniformly on the insulating layer 11. Let This CMP process is intended to planarize W, and the CMP process is terminated when the planarization is performed. At this time, it should be noted that W is not recessed from the surface of the insulating layer 11 forming the hole 12.

  That is, it is important that no recess occurs on the W plug regardless of the density of the hole pattern. Based on these, W on the insulating layer 11 is left with a thickness that does not cause a recess on the W plug. The method of leaving W on the edge layer 11 controls the CMP processing time. For example, the CMP process may be divided into two or more steps to improve the accuracy. In addition, the CMP processing time may be calculated after measuring the film thickness of W on the insulating layer 11 before the CMP processing, including stepwise processing. When a recess can be formed on the current W plug, it is about 20 nm to 30 nm, so that the remaining film of W is considered to be appropriate to be 30 nm or more. Even if the polishing rate variation of the CMP process is considered in the wafer surface, it is considered that the remaining film of W on the insulating layer 11 is about 30 nm to about 40 nm.

  Next, as shown in FIG. 5, the wiring member 14 is formed on the W surface of the wiring member 13. In the wiring member 14, the main wiring member 142 is formed on the underlying barrier film 141 and the uppermost layer is covered with a protective metal film (cap film) 143. As the underlying barrier film 141, a total of several tens of nm of Ti / TiN laminated films are formed by sputtering. In addition, it is conceivable to use only a TiN film as the barrier film 131. After covering the barrier film 141, as the main wiring member 142, for example, an Al—Cu alloy containing less than 1% (for example, 0.5%) of Cu is formed by sputtering to a few hundred nm (300 nm or more). Further, as the uppermost protective metal film (cap film) 143, a Ti / TiN laminated film is formed by sputtering in a total of several tens of nm. In addition, it is conceivable that only the TiN film is used as the protective metal film 143.

  Next, as shown in FIG. 6, a mask pattern 15 as shown by a broken line is formed through a photolithography process. The mask pattern 15 may include not only a resist pattern but also a hard mask structure such as a silicon oxide film. Then, the wiring member 14 and the wiring member 13 are removed according to the mask pattern 15 by an anisotropic dry etching technique using a Cl-based (or CF-based) etching gas. Thereby, the wiring pattern 16 having the wiring member 13 integrated with the wiring member 14 in a self-aligning manner is formed.

  According to the method of the above embodiment, W of the wiring member 13 on the insulating layer 11 embedded in the hole 12 remains uniformly on the insulating layer 11 even after planarization. Thereby, it is not necessary to pay attention to the embedded state of W in the plurality of holes 12. That is, a predetermined thickness of W as the wiring member 13 is left on the insulating layer 11 so that the upper portion of the hole 12 cannot be recessed. Thereafter, the wiring member 14 is formed, and the wiring members 13 and 14 form a wiring pattern 16 integrated in a self-aligning manner. As a result, regardless of the density of the hole pattern, the recess is extremely difficult to be formed in the upper portion of the hole 12, and resistance increase and resistance variation due to the foreign matter accumulated in the recess portion are almost eliminated.

  In the method of the above embodiment, the dimension of the hole 12 is substantially the same as the dimension (width) of the wiring pattern 16. The present invention is not limited to this, and the same effect as described above can be obtained even if a configuration in which the size (width) of the wiring pattern 16 is larger than the size of the hole 12 is adopted.

  As described above, according to the present invention, the first wiring member embedded in the hole extends on the insulating layer. More preferably, the first wiring member above the hole is held on the insulating layer at a predetermined thickness so that the recess cannot be made. This eliminates the concern about the occurrence of recesses in the embedded state by the first wiring members in the plurality of holes regardless of the density of the hole pattern. Although the second wiring member constitutes a substantial wiring pattern, the first wiring member exists in a self-aligning pattern with the wiring pattern below the second wiring member. As a result, it is possible to provide a semiconductor device having a more stable configuration that suppresses an increase in resistance and has no resistance variation regardless of pattern density, and a method for manufacturing the same, with respect to contact hole and via hole connection portions.

  The present invention is not limited to the above-described embodiments and methods, and various modifications and applications can be implemented without departing from the spirit of the present invention.

1 is a first cross-sectional view showing a main part of a semiconductor device according to a first embodiment. FIG. 3 is a second cross-sectional view showing the main part of the semiconductor device according to the first embodiment. The 1st sectional view showing the manufacturing method of the semiconductor device concerning a 2nd embodiment in order of a process. The 2nd sectional view following Drawing 3. FIG. 5 is a third sectional view following FIG. 4. FIG. 6 is a fourth cross-sectional view following FIG. 5.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Connection area | region, 11 ... Insulating layer, 12 ... Hole, 13, 14 ... Wiring member, 131, 141 ... Barrier film, 132 ... Embedded metal, 142 ... Main wiring member, 143 ... Protective metal film (cap film), 15 ... mask pattern, 16 ... wiring pattern.

Claims (10)

An insulating layer;
Holes reaching any connection region under the insulating layer;
A first wiring member embedded in the hole and extending on the insulating layer;
A second wiring member formed on the first wiring member including above the hole and constituting a wiring pattern on the insulating layer together with the first wiring member;
A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein the first wiring member has a pattern smaller in thickness than the second wiring member on the insulating layer and integrated with the second wiring member in a self-aligning manner. The semiconductor device according to claim 1, wherein the first wiring member includes a buried metal made of tungsten, and a barrier film provided between the buried metal, the inner wall of the hole, and the insulating layer. The second wiring member includes a main wiring metal mainly composed of aluminum, a barrier film provided between the main wiring metal and the first wiring member, and a protective metal film on the main wiring metal. The semiconductor device as described in any one of Claims 1-3. In a manufacturing method of a semiconductor device constituting a semiconductor integrated circuit wiring,
Forming a hole that penetrates the insulating layer and reaches an arbitrary connection region under the insulating layer;
Forming a first wiring member on the insulating layer while filling the hole;
Flattening an upper surface of the first wiring member, and uniformly leaving the first wiring member on the insulating layer;
Forming a second wiring member on the first wiring member;
Forming a mask pattern on the second wiring member;
Forming the wiring pattern by anisotropically etching the second wiring member and the first wiring member according to the mask pattern;
A method of manufacturing a semiconductor device including: The method of manufacturing a semiconductor device according to claim 5, wherein the first wiring member is planarized by chemical mechanical polishing so that the thickness of the first wiring member is smaller than that of the second wiring member on the insulating layer. 7. The method of manufacturing a semiconductor device according to claim 5, wherein the first wiring member is formed with tungsten on the insulating layer through a barrier film covering the connection region and the inner wall of the hole. In the first wiring member, tungsten is formed on the insulating layer through a barrier film covering the connection region and the inner wall of the hole, and the tungsten upper surface is flattened by measuring the thickness of the tungsten on the insulating layer. The method for manufacturing a semiconductor device according to claim 5, wherein a chemical mechanical polishing processing time for the conversion is controlled. 7. The upper surface of the first wiring member is tungsten, and the tungsten is controlled to remain uniformly on the insulating layer by a plurality of stepwise chemical mechanical polishing processes. Semiconductor device manufacturing method. In the second wiring member, a main wiring metal mainly composed of aluminum is formed through a barrier film coating on the first wiring member, and a protective metal film is coated on the main wiring metal. Item 10. A method for manufacturing a semiconductor device according to any one of Items 5 to 9.

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