JP2006319130A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2006319130A
JP2006319130A JP2005140164A JP2005140164A JP2006319130A JP 2006319130 A JP2006319130 A JP 2006319130A JP 2005140164 A JP2005140164 A JP 2005140164A JP 2005140164 A JP2005140164 A JP 2005140164A JP 2006319130 A JP2006319130 A JP 2006319130A
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package body
peripheral wall
semiconductor device
chip
cover glass
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Japanese (ja)
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Masaaki Aoki
正昭 青木
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Fujifilm Holdings Corp
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Fuji Photo Film Co Ltd
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Priority to JP2005140164A priority Critical patent/JP2006319130A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

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  • Solid State Image Pick-Up Elements (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving adhesiveness of an adhesion interface between a translucent member and a package body in an airtight sealing system and of improving the quality by sufficiently securing adhesion strength without accompanying an increased number of processes and an increased cost. <P>SOLUTION: The semiconductor device 100 comprises an imaging element chip 13; a package body 12 composed of a chip housing 15 for mounting the imaging element chip 13, and of a peripheral wall 17 formed around the chip housing 15; and the translucent member 14 joined with the peripheral wall 17 so as to seal the chip housing 15 of the package body 12. In the semiconductor device, a roughened region 21 is formed on both junction surfaces 20A, 20B of the translucent member 14 and the peripheral wall 17. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、パッケージ本体に装着された撮像素子チップを透光性部材により封止した半導体装置に関する。   The present invention relates to a semiconductor device in which an imaging element chip mounted on a package body is sealed with a light-transmitting member.

代表的な半導体装置の封止方式として気密封止方式と呼ばれるものがある。この気密封止方式は、その封止構造から、金属封止、セラミック封止、ガラス封止等に区分される。こうした気密封止方式の半導体装置では、半導体装置のベースとなるパッケージ本体に、撮像素子チップ収納用の凹部を一体形成し、この凹部に撮像素子チップを装着して、更にパッケージ本体にリッド(蓋体)を接合することにより、撮像素子チップを気密状態に封止するものが広く知られている。   As a typical semiconductor device sealing method, there is a method called an airtight sealing method. This hermetic sealing method is classified into metal sealing, ceramic sealing, glass sealing and the like from the sealing structure. In such a hermetically sealed semiconductor device, a recess for housing an image sensor chip is integrally formed in a package body serving as a base of the semiconductor device, an image sensor chip is mounted in the recess, and a lid (lid) is further attached to the package body. What seals an image pick-up element chip | tip in an airtight state by joining a body is known widely.

従来の半導体装置として、接着剤によってパッケージ本体の周囲にリッドを接合したものがある（例えば、特許文献１参照）。また、パッケージ本体と蓋体との接合面を凹凸状に形成したものもある（例えば、特許文献２参照）。特許文献２に開示された半導体装置では、パッケージ本体側に複数の凹部や階段状部や波状部を環状に形成するとともに、蓋体側に同じく環状に複数の凸部や階段状部や波状部を形成し、これら凹部と凸部、両階段状部、両波状部を嵌め合わせるようにしている。
特開平７−７８９５１号公報 特開平１０−２４７６９５号公報 As a conventional semiconductor device, there is one in which a lid is joined around a package body with an adhesive (see, for example, Patent Document 1). In addition, there is a case where the joint surface between the package body and the lid is formed in an uneven shape (see, for example, Patent Document 2). In the semiconductor device disclosed in Patent Document 2, a plurality of concave portions, stepped portions, and corrugated portions are formed in an annular shape on the package body side, and a plurality of convex portions, stepped portions, and corrugated portions are also annularly formed on the lid body side. These concave and convex portions, both stepped portions, and both wavy portions are fitted together.
JP-A-7-78951 Japanese Patent Laid-Open No. 10-247695

気密封止方式の半導体装置においては、特に、ＣＣＤ型センサやＭＯＳ型センサに代表される固体撮像装置では、一般的に、ガラス製のリッドを熱硬化やＵＶ硬化樹脂等によりパッケージ本体に接合して封止している。この場合、ガラスリッドとパッケージ本体との密着性は、ガラスリッドおよびパッケージ本体の接着界面状態に大きく影響される。例えば、接着剤と接するガラスリッド及びパッケージ本体との界面の親水性が悪いと、接着時の樹脂硬化応力により、また、接着後もそれぞれの部材の熱膨張率の相違に起因する応力により、接着強度を十分に確保できない場合が生じる。そして、近年のパッケージ小型化に伴い、パッケージ本体とリッドとの接合面積を十分に確保できなくなることにより、更に接着強度の低下を招いている。その結果、半導体装置の気密性、特に素子品質に大きく影響を及ぼす耐湿性が低下して、固体撮像装置にあっては結露等による機能障害を生じる虞が予想される。   In a hermetically sealed semiconductor device, particularly in a solid-state imaging device represented by a CCD sensor or a MOS sensor, generally, a glass lid is bonded to a package body by thermosetting or UV curable resin. And sealed. In this case, the adhesion between the glass lid and the package body is greatly influenced by the state of the bonding interface between the glass lid and the package body. For example, if the hydrophilicity of the interface between the glass lid and the package body in contact with the adhesive is poor, the adhesive is caused by the resin curing stress at the time of adhesion, and also after the adhesion due to the stress due to the difference in the thermal expansion coefficient of each member. In some cases, sufficient strength cannot be secured. As the package size is reduced in recent years, the bonding area between the package body and the lid cannot be sufficiently secured, thereby further reducing the adhesive strength. As a result, the airtightness of the semiconductor device, in particular, the moisture resistance that greatly affects the element quality, is lowered, and in the solid-state imaging device, there is a possibility of causing a functional failure due to condensation or the like.

このように、上記特許文献１では、パッケージ本体側の接合面と、リッド側の接合面とがいずれも狭領域の平滑面であるため、双方の接着後に各接合面の面積が不十分となることや、各接合面がパッケージ本体及びリッドの熱膨張率の相違に起因する応力により、接着強度が十分に確保できなくなる虞がある。また、パッケージ本体とガラスリッドとの接合の位置合わせの確認が、ガラスリッドが透明体であるために外観からは困難となる。   As described above, in Patent Document 1, since the joint surface on the package body side and the joint surface on the lid side are both smooth surfaces in a narrow region, the area of each joint surface becomes insufficient after both are bonded. In addition, there is a possibility that the bonding strength cannot be sufficiently secured due to the stress caused by the difference in thermal expansion coefficient between the package body and the lid. In addition, it is difficult to confirm the alignment of the bonding between the package body and the glass lid from the appearance because the glass lid is a transparent body.

また、上記特許文献２では、エポキシ樹脂製のパッケージ本体に複数の凹部や階段状部や波状部を形成するに際し、形状の複雑化に伴ってパッケージ本体に成形時のひけ等の支障を生ずる虞がある。また、ガラス製の蓋体に複数の凸部や階段状部や波状部を形成するに際し、角部に欠け等の破損を生ずることがある。さらに、ガラス製品に対する加工が難しいので、加工工数を多く必要としてコスト面で不利となり、実現性に乏しい。また、パッケージ本体がセラミック材である場合は、その形状加工が煩雑となりコストアップの要因となる。   Further, in Patent Document 2, when forming a plurality of concave portions, stepped portions, and corrugated portions in a package body made of epoxy resin, there is a risk of causing problems such as sink marks at the time of molding in the package body as the shape becomes complicated. There is. Further, when a plurality of convex portions, stepped portions, or corrugated portions are formed on the glass lid, breakage such as chipping may occur in the corner portions. Furthermore, since it is difficult to process glass products, it requires a large number of processing steps, which is disadvantageous in terms of cost and lacks feasibility. Further, when the package body is made of a ceramic material, the shape processing becomes complicated and causes an increase in cost.

本発明は、上述した事情に鑑みてなされたものであり、その目的は、工数の増大やコストアップを伴うことなく接着強度を十分に確保し、気密封止方式における透光性部材とパッケージ本体との接着界面の密着性を向上させ、品質向上を図ることができる半導体装置を提供することにある。   The present invention has been made in view of the above-described circumstances, and the object thereof is to ensure sufficient adhesive strength without increasing man-hours and cost, and to provide a light-transmitting member and a package body in an airtight sealing system. It is an object of the present invention to provide a semiconductor device capable of improving the quality of the adhesive interface and improving the quality.

本発明に係る上記目的は、下記構成により達成できる。
（１）撮像素子チップと、撮像素子チップを装着するためのチップ収容部を有するとともに、該チップ収容部を囲んで形成された周壁を有するパッケージ本体と、前記パッケージ本体の前記チップ収容部を封止するように前記周壁と接合される透光性部材と、を備えた半導体装置であって、前記透光性部材と前記周壁の双方の接合面に粗面化領域を形成したことを特徴とする半導体装置。 The above object of the present invention can be achieved by the following configuration.
(1) An image pickup device chip, a package main body having a chip housing portion for mounting the image pickup device chip and having a peripheral wall formed surrounding the chip housing portion, and the chip housing portion of the package main body are sealed. A translucent member joined to the peripheral wall so as to stop, characterized in that a roughened region is formed on the joint surface of both the translucent member and the peripheral wall. Semiconductor device.

このように構成された半導体装置においては、透光性部材におけるパッケージ本体への接合面に粗面化領域が形成されているために、親水性が高くなって接着界面の密着性が向上する。それにより、接着時の樹脂硬化応力や、接着後の透光性部材とパッケージ本体との熱膨張率の相違による応力が加えられたとしても、接着強度が低下することなく高い強度を発揮して確実な接合を行うことができる。   In the semiconductor device configured as described above, since the roughened region is formed on the bonding surface of the translucent member to the package body, the hydrophilicity is increased and the adhesion at the adhesion interface is improved. As a result, even if resin curing stress at the time of adhesion or stress due to the difference in thermal expansion coefficient between the translucent member and the package body after adhesion is applied, high strength is exhibited without lowering the adhesive strength. Reliable joining can be performed.

（２）前記粗面化領域が、サンドブラスト処理により成形されていることを特徴とする（１）記載の半導体装置。 (2) The semiconductor device according to (1), wherein the roughened region is formed by sandblasting.

このように構成された半導体装置においては、サンドブラスト処理により、透光性部材のパッケージ本体側の接合面の表面積が大きくなるために、接着剤の食い付きが良好になって接着強度を向上させることができる。   In the semiconductor device configured as described above, the sandblasting process increases the surface area of the joint surface on the package body side of the translucent member, so that the adhesive bite is improved and the adhesive strength is improved. Can do.

（３）前記粗面化領域が、前記透光性部材の周縁部に、前記周壁の接合面の幅と同一幅で形成されていることを特徴とする（１）又は（２）記載の半導体装置。 (3) The semiconductor according to (1) or (2), wherein the roughened region is formed in the peripheral portion of the translucent member with the same width as the width of the joint surface of the peripheral wall. apparatus.

このように構成された半導体装置においては、透光性部材とパッケージ本体との組付け工程に対し、透光性部材の粗面化領域をパッケージ本体の周壁の接合面に合わせることで位置合わせの確認が行われる。これにより、万一、透光性部材がパッケージ本体の周壁に対して位置ずれしている場合、粗面化領域に周壁が一致していないことで位置ずれを生じていることが外観から簡単に判別できるので、製造工程の早期から不良品の選別が可能となる。   In the semiconductor device configured as described above, the alignment process is performed by aligning the roughened region of the translucent member with the joint surface of the peripheral wall of the package body in the assembling process of the translucent member and the package main body. Confirmation is performed. As a result, in the unlikely event that the translucent member is displaced with respect to the peripheral wall of the package body, it is easy to see from the appearance that the peripheral wall does not match the roughened region. Since it can be discriminated, defective products can be selected from the early stage of the manufacturing process.

本発明の半導体装置によれば、接着強度を十分に確保し、また工数の増大やコストアップを伴うことなく、気密封止方式における透光性部材とパッケージ本体との接着界面の密着性を向上させ、半導体装置の品質向上を図ることができる。   According to the semiconductor device of the present invention, sufficient adhesive strength is ensured, and the adhesion at the adhesive interface between the translucent member and the package body in the hermetic sealing method is improved without increasing man-hours and costs. Thus, the quality of the semiconductor device can be improved.

以下、本発明に係る半導体装置の好適な実施の形態について、図面を参照して説明する。
図1に半導体装置の分解斜視図、図２に図１に示す半導体装置のＡ−Ａ縦断面図を示した。ここでは半導体装置の一例として固体撮像素子パッケージを説明することにする。 DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of a semiconductor device according to the invention will be described with reference to the drawings.
FIG. 1 shows an exploded perspective view of the semiconductor device, and FIG. 2 shows an AA longitudinal sectional view of the semiconductor device shown in FIG. Here, a solid-state imaging device package will be described as an example of a semiconductor device.

まず、この固体撮像パッケージ１００の構成から説明する。
図１、図２に示すように、固体撮像パッケージ１００は、パッケージ本体１２と半導体チップ１３とからなる組立体１１と、カバーガラス１４とを有して構成されている。パッケージ本体１２はセラミック材料からなり、中央部にチップ収容部１５を有するとともに、このチップ収容部１５の周りに段部１６を有し、段部１６の周りに直立した周壁１７を有する。 First, the configuration of the solid-state imaging package 100 will be described.
As shown in FIGS. 1 and 2, the solid-state imaging package 100 includes an assembly 11 including a package body 12 and a semiconductor chip 13 and a cover glass 14. The package body 12 is made of a ceramic material, and has a chip accommodating portion 15 at the center, a step portion 16 around the chip accommodating portion 15, and a peripheral wall 17 that stands upright around the step portion 16.

チップ収容部１５は、段部１６の略中央部に凹状に形成されており、半導体チップ１３がダイボンド剤を介して装着されている。
段部１６は、半導体チップ１３の側部に配置された不図示の複数の各ポートとの間にそれぞれ電気的に接続された複数の導電部材（ボンディングワイヤ）１８に電気的に接続される不図示のリードフレームを一体に埋め込んでなる。各ボンディングワイヤ１８は、一端部が半導体チップの各ポートに電気的に接続され、他端部がリードフレームの一端部に電気的に接続される。リードフレームは、他端部がパッケージ本体１２の下面や側面から外側に表出して不図示の制御回路に電気的に接続される。 The chip accommodating portion 15 is formed in a concave shape at a substantially central portion of the step portion 16, and the semiconductor chip 13 is mounted via a die bond agent.
The step portion 16 is electrically connected to a plurality of conductive members (bonding wires) 18 electrically connected to a plurality of ports (not shown) arranged on the side of the semiconductor chip 13. The illustrated lead frame is embedded integrally. Each bonding wire 18 has one end portion electrically connected to each port of the semiconductor chip and the other end portion electrically connected to one end portion of the lead frame. The other end of the lead frame is exposed to the outside from the lower surface or side surface of the package body 12 and is electrically connected to a control circuit (not shown).

周壁１７は、予め定められた厚さを有し、その上面に平坦な接合面２０Ａを有する。接合面２０Ａの幅は、全周に渡ってＷ１とされている。カバーガラス１４は、その接合面２０Ｂと、パッケージ本体１２の接合面２０Ａとの間にシーリング剤（接着剤）２３を介在させて周壁１７上に接合される。ここで、周壁１７の接合面２０Ａは、全周に渡って粗面化処理を施した粗面化領域２１とされている。粗面化領域２１には、接合面２０Ａと略同一の幅内においてサンドブラスト処理等による粗面加工が全周に渡って施されている。   The peripheral wall 17 has a predetermined thickness, and has a flat joint surface 20A on the upper surface thereof. The width of the joining surface 20A is W1 over the entire circumference. The cover glass 14 is bonded onto the peripheral wall 17 with a sealing agent (adhesive) 23 interposed between the bonding surface 20B thereof and the bonding surface 20A of the package body 12. Here, 20 A of joining surfaces of the surrounding wall 17 are made into the roughening area | region 21 which performed the roughening process over the perimeter. The roughened region 21 is subjected to roughening by sandblasting or the like over the entire circumference within substantially the same width as the joining surface 20A.

図３にカバーガラスの接合面側の平面図を示した。
カバーガラス１４は、比較的薄い透明のガラス板であり、中央部分が光透過用であって、裏面の周囲に、パッケージ本体１２の周壁１７の接合面２０Ａと同一の幅Ｗ２を有する接合面２０Ｂを有し、この接合面２０Ｂの全周が粗面化領域２２として形成されている。パッケージ本体１２の粗面化領域２１は、カバーガラス１４の粗面化領域２２と重ね合わせた際に一致するように形成される。カバーガラス１４の粗面化領域２２は、パッケージ本体１２側と同様に、サンドブラスト処理等による粗面加工が周壁１７の全周に渡って施されている。 FIG. 3 shows a plan view of the cover glass on the bonding surface side.
The cover glass 14 is a relatively thin transparent glass plate, the central portion is for light transmission, and has a joint surface 20B having the same width W2 as the joint surface 20A of the peripheral wall 17 of the package body 12 around the back surface. The entire circumference of the joint surface 20B is formed as the roughened region 22. The roughened region 21 of the package body 12 is formed so as to coincide with the roughened region 22 of the cover glass 14 when overlapped. The roughened region 22 of the cover glass 14 is subjected to roughening by sandblasting or the like over the entire circumference of the peripheral wall 17 in the same manner as the package body 12 side.

サンドブラスト処理は、周壁１７やカバーガラス１４の周囲に所定の幅を介してマスキングを行ったうえで、専用のシェルター内において、周壁１７やカバーガラス１４の表面に砂等のサンドブラスト材を圧縮空気により吹き付けることにより、接合面２０Ａ，２０Ｂを断面のこぎり波状の微小凹凸に粗面化する処理である。なお、カバーガラス１４の場合、粗面化領域２１はサンドブラスト処理に代えてエッチング加工等を用いて形成することもできる。   In the sand blasting process, the periphery of the peripheral wall 17 and the cover glass 14 is masked through a predetermined width, and then sand blasting material such as sand is applied to the surface of the peripheral wall 17 and the cover glass 14 with compressed air in a dedicated shelter. By spraying, the bonding surfaces 20A and 20B are roughened into sawtooth wave-like minute irregularities in the cross section. In the case of the cover glass 14, the roughened region 21 can be formed by using an etching process or the like instead of the sandblasting process.

このように、本実施形態の固体撮像パッケージ１００によれば、パッケージ本体１２の周壁１７の接合面２０Ａ、及びカバーガラス１４におけるパッケージ本体１２への接合面２０Ｂの双方に、粗面化領域２１、２２が形成されているために、各接合面２０Ａ，２０Ｂの親水性が高くなって接着界面の密着性が向上する。その結果、接着時における樹脂硬化応力や、接着後のカバーガラス１４とパッケージ本体１２との熱膨張率の相違による応力が加えられたとしても、高い接着強度を維持して確実な接合を行うことができる。さらに、気密性において重要な耐湿性能を向上させることで、結露等による機能障害を生ずることを確実に防止できる。   As described above, according to the solid-state imaging package 100 of the present embodiment, the roughened region 21 is provided on both the bonding surface 20A of the peripheral wall 17 of the package body 12 and the bonding surface 20B of the cover glass 14 to the package body 12. Since 22 is formed, the hydrophilicity of each joining surface 20A, 20B becomes high, and the adhesiveness of an adhesion interface improves. As a result, even if a resin curing stress at the time of bonding or stress due to a difference in thermal expansion coefficient between the cover glass 14 and the package body 12 after bonding is applied, high bonding strength is maintained and reliable bonding is performed. Can do. Furthermore, by improving the moisture resistance, which is important for airtightness, it is possible to reliably prevent functional failures due to condensation or the like.

次に、固体撮像パッケージ１００の組立て時の作用について説明する。
図４（ａ）は固体撮像パッケージ１００の組立て状態における不具合を説明する縦断面図、図４（ｂ）は（ａ）に示すＢ−Ｂ線の縦断面図である。
固体撮像パッケージ１００は、パッケージ本体１２の周壁１７における接合面２０Ａと、カバーガラス１４の接合面２０Ｂとの間にシーリング材２３を介在させて、カバーガラス１４が周壁１７上に接合されることで組立てが行われる。 Next, an operation when the solid-state imaging package 100 is assembled will be described.
4A is a longitudinal sectional view for explaining a problem in the assembled state of the solid-state imaging package 100, and FIG. 4B is a longitudinal sectional view taken along line BB shown in FIG.
In the solid-state imaging package 100, the cover glass 14 is bonded onto the peripheral wall 17 with a sealing material 23 interposed between the bonding surface 20 </ b> A on the peripheral wall 17 of the package body 12 and the bonding surface 20 </ b> B of the cover glass 14. Assembly is performed.

このとき、カバーガラス１４とパッケージ本体１２とが相対的に位置ずれを起こす場合がある。例えば図示のように一方向への位置ずれが生じ、パッケージ本体１２の周壁１７の接合面２０Ａに対してカバーガラス１４の接合面２０Ｂが長さΔＷだけずれて接合されると、カバーガラス１４の粗面化領域２２の外側に、パッケージ本体１２の粗面化領域２１に一致しない周壁１７からはみ出した非接合面部２４がカバーガラス１４を通して観察される。この非接合面部２４は、カバーガラス１４の接合面２０Ｂにおける粗面化領域２２の幅寸法Ｗ２が、周壁１７の接合面２０Ａの幅寸法Ｗ１と同一寸法になっており、カバーガラス１４の粗面化領域２２が半透明の摺りガラス状となり不透明な白色になっていることにより明瞭に観察できる。   At this time, the cover glass 14 and the package body 12 may be relatively displaced. For example, as shown in the figure, when the position shift in one direction occurs, and the bonding surface 20B of the cover glass 14 is bonded to the bonding surface 20A of the peripheral wall 17 of the package body 12 by being shifted by the length ΔW, the cover glass 14 A non-joint surface portion 24 protruding from the peripheral wall 17 that does not coincide with the roughened region 21 of the package body 12 is observed through the cover glass 14 outside the roughened region 22. In the non-joint surface portion 24, the width dimension W <b> 2 of the roughened region 22 in the joint surface 20 </ b> B of the cover glass 14 is the same as the width dimension W <b> 1 of the joint surface 20 </ b> A of the peripheral wall 17. It is possible to observe clearly because the conversion region 22 has a translucent ground glass shape and is opaque white.

即ち、カバーガラス１４の粗面化領域２２のうち、パッケージ本体１２の周壁１７の接合面２０Ａと接合された部分では、シーリング材２３によりカバーガラス１４の粗面化領域２２の微小凹凸が埋まり、光の拡散効果が薄れる。これにより、カバーガラス１４を通して周壁１７が透けて見える状態となる。その場合の周壁１７は、周壁１７側の粗面化領域２１の微小凹凸がシーリング材２３により埋まり、パッケージ本体１２の素地色、若しくはシーリング材２３が有色の場合はシーリング材２３の色として観察される。   That is, in the roughened region 22 of the cover glass 14, in the portion bonded to the bonding surface 20 </ b> A of the peripheral wall 17 of the package body 12, the minute unevenness of the roughened region 22 of the cover glass 14 is filled with the sealing material 23. Light diffusion effect fades. As a result, the peripheral wall 17 can be seen through the cover glass 14. The peripheral wall 17 in that case is observed as the base color of the package body 12 or the color of the sealing material 23 when the sealing material 23 is colored, with the minute unevenness of the roughened region 21 on the peripheral wall 17 side being filled with the sealing material 23. The

一方、カバーガラス１４の粗面化領域２２のうち、周壁１７の内側で表出した周壁１７の接合面２０Ａの一部２５は、接合面２０Ａの粗面化状態における光拡散面のままとなり、隣接するカバーガラス１４と接合された領域との差が明瞭に視認できる。これにより、非接合面部２４，２５が外観上観察可能となることで、カバーガラス１４とパッケージ本体１２との位置ずれを簡単に見つけることができる。   On the other hand, in the roughened region 22 of the cover glass 14, a part 25 of the joint surface 20A of the peripheral wall 17 exposed inside the peripheral wall 17 remains the light diffusion surface in the roughened state of the joint surface 20A. The difference between the area joined to the adjacent cover glass 14 can be clearly seen. Thereby, since the non-joint surface parts 24 and 25 can be observed in appearance, a positional deviation between the cover glass 14 and the package body 12 can be easily found.

このように、本実施形態の固体撮像パッケージ１００によれば、カバーガラス１４とパッケージ本体１２との組付けに際し、カバーガラス１４の粗面化領域２２をパッケージ本体１２の周壁１７に合わせることで位置合わせが行われる。これにより、万が一に、カバーガラス１４がパッケージ本体１２の周壁１７に対して位置ずれしている場合、粗面化領域２２に周壁１７が一致していないことで位置ずれを生じていることを、周壁１７からはみ出した非接合面部２４，２５によって簡単に判別できる。これにより、製造工程の早期の段階で不良品を簡単に見つけることができる。そして、粗面化領域２１、２２は、接合面２０Ａ，２０Ｂの接合時の位置合せ手段としても用いることができるので、簡単にして、位置ずれのない高品質な固体撮像パッケージ１００を製造することができる。   As described above, according to the solid-state imaging package 100 of the present embodiment, when the cover glass 14 and the package body 12 are assembled, the roughened region 22 of the cover glass 14 is aligned with the peripheral wall 17 of the package body 12. Matching is done. Thereby, when the cover glass 14 is misaligned with respect to the peripheral wall 17 of the package main body 12, the misalignment is caused by the peripheral wall 17 not matching the roughened region 22. This can be easily determined by the non-joint surface portions 24 and 25 protruding from the peripheral wall 17. Thereby, a defective product can be easily found at an early stage of the manufacturing process. Since the roughened regions 21 and 22 can be used as alignment means when the bonding surfaces 20A and 20B are bonded, the high-quality solid-state imaging package 100 with no positional deviation can be easily manufactured. Can do.

以上説明した本発明に係る固体撮像パッケージ１００によれば、サンドブラスト処理等の粗面化処理により、カバーガラス１４及びパッケージ本体１２の接合面２０の表面積が増大するために、接着剤の食い付きが良好になって接着強度を向上させることができ、密閉性が良好となり、耐湿性が高められる。また、カバーガラス１４とパッケージ本体１２とを組み付ける際の位置合わせ精度を簡単に向上できる。   According to the solid-state imaging package 100 according to the present invention described above, the surface area of the bonding surface 20 of the cover glass 14 and the package body 12 is increased by the roughening process such as the sandblasting process. As a result, the adhesive strength can be improved, the airtightness is improved, and the moisture resistance is improved. Further, the alignment accuracy when the cover glass 14 and the package body 12 are assembled can be easily improved.

本発明に係る半導体装置の分解斜視図である。1 is an exploded perspective view of a semiconductor device according to the present invention. 図１に示す半導体装置のＡ−Ａ縦断面図である。FIG. 2 is an AA longitudinal sectional view of the semiconductor device shown in FIG. 1. カバーガラスの接合面側の平面図である。It is a top view of the joint surface side of a cover glass. （ａ）は図１に示した固体撮像パッケージの組立状態における作用を説明する縦断面図、（ｂ）は（ａ）のＢ−Ｂ線の縦断面図である。(A) is a longitudinal cross-sectional view explaining the effect | action in the assembly state of the solid-state imaging package shown in FIG. 1, (b) is a longitudinal cross-sectional view of the BB line of (a).

符号の説明Explanation of symbols

１２ パッケージ本体
１３ 半導体チップ（撮像素子チップ）
１４ カバーガラス（透光性部材）
１５ チップ収容部
１７ 周壁
２０Ａ 接合面（パッケージ本体側）
２０Ｂ 接合面（カバーガラス側）
２１ 粗面化領域
１００ 固体撮像パッケージ（半導体装置） 12 Package body 13 Semiconductor chip (imaging device chip)
14 Cover glass (translucent member)
15 Chip receiving part 17 Peripheral wall 20A Bonding surface (package body side)
20B Bonding surface (cover glass side)
21 Roughened region 100 Solid-state imaging package (semiconductor device)

Claims (3)

撮像素子チップと、
撮像素子チップを装着するためのチップ収容部を有するとともに、該チップ収容部を囲んで形成された周壁を有するパッケージ本体と、
前記パッケージ本体の前記チップ収容部を封止するように前記周壁と接合される透光性部材と、を備えた半導体装置であって、
前記透光性部材と前記周壁の双方の接合面に粗面化領域を形成したことを特徴とする半導体装置。 An image sensor chip;
A package body having a chip housing portion for mounting the image pickup device chip and having a peripheral wall formed surrounding the chip housing portion;
A translucent member joined to the peripheral wall so as to seal the chip housing portion of the package body,
A semiconductor device, wherein a roughened region is formed on a joint surface between both the translucent member and the peripheral wall. 前記粗面化領域が、サンドブラスト処理により成形されていることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the roughened region is formed by sandblasting. 前記粗面化領域が、前記透光性部材の周縁部に、前記周壁の接合面の幅と同一幅で形成されていることを特徴とする請求項１又は請求項２記載の半導体装置。   3. The semiconductor device according to claim 1, wherein the roughened region is formed in a peripheral portion of the translucent member with the same width as a width of a joint surface of the peripheral wall.
JP2005140164A 2005-05-12 2005-05-12 Semiconductor device Pending JP2006319130A (en)

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JP2013218245A (en) * 2012-04-12 2013-10-24 Seiko Epson Corp Optical element, imaging device, camera, and manufacturing method of optical element
JP2015035491A (en) * 2013-08-08 2015-02-19 セイコーインスツル株式会社 Optical semiconductor device and process of manufacturing the same
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Cited By (5)

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JP2009098473A (en) * 2007-10-18 2009-05-07 Seiko Epson Corp Fixing roller, fixing device using same, and image forming device
JP2013218245A (en) * 2012-04-12 2013-10-24 Seiko Epson Corp Optical element, imaging device, camera, and manufacturing method of optical element
JP2015035491A (en) * 2013-08-08 2015-02-19 セイコーインスツル株式会社 Optical semiconductor device and process of manufacturing the same
WO2016111038A1 (en) * 2015-01-08 2016-07-14 株式会社村田製作所 Piezoelectric oscillation member and production method for same
JPWO2016111038A1 (en) * 2015-01-08 2017-09-07 株式会社村田製作所 Piezoelectric vibration component and manufacturing method thereof

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