JP2006309734A5 - - Google Patents

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Publication number
JP2006309734A5
JP2006309734A5 JP2006085007A JP2006085007A JP2006309734A5 JP 2006309734 A5 JP2006309734 A5 JP 2006309734A5 JP 2006085007 A JP2006085007 A JP 2006085007A JP 2006085007 A JP2006085007 A JP 2006085007A JP 2006309734 A5 JP2006309734 A5 JP 2006309734A5
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JP
Japan
Prior art keywords
oite
memory
tag
sets
period
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JP2006085007A
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English (en)
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JP4364878B2 (ja
JP2006309734A (ja
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Priority to JP2006085007A priority Critical patent/JP4364878B2/ja
Priority claimed from JP2006085007A external-priority patent/JP4364878B2/ja
Publication of JP2006309734A publication Critical patent/JP2006309734A/ja
Publication of JP2006309734A5 publication Critical patent/JP2006309734A5/ja
Application granted granted Critical
Publication of JP4364878B2 publication Critical patent/JP4364878B2/ja
Expired - Fee Related legal-status Critical Current
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Claims (2)

  1. キャッシュメモリを有する演算処理装置であって、
    データメモリおよびタグメモリをそれぞれ有する複数のセットと、
    タグヒット率を第1の期間について計数する手段と
    前記第1の期間おいて、動作状態にある前記複数のセットのうち前記タグヒットが最もいセットを停止状態に遷移させる手段と、
    を有することを特徴とする演算処理装置。
  2. 請求項1において、
    前記停止状態において、前記データメモリおよび前記タグメモリへの、書き込み信号および読み出し信号が非有効化されることを特徴とする演算処理装置。
JP2006085007A 2005-03-31 2006-03-27 演算処理装置 Expired - Fee Related JP4364878B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006085007A JP4364878B2 (ja) 2005-03-31 2006-03-27 演算処理装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005102105 2005-03-31
JP2006085007A JP4364878B2 (ja) 2005-03-31 2006-03-27 演算処理装置

Publications (3)

Publication Number Publication Date
JP2006309734A JP2006309734A (ja) 2006-11-09
JP2006309734A5 true JP2006309734A5 (ja) 2009-02-12
JP4364878B2 JP4364878B2 (ja) 2009-11-18

Family

ID=37476495

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006085007A Expired - Fee Related JP4364878B2 (ja) 2005-03-31 2006-03-27 演算処理装置

Country Status (1)

Country Link
JP (1) JP4364878B2 (ja)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4519151B2 (ja) * 2007-03-20 2010-08-04 富士通株式会社 キャッシュ制御回路
JP5167952B2 (ja) * 2008-05-26 2013-03-21 富士通株式会社 キャッシュメモリシステム
JP5338905B2 (ja) * 2009-05-29 2013-11-13 富士通株式会社 キャッシュ制御装置およびキャッシュ制御方法
CN102792289B (zh) 2010-03-08 2015-11-25 惠普发展公司,有限责任合伙企业 数据存储装置
JP5484281B2 (ja) * 2010-09-21 2014-05-07 三菱電機株式会社 情報処理システム
US9703704B2 (en) 2012-05-01 2017-07-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

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