JP2006303469A - SiC SEMICONDUCTOR DEVICE - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an SiC semiconductor device in which leakage current is reduced and current properties are improved. <P>SOLUTION: A first conductor layer 101 is an n-type semiconductor layer that has 4H-SiC as a main composition, and includes n-type impurities. A second conductor layer 102 is a p-type semiconductor layer that has 4H-SiC as a main composition, and includes p-type impurities. To protect a pn junction formed at an interface between the adjacent first conductor layer 101 and the second conductor layer 102, an insulating film 103 is so formed on a side wall 104 as to coat an end 31. The direction of an axis C1 extending in the normal direction of the principal surface of the side wall 104 tilts in a range of 25-45° from a (0001) axis direction toward a (01-10) axis direction. Consequently, since an interface state (interface state density) between the insulating film and the end of the pn junction is decreased, the leakage current is reduced and current properties are improved. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a SiC semiconductor device having 4H-SiC (4-period hexagonal silicon carbide having a stacking period of 4) as a main composition and having adjacent P-type and N-type semiconductor layers forming a PN junction. .

  SiC has a high dielectric breakdown electric field, and research and development aiming at realization of a semiconductor device having a high breakdown voltage and an ultra-low loss that could not be realized by a conventional Si semiconductor device is being actively conducted. Examples of semiconductor devices using SiC include PN diodes, PiN diodes, and NPN transistors. Hereinafter, the structure of a conventional semiconductor device will be described.

FIG. 11 shows an example of the structure of a conventional SiC semiconductor device (PiN diode) manufactured using a 4H—SiC substrate. This figure also shows an example of termination of the PN junction end. In SiC semiconductor device 2a, on ^{N +} bulk layer 201 made of SiC containing a high concentration of N-type impurity, N made of SiC containing a low concentration of N type impurity ^- and drift layer 202 is formed, N ^- drift On the layer 202, a P ⁺ anode layer 203 made of SiC containing a high-concentration P-type impurity is formed. A PN junction is formed at the interface between the adjacent N ⁻ drift layer 202 and P ⁺ anode layer 203.

The PN junction first protective film 204 and the PN junction second made of an insulator such as a thermal oxide film so that the PN junction covers the end 41 exposed on the surfaces of the N ⁻ drift layer 202 and the P ⁺ anode layer 203. A protective film 205 is formed. In this way, the inactivation process is performed on the end portion of the PN junction. On the P ⁺ anode layer 203, an anode electrode 206 is formed in an opening formed by removing a part of the PN junction first protective film 204 and the PN junction second protective film 205. On the anode electrode 206, a lead electrode 207 for electrical connection with the outside is formed. A cathode electrode 208 is formed on the main surface of the N ⁺ bulk layer 201 facing the main surface on which the N ⁻ drift layer 202 is formed.

FIG. 12 shows an example of the structure of a conventional SiC semiconductor device (NPN transistor) manufactured using a 4H—SiC substrate. This figure also shows an example of termination of the PN junction end. In SiC semiconductor device 2b, on ^{N +} bulk layer 211 made of SiC containing a high concentration of N-type impurity, N made of SiC containing a low concentration of N type impurity ^- and drift layer 212 is formed, N ^- drift A P-type base layer 213 made of SiC containing P-type impurities is formed on the layer 212. In the surface region of the P-type base layer 213, a P ⁺ base contact layer 214 containing a high-concentration P-type impurity is formed. On the P-type base layer 213, an N ⁺ emitter layer 215 made of SiC containing a high-concentration N-type impurity is formed.

A P-type device termination layer 216 is formed on the surface of the N ^- drift layer 212 in a region where the P-type base layer 213 is not formed. N ^- collector electrode 217 is formed on the main surface of the opposite side of the ^{N +} bulk layer 211 and the main surface of the ^{N +} bulk layer 211 drift layer 212 is formed. An emitter electrode 218 is formed on the N ⁺ emitter layer 215, and a base electrode 219 is formed on the P ⁺ base contact layer 214. A PN junction is formed at the interface between the adjacent P-type base layer 213 and N ⁺ emitter layer 215. A PN junction protective film 220 made of an insulator such as a thermal oxide film is formed so that the PN junction covers the end portion 42 exposed on the surfaces of the P-type base layer 213 and the N ⁺ emitter layer 215. In this way, the inactivation process is performed on the end portion of the PN junction. Non-Patent Document 1 describes a SiC-PN diode, and Non-Patent Document 2 describes a SiC-NPN transistor.
Camara N. and 3 others, "Influence of mesa wall etching on forward bias degradation in 4H-SiC pin diodes", 5th European Conference on Silicon Carbide and Related Materials (ECSCRM2004), (Italy), Trans Tech Publications Inc., Aug. 31-Sept.4, p.560-561 Anant K. Agarwal and 10 others, "Recent Progress in SiC Bipolar Junction Transistors", Proceedings of 2004 International Symposium on Power Semiconductor Devices & ICs, Institute of Electrical Engineers of Japan, p.361-364

  In the PN junction end portion of the PiN diode shown in FIG. 11, the insulating film formation process may be insufficient. Therefore, there is a problem that the reverse leakage current of the diode is large and affects the current characteristics.

Further, the deactivation process may be inappropriate at the PN junction end between the P-type base layer 213 and the N ⁺ emitter layer 215 of the NPN transistor shown in FIG. As a result, the base current injected from the base leaks through the interface state existing at the insulator-semiconductor interface, and the base current corresponding to the base current cannot contribute to the current amplification function. Therefore, there is a problem that the current amplification factor of the transistor becomes small and affects the current characteristics.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a SiC semiconductor device that can reduce leakage current and improve current characteristics.

  The present invention has been made to solve the above problems, and the invention according to claim 1 includes a first semiconductor layer of a first conductivity type having a main composition of 4H—SiC and forming a PN junction, and An SiC semiconductor device comprising: a second semiconductor layer of a second conductivity type; and an insulating film that covers the PN junction exposed on the surfaces of the first semiconductor layer and the second semiconductor layer. The exposed end portion has a main surface perpendicular to an axis inclined from 25 degrees to 45 degrees in the <01-10> axial direction from the [0001] axial direction or the [000-1] axial direction. The SiC semiconductor device is characterized.

  According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the main surface is 30 degrees or more 39 in the <01-10> axial direction from the [0001] axial direction or the [000-1] axial direction. The main surface is perpendicular to an axis inclined at a degree or less.

  According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the main surface extends from the [0001] axial direction or the [000-1] axial direction to the <01-10> axial direction. It is a {03-38} plane inclined by 35.3 degrees.

  According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects of the present invention, the PN junction is less than the [0001] axial direction or the [000-1] axial direction. 01-10> An axis inclined by less than 25 degrees in the axial direction, or a plane perpendicular to an axis inclined by more than 45 degrees and the principal surface are separated from the intersecting portion.

  According to the present invention, since the interface state (interface state density) between the insulating film and the end of the PN junction is reduced, the effect of reducing the leakage current and improving the current characteristics is obtained. It is done.

  The best mode for carrying out the present invention will be described below with reference to the drawings. First, crystal axes used for explaining the present invention will be described. In the description of the present invention, a hexagonal crystal axis based on the Miller index of crystallography is used. The crystal axis extending in the normal direction of the main surface of the 4H—SiC substrate serving as the base of the SiC semiconductor device of the present invention is the [0001] axis or the [000-1] axis, and the main surface corresponding to each crystal axis is The (0001) plane or the (000-1) plane. [000-1] is equivalent to the notation shown in the following [Equation 1].

  A plurality of equivalent crystal axes are collectively represented by <>. For example, the <01-10> axis includes the [01-10] axis, [0-110] axis, [1-100] axis, [-1100] axis, [10-10] axis, and [-1010] axis. Is equivalent. Similarly, a plurality of equivalent crystal planes are collectively represented by {}. For example, the {0001} plane is equivalent to the (0001) plane and the (000-1) plane.

  Next, a first embodiment of the present invention will be described. FIG. 1 shows a cross-sectional structure of the SiC semiconductor device according to the present embodiment. In the SiC semiconductor device 1a (SiC-PN diode), the first conductor layer 101 is an N-type semiconductor layer containing 4H—SiC as a main composition and containing an N-type impurity. A second conductor layer 102 is formed on the first conductor layer 101. The second conductor layer 102 is a P-type semiconductor layer having a main composition of 4H—SiC and containing P-type impurities. The side walls 104 of the first conductor layer 101 and the second conductor layer 102 are inclined surfaces that are inclined with respect to the main surface 101 a of the first conductor layer 101.

  A PN junction is formed at the interface between the adjacent first conductor layer 101 and second conductor layer 102. In order to protect the PN junction, the insulating film 103 made of an insulating material such as a thermal oxide film so that the PN junction covers the end portion 31 exposed on the surfaces of the first conductor layer 101 and the second conductor layer 102. Is formed on the side wall 104.

  The crystal axis extending in the upper direction in FIG. 1 (the normal direction of the main surface 101a of the first conductor layer 101) is the [0001] axis. The crystal axis extending in the left direction in FIG. 1 perpendicular to the [0001] axis is the [01-10] axis. The main surface 101a of the first conductor layer 101 is a (0001) plane. The direction of the axis C1 extending in the normal direction of the main surface of the side wall 104 is inclined by θ1 from the [0001] axis direction to the [01-10] axis direction. The range of θ1 is desirably 25 degrees or more and 45 degrees or less. Furthermore, it is more desirable that the range of θ1 is not less than 30 degrees and not more than 39 degrees. Furthermore, it is more desirable that θ1 is 35.3 degrees. When θ1 is 35.3 degrees, the main surface of the sidewall 104 is a (03-38) plane. The hexagonal (03-38) plane corresponds to a cubic (001) plane and has a small number of insulator-semiconductor interface states. However, if an error due to manufacturing conditions is taken into consideration, it is desirable that θ1 be 34 degrees or more and 36 degrees or less.

  In the above description, the inclination of the main surface of the side wall 104 has been described. More specifically, the end portion 31 including the PN junction end exposed on the surfaces of the first conductor layer 101 and the second conductor layer 102 is formed. It is desirable that the inclination of the included main surface satisfies the above conditions. The end 31 is a region in the vicinity of the PN junction end P1 on the side wall 104, and is a region within a radius of 0.1 μm, within a radius of 0.3 μm, or within a radius of 0.5 μm around the PN junction end P1. That is, the end portion 31 is in a main surface perpendicular to an axis inclined from 25 degrees to 45 degrees from the [0001] axis direction to the [01-10] axis direction. Microscopically, the main surface is an end portion. 31, and macroscopically, the main surface is the main surface of the side wall 104. In an ideal state where the surface is not rough, the main surface of the end portion 31 and the main surface of the side wall 104 coincide.

  The principal surface 101a of the first conductor layer 101 may be a (000-1) plane, and the axis C1 has an inclination of θ1 from the [000-1] axis direction to the [01-10] axis direction. It may be. In consideration of a crystal axis equivalent to the [01-10] axis, the axis C1 may be inclined by θ1 from the [0001] axis direction or the [000-1] axis direction to the <01-10> direction. When θ1 is 35.3, the plane perpendicular to the axis C1 is the {03-38} plane.

  The PN junction at the interface between the two semiconductor layers has an axis inclined less than 25 degrees from the [0001] axis direction or the [000-1] axis direction to the <01-10> axis direction, or an axis inclined more than 45 degrees. A first vertical surface and a second surface (for example, the side wall 104) perpendicular to an axis tilted from the [0001] axial direction or the [000-1] axial direction to the <01-10> axial direction by 25 degrees or more and 45 degrees or less. It is desirable to be exposed on the second surface at a position isolated from the intersecting portion formed by intersecting with the main surface.

  Next, the reason why the range of the inclination θ1 of the axis C1 is the above range will be described. FIG. 2 is a numerical calculation result of the number of dangling bonds (number of unbonded hands) on the 4H—SiC surface. The horizontal axis is the inclination angle measured from the <0001> axial direction to the <01-10> axial direction or the <11-20> axial direction, and the vertical axis is dangling per unit area. The number of bonds. When the inclination angle is 90 degrees, the 4H—SiC surface is a {01-10} plane or a {11-20} plane.

  As shown in FIG. 2, when the tilt angle increases from 0 degree, the dangling bond number decreases monotonously, and the tilt angle becomes minimum at 35.3 degrees. When the tilt angle increases beyond 35.3 degrees, the number of dangling bonds increases monotonously. In the conventional semiconductor device, the main surface including the PN junction end is the {01-10} plane or the {11-20} plane. In FIG. 2, the number of dangling bonds on the {01-10} plane is represented by point A, and the number of dangling bonds on the {11-20} plane is represented by point B.

When the number of dangling bonds per unit area decreases, the interface state (interface state density) decreases, and as a result, the leakage current decreases. Therefore, in order to reduce the leakage current as compared with the conventional structure, the number of dangling bonds per unit area is desirably 0.3 × 10 ¹⁶ (cm ⁻² ) or less, and the inclination angle is 25 correspondingly. It is desirable that it is not less than 45 degrees and not more than 45 degrees. Further, the number of dangling bonds per unit area is more preferably 0.2 × 10 ¹⁶ (cm ⁻² ) or less, and the inclination angle is preferably 30 ° to 39 ° correspondingly. The inclination angle is more preferably 35.3 degrees at which the number of dangling bonds is minimized.

  Next, the method for fabricating the semiconductor device 1a according to the present embodiment will be explained with reference to FIG. P-type SiC is deposited on the first conductivity type layer 101 constituting the N-type SiC substrate by a CVD (Chemical Vapor Deposition) method or the like to form the second conductivity type layer 102 (FIG. 3A). In order to facilitate the CVD growth of the second conductivity type layer 102, the main surface 101a of the first conductivity type layer 101 is preferably subjected to chemical mechanical polishing, but may be omitted. The second conductor layer 102 may be formed by injecting Al or B into the surface of the first conductor layer 101 by ion implantation and heating to 1500 ° C. or higher.

Subsequently, after forming an etching mask (not shown) on the second conductor layer 102 and patterning the etching mask, a dry etching process is performed on the window portion of the etching mask in a dry etching apparatus. For example, the dry etching process is performed under the following conditions. The gas type used for etching is a mixed gas of CF ₄ and O ₂ , and the mixing ratio of O ₂ occupying the entire mixed gas is about 10 to 90% in terms of flow rate. As a gas species, CHF, CF ₆ , or a mixed gas composed of a combination of CF ₃ and O ₂ may be used.

After the etching gas is introduced in the vicinity of the induction coil in the processing chamber of the dry etching apparatus, 2.45 GHz high frequency power of 200 W to 1000 W is applied to the induction coil to generate CF ₄ and O ₂ plasma. As the power applied to the induction coil, it is desirable to use a 2.45 GHz microwave capable of forming plasma with high density, but a 13.56 MHz radio wave may be used.

  Usually, in order to perform etching with a high aspect ratio, a high voltage of, for example, about 1000 V is applied to the sample stage on which the sample is placed, and the sample is positively irradiated with positively charged plasma, Increase anisotropy. In this embodiment, etching is performed by adjusting the voltage applied to the sample stage to, for example, about 0 to 500 V so that the etching surface where the PN junction is exposed is inclined with respect to the main surface of the SiC substrate. . This voltage is desirably 300 V or less, and more desirably 200 V or less. As a result, the side wall 104 having a principal surface perpendicular to the axis inclined from 25 degrees to 45 degrees from the [0001] axis direction to the [01-10] axis direction is formed (FIG. 3B).

Subsequently, an insulating film 103 is formed on the first conductive type layer 101 and the second conductive type layer 102 by a thermal oxidation method, and the insulating film 103 is patterned (FIG. 3C). The exposed PN junction is protected by the insulating film 103. As a method for forming the insulating film, an insulating film deposited by a CVD method may be used. As a gas used at the time of thermal oxidation, O ₂ , N ₂ O, NO, or the like can be used. The furnace temperature when forming the thermal oxide film is, for example, in the range of 900 to 1400 ° C. This is due to favorable insulating film formation conditions for each gas type and manufacturing restrictions. The semiconductor device 1a is completed through the above steps.

  As described above, in this embodiment, the end portion of the PN junction exposed on the surfaces of the P-type semiconductor layer and the N-type semiconductor layer is <01-10> from the [0001] axial direction or the [000-1] axial direction. A main surface perpendicular to the axis inclined by the aforementioned angle in the axial direction is provided, and the PN junction is exposed on the surface of the semiconductor layer in this main surface. As a result, even if the end portion of the PN junction is covered with the protective insulating film, the interface state (interface state density) between the insulating film and the end portion of the PN junction is reduced as compared with the conventional case. The reverse leakage current of the diode can be reduced and the current characteristics can be improved.

Next, a second embodiment of the present invention will be described. FIG. 4 shows a cross-sectional structure of the SiC semiconductor device according to the present embodiment. In the SiC semiconductor device 1b (SiC-PiN diode), the N ⁺ bulk layer 111 is a layer containing 4H-SiC having a low resistance containing a high concentration of N-type impurities, and constitutes an N-type SiC substrate. An N ⁻ drift layer 112 is formed on the N ⁺ bulk layer 111. The N ⁻ drift layer 112 is a layer containing high-resistance 4H—SiC containing a low concentration N-type impurity.

A P ⁺ anode layer 113 is formed on the N ⁻ SiC layer 112. The P ⁺ anode layer 113 is a layer that includes low-resistance 4H—SiC containing a high concentration of P-type impurities. Sidewalls 119 of N ⁻ drift layer 112 and P ⁺ anode layer 113 are inclined surfaces having an inclination with respect to main surface 111 a of N ⁺ bulk layer 111. A PN junction is formed at the interface between the adjacent N ⁻ drift layer 112 and P ⁺ anode layer 113.

In order to protect this PN junction, the first PN junction made of an insulator such as thermal oxynitride is used so as to cover the end 32 exposed on the surfaces of the N ⁻ drift layer 112 and the P ⁺ anode layer 113. A protective film 114 is formed on the side wall 119. A PN junction second protective film 115 made of an insulator such as a nitride is formed on the PN junction first protective film 114. When the semiconductor device 1 b is viewed from a direction perpendicular to the (0001) plane, the PN junction first protective film 114 and the PN junction second protective film 115 are formed in a ring shape so as to surround the N ⁻ drift layer 112. Yes.

On the P ⁺ anode layer 113, an anode electrode 116 is formed in an opening formed by removing a part of the PN junction first protective film 114 and the PN junction second protective film 115. The anode electrode 116 is in ohmic contact with the P ⁺ anode layer 113, and is formed, for example, by annealing a laminated film deposited in the order of Ti and Al from the P ⁺ anode layer 113 side at 900 ° C. or higher. Electrode. On the anode electrode 116, an extraction electrode 117 for electrical connection with the outside is formed. The extraction electrode 117 is made of Al, Ni, Au, or the like. A cathode electrode 118 is formed on the main surface of the N ⁺ bulk layer 111 facing the main surface 111a on which the N ⁻ drift layer 112 is formed. The cathode electrode 118 is in ohmic contact with the N + bulk layer 111, and is an electrode formed by, for example, annealing at 900 ° C. or higher after depositing Ni.

The crystal axis extending in the upper direction in FIG. 4 (N ⁺ normal direction of the main surface 111a of the bulk layer 111) is the [0001] axis. Further, the crystal axis extending in the left direction in FIG. 4 perpendicular to the [0001] axis is the [01-10] axis. The direction of the axis C2 extending in the normal direction of the main surface of the side wall 119 is inclined by θ2 from the [0001] axis direction toward the [01-10] axis direction. The range of θ2 is desirably 25 degrees or more and 45 degrees or less. Furthermore, it is more desirable that the range of θ2 is 30 degrees or more and 39 degrees or less. Furthermore, it is more desirable that θ2 is 35.3 degrees. However, if an error due to manufacturing conditions is taken into consideration, it is desirable that θ2 be 34 degrees or more and 36 degrees or less. The main surface may be a macroscopic main surface in the entire side wall 119 or a main surface in a microscopic region near the end portion 32 of the PN junction.

Next, the method for fabricating the semiconductor device 1b according to the present embodiment will be explained with reference to FIGS. On the main surface 111a of the low-resistance N ⁺ bulk layer 111 that lowers the series resistance, a high-resistance N ⁻ drift layer 112 having an impurity concentration and a thickness necessary for ensuring a breakdown voltage is formed by a CVD method or the like. (FIG. 5 (a)). Subsequently, a P ⁺ anode layer 113 is formed on the surface of the N ⁻ drift layer 112 by a CVD method or the like (FIG. 5B). The P ⁺ anode layer 113 may be formed by injecting Al or B into the surface of the N ⁻ drift layer 112 by ion implantation and then heating to 1500 ° C. or higher.

Subsequently, as in the first embodiment, a dry etching process is performed to expose the side wall 119. Further, a PN junction first protective film 114 is formed by forming a thermal oxynitride film using N ₂ O gas at 1200 ° C. on the surface of the sidewall 119 including the exposed PN junction. Subsequently, a PN junction second protective film 115 is formed on the surface of the PN junction first protective film 114 by depositing a nitride film by a CVD method. The PN junction second protective film 115 acts as a protective film for the PN junction and has an effect of protecting the PN junction first protective film 114 from acid treatment during electrode etching described later. Part of the PN junction first protective film 114 and the PN junction second protective film 115 formed as described above is removed by acid treatment to expose part of the P ⁺ anode layer 113 (FIG. 5C). .

Subsequently, the anode electrode 116 and the extraction electrode 117 are formed as follows. Ti and Al are deposited in this order on the surfaces of the P ⁺ anode layer 113 and the PN junction second protective film 115, leaving a portion corresponding to the anode electrode 116 and removed by acid treatment. Further, for example, Al is deposited on the surfaces of the anode electrode 116 and the PN junction second protective film 115 by an evaporation method, and then removed by acid treatment, leaving a portion corresponding to the extraction electrode 117 (FIG. 6A )).

Subsequently, Ni is deposited from the back side of the N ⁺ bulk layer 111 by vapor deposition or the like, and then annealed at 900 ° C. or more to form the cathode electrode 118 (FIG. 6B). The semiconductor device 1b is completed through the above steps.

  According to the present embodiment, since the interface state (interface state density) between the insulating film and the end of the PN junction is reduced as compared with the first embodiment, the reverse leakage current of the diode is reduced. And the current characteristics can be improved.

Next, a third embodiment of the present invention will be described. FIG. 7 shows a cross-sectional structure of the SiC semiconductor device according to the present embodiment. The SiC semiconductor device 1c is a SiC-NPN transistor, and has a unit cell 10 as a basic structure, and has a structure in which a plurality of the same structures as the unit cell 10 are arranged in the horizontal direction in FIG. In FIG. 7, only the basic structure is shown, and the repeated structure is not shown. In the SiC semiconductor device 1c, the N ⁺ bulk layer 121 is a layer containing 4H—SiC having a low resistance containing a high concentration of N-type impurities, and constitutes an N-type SiC substrate. An N ⁻ drift layer 122 is formed on the N ⁺ bulk layer 121. The N ⁻ drift layer 122 is a layer containing high-resistance 4H—SiC containing a low concentration N-type impurity.

On the N ⁻ drift layer 122, a P-type base layer 123 having 4H—SiC containing P-type impurities as a main composition is formed. An N ⁺ emitter layer 124 is formed on the P-type base layer 123. The N ⁺ emitter layer 124 is a layer containing 4H—SiC having a low resistance and containing a high concentration of N-type impurities. The N ⁺ emitter layer 124 is formed by a CVD method, but may be formed by injecting P or N into the surface of the P-type base layer 123 by ion implantation and then heating to 1500 ° C. or higher.

In the surface region of the P-type base layer 123, a P ⁺ base contact layer 125 containing a high-concentration P-type impurity is formed. A P-type device termination layer 126 is formed in a region of the surface of the N ⁻ drift layer 122 excluding the region where the P-type base layer 123 is formed. Side walls 131 of the P-type base layer 123 and the N ⁺ emitter layer 124 are inclined surfaces that are inclined with respect to the main surface 121 a of the N ⁺ bulk layer 121. A PN junction is formed at the interface between the adjacent P-type base layer 123 and N ⁺ emitter layer 124.

In order to protect the PN junction, the PN junction is made of an insulating material such as a thermal oxide film or a thermal oxynitride so as to cover the end portion 33 exposed on the surfaces of the P-type base layer 123 and the N ⁺ emitter layer 124. A PN junction protective film 127 is formed on the side wall 131. The PN junction protective film 127 covers all or part of the surfaces of the N ⁺ emitter layer 124, the P-type base layer 123, the P ⁺ base contact layer 125, the P-type device termination layer 126, and the N ⁻ drift layer 122. Thus, it mainly serves to protect the PN junction between the P-type base layer 123 and the N ⁺ emitter layer 124.

An emitter electrode 128 is formed on the N ⁺ emitter layer 124, and a base electrode 129 is formed on the P ⁺ base contact layer 125. The emitter electrode 128 is in ohmic contact with the N ⁺ emitter layer 124 and is an electrode annealed at a temperature of 900 ° C. or higher after depositing, for example, Ni. The base electrode 129 is formed an ohmic contact with the P ⁺ base contact layer 125, for example, after being stacked from P ⁺ base contact layer 125 side of Ti and Al in this order, a laminated film and annealed at 900 ° C. or higher temperature It is an electrode. A collector electrode 130 is formed on the surface of the N ⁺ bulk layer 121 opposite to the main surface of the N ⁺ bulk layer 121 where the N ⁻ drift layer 122 is formed. The collector electrode 130 is an electrode annealed at a temperature of 900 ° C. or higher after Ni is deposited by, for example, an evaporation method.

The crystal axis extending in the upper direction in FIG. 7 (N ⁺ normal direction of the main surface 121a of the bulk layer 121) is the [0001] axis. Further, the crystal axis extending in the left direction in FIG. 7 perpendicular to the [0001] axis is the [01-10] axis. The direction of the axis C3 extending in the normal direction of the main surface of the side wall 131 is inclined by θ3 from the [0001] axis direction toward the [01-10] axis direction. The range of θ3 is desirably 25 degrees or more and 45 degrees or less. Furthermore, it is more desirable that the range of θ3 is 30 degrees or more and 39 degrees or less. Furthermore, it is more desirable that θ3 is 35.3 degrees. However, if an error due to manufacturing conditions is taken into consideration, it is desirable that θ3 be 34 degrees or more and 36 degrees or less. The main surface may be a macroscopic main surface in the entire side wall 131 or a main surface in a microscopic region near the end portion 33 of the PN junction.

  FIG. 8 is a plan view of the semiconductor device 1c viewed in the [000-1] axial direction. The emitter electrode 128 and the base electrode 129 have a rectangular shape with rounded corners, and a plurality of emitter electrodes 128 and a plurality of base electrodes 129 are arranged so that the major axis faces the <11-20> axis direction. The P-type device termination layer 126 is arranged in a ring shape so as to surround the entire cell structure.

Next, the method for fabricating the semiconductor device 1c according to the present embodiment will be explained with reference to FIGS. On the main surface 121a of the low-resistance N ⁺ bulk layer 121 that lowers the series resistance, a high-resistance N ⁻ drift layer 122 having an impurity concentration and a thickness necessary for ensuring a breakdown voltage is formed by a CVD method or the like. . Subsequently, a P-type base layer 123 having an impurity concentration and a thickness necessary for acting as a base layer of the transistor is formed on the surface of the N ⁻ drift layer 122 by a CVD method or the like. Subsequently, an N ⁺ emitter layer 124 for acting as an emitter layer of the transistor is formed on the surface of the P-type base layer 123 by a CVD method or the like (FIG. 9A). The N ⁺ emitter layer 124 may be formed by injecting N or P into the surface of the P-type base layer 123 by ion implantation and then heating to 1500 ° C. or higher.

Subsequently, the peripheral portions of the P-type base layer 123 and the N ⁺ emitter layer 124 are removed by dry etching to form a groove for forming the P-type device termination layer 126 (FIG. 9B). Further, as in the first embodiment, a dry etching process is performed to expose the side wall 131.

Subsequently, the P-type device termination portion 126 and the P ⁺ base contact layer 125 are formed as follows. An oxide film as an ion implantation mask is formed on the surfaces of the N ⁻ drift layer 122, the P-type base layer 123, and the N ⁺ emitter layer 124 by a CVD method, followed by a photographic process (exposure and development), and an acid treatment. Then, the oxide film at the position corresponding to the P-type device termination layer 126 is removed, and the portion of the N ⁻ drift layer 122 is exposed. Subsequently, for example, Al is implanted from the exposed portion by ion implantation.

Further, an oxide film is formed as an ion implantation mask on the surfaces of the N ⁻ drift layer 122, the P-type base layer 123, and the N ⁺ emitter layer 124 by a CVD method, and then a photographic process is performed to perform P ⁺ by acid treatment. The oxide film at the position corresponding to the base contact layer 125 is removed, and the P-type base layer 123 at that portion is exposed. Subsequently, for example, Al is implanted from the exposed portion so as to have a high concentration by ion implantation. In order to activate the implanted impurities, the oxide film used as an ion implantation mask is removed, and then a heat treatment at 1500 ° C. or higher is performed to form a P ⁺ base contact layer 125 and a P-type device termination layer 126 (FIG. 9 (c)).

Subsequently, a PN junction protective film 127 is formed as follows. The whole structure is thermally oxidized or thermally oxynitrided to form an insulating film (not shown) on the entire surface, and then subjected to a photographic process, and then acid treatment to correspond to the N ⁺ emitter layer 124 and the P ⁺ base contact layer 125 The insulating film at the position is removed, and parts of the surfaces of the N ⁺ emitter layer 124 and the P ⁺ base contact layer 125 are exposed. The remaining insulating film becomes the PN junction protective film 127 (FIG. 10A).

Subsequently, an emitter electrode 128 and a base electrode 129 are formed by a lift-off method. The emitter electrode 128 is formed by depositing Ni on the N ⁺ emitter layer 124 by vapor deposition, for example. The base electrode 129 is formed by laminating Ti and Al in this order, for example, by vapor deposition. After depositing the emitter electrode material and the base electrode material, Ni is deposited on the back surface of the N ⁺ bulk layer 121 by, eg, vapor deposition to form the collector electrode 130. After depositing the collector electrode material, an annealing treatment at 900 ° C. or higher is performed. As a result, ohmic contacts are formed between the N ⁺ emitter layer 124 and the emitter electrode 128, between the P ⁺ base contact layer 125 and the base electrode 129, and between the N ⁺ bulk layer 121 and the collector electrode 130. The semiconductor device 1c is completed through the above steps.

  According to the present embodiment, since the interface state (interface state density) between the insulating film and the end of the PN junction is reduced as compared with the prior art, the leakage of the base current is reduced as in the first embodiment. In addition, the current amplification factor of the NPN transistor can be improved. Therefore, the current characteristics of the NPN transistor are improved.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to these embodiments, and includes design changes and the like without departing from the gist of the present invention. . For example, the present invention is used as a method for protecting PN junctions of various semiconductor devices such as SiC thyristors, SiC-SITs (electrostatic induction transistors), and SiC-GTOs as well as SiC-PiN diodes and SiC-NPN transistors. Can do. In addition, the specific materials and layer configurations described in the above-described embodiments are merely examples, and can be changed as appropriate.

1 is a schematic cross-sectional view showing a cross-sectional structure of a SiC semiconductor device according to a first embodiment of the present invention. It is a graph which shows the numerical calculation result in the 1st Embodiment of this invention. It is a schematic cross section for demonstrating the manufacturing method of the SiC semiconductor device by the 1st Embodiment of this invention. It is a schematic cross section which shows the cross-section of the SiC semiconductor device by the 2nd Embodiment of this invention. It is a schematic cross section for demonstrating the manufacturing method of the SiC semiconductor device by the 2nd Embodiment of this invention. It is a schematic cross section for demonstrating the manufacturing method of the SiC semiconductor device by the 2nd Embodiment of this invention. It is a schematic cross section which shows the cross-section of the SiC semiconductor device by the 3rd Embodiment of this invention. It is a top view of the SiC semiconductor device by a 3rd embodiment of the present invention. It is a schematic cross section for demonstrating the manufacturing method of the SiC semiconductor device by the 3rd Embodiment of this invention. It is a schematic cross section for demonstrating the manufacturing method of the SiC semiconductor device by the 3rd Embodiment of this invention. It is a schematic cross section showing a cross-sectional structure of a conventional SiC semiconductor device. It is a schematic cross section showing a cross-sectional structure of a conventional SiC semiconductor device.

Explanation of symbols

1a, 1b, 1c, 2a, 2b Semiconductor device, 10 unit cell, 31, 32, 33, 41, 42 end, 101 first conductivity type layer, 101a, 111a, 121a main surface, 102 second conductivity type layer, 103 insulating film, 104, 119, 131 sidewall, 111, 121, 201, 211 N ⁺ bulk layer, 112, 122, 202, 212 N ⁻ drift layer, 113, 203 P ⁺ anode layer, 114, 204 PN junction first Protective film, 115, 205 PN junction second protective film, 116, 206 anode electrode, 117, 207 lead electrode, 118, 208 cathode electrode, 123, 213 P-type base layer, 124, 215 N ⁺ emitter layer, 125, 214 P ⁺ base contact layer, 126,216 P-type device termination layer, 127,220 PN junction protective film, 128,21 The emitter electrode, 129,219 base electrode, 130,217 collector electrode

Claims (4)

A first conductive type first semiconductor layer and a second conductive type second semiconductor layer forming a PN junction with 4H—SiC as a main composition, and the first semiconductor layer and the second semiconductor layer. In an SiC semiconductor device comprising an insulating film covering the PN junction exposed on the surface,
The exposed end of the PN junction has a principal surface perpendicular to an axis inclined from 25 degrees to 45 degrees in the <01-10> axial direction from the [0001] axial direction or the [000-1] axial direction. A SiC semiconductor device characterized by comprising:   The main surface is a main surface perpendicular to an axis inclined at 30 degrees or more and 39 degrees or less from a [0001] axial direction or a [000-1] axial direction to a <01-10> axial direction. 2. The SiC semiconductor device according to 1.   The main surface is a {03-38} plane inclined by 35.3 degrees from the [0001] axial direction or the [000-1] axial direction to the <01-10> axial direction. The SiC semiconductor device described. The PN junction includes an axis inclined less than 25 degrees from the [0001] axis direction or the [000-1] axis direction to the <01-10> axis direction, or a plane perpendicular to an axis inclined more than 45 degrees. The SiC semiconductor device according to any one of claims 1 to 3, wherein the SiC semiconductor device is isolated from an intersecting portion intersecting with the main surface.

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