JP2006303360A - Through-wire board, composite board, and electronic apparatus - Google Patents

Through-wire board, composite board, and electronic apparatus Download PDF

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JP2006303360A
JP2006303360A JP2005126244A JP2005126244A JP2006303360A JP 2006303360 A JP2006303360 A JP 2006303360A JP 2005126244 A JP2005126244 A JP 2005126244A JP 2005126244 A JP2005126244 A JP 2005126244A JP 2006303360 A JP2006303360 A JP 2006303360A
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wiring
base material
substrate
exposed
board
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JP2006303360A5 (en
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Satoshi Yamamoto
敏 山本
Mikio Hashimoto
橋本  幹夫
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Fujikura Ltd
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Fujikura Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a through-wire board and a composite board with a high degree of designing a wire structure and provided with through-wires capable of highly dense three-dimensional mount, and to provide an electronic apparatus employing them. <P>SOLUTION: The through-wire board is provided with a base member (11) wherein a very small hole (12) tying at least two sides (11a or 11b and 11c) of the base member (11), and the through-wire (13) formed by filling a conductive substance in the very small hole (12), are provided, and at least part of the through-wire (13) is extended in a direction different from the thick direction of the base member (11) (all of the through-wire (13) in the case of Fig. 1). The composite board is disclosed, and the electronic apparatus is disclosed employing the through wire board and the composite board. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、電子デバイスや光学デバイス、MEMSデバイス等の高密度実装、またはそれらのデバイスを一つのパッケージ内でシステム化するSiP(システムインパッケージ)を可能にする貫通配線を備えた貫通配線基板や複合基板、及びこれらを用いた電子装置に関する。   The present invention relates to a through-wiring board having a through-wiring that enables high-density mounting of electronic devices, optical devices, MEMS devices, etc., or SiP (system-in-package) for systematizing these devices in one package, The present invention relates to a composite substrate and an electronic device using these.

近年、携帯電話等の電子機器の高機能化に伴い、それらに使われる電子デバイス等にも更なる高速化、高機能化が要求されている。これを実現するためには、微細化等によるデバイス自身の高速化だけではなく、デバイスのパッケージにも高速化、高密度化に向けた技術開発が必須となっている。   In recent years, with the enhancement of functions of electronic devices such as mobile phones, electronic devices and the like used for them have been required to have higher speed and higher functions. In order to realize this, not only the speed of the device itself by miniaturization and the like, but also the development of technology for the speed and density of the device package is indispensable.

高密度実装を実現する技術として、微細な貫通電極を用いてチップを積層実装する三次元実装や、貫通電極が形成された貫通配線基板を用いたSiPが提案されており、これを実現するための貫通電極形成技術や貫通配線基板の形成技術が活発に研究、開発されている。   In order to realize high-density mounting, three-dimensional mounting in which chips are stacked and mounted using fine through electrodes and SiP using a through wiring substrate on which through electrodes are formed have been proposed. The through electrode forming technology and the through wiring substrate forming technology have been actively researched and developed.

図19は、セラミックやシリコン等のリジッドな貫通配線基板を用いてなるSiP(Single in line Package)の模式的な断面図である。貫通配線基板191上に複数のデバイス195A、195Bが貫通電極193と電気的に接続するように実装されており、全体として一つのパッケージを形成している。その際、図19に示すように、従来の貫通配線基板においては、その表裏の主平面間を最短距離でつなぐように主平面に対して垂直に貫通電極が設けられていた。   FIG. 19 is a schematic cross-sectional view of a SiP (Single in line Package) using a rigid through wiring substrate such as ceramic or silicon. A plurality of devices 195 </ b> A and 195 </ b> B are mounted on the through wiring substrate 191 so as to be electrically connected to the through electrode 193, thereby forming a single package as a whole. At that time, as shown in FIG. 19, in the conventional through wiring substrate, through electrodes are provided perpendicular to the main plane so as to connect the main planes on the front and back sides with the shortest distance.

このような貫通電極を配してなるを貫通配線基板を用いたSiPにおいては、以下に示す技術的な問題点があった。
(1)三次元実装において、積層するデバイスが異種デバイスである場合、デバイスごとに必要な電極の数や電極のピッチが異なるため、これらの差異を解消するための表面配線や配線基板(インターポーザー)が必要になる。
(2)SiPにおいて使用される貫通配線基板においても、基板上に搭載されるデバイスの電極ピッチと、マザーボード等に実装される際のバンプピッチとに大きな差異があるため、貫通配線基板上にこれらの差異を解消するための配線形成が必要となる。
(3)貫通配線を用いた三次元的な実装とはいえ、貫通電極は基本的に基板表裏を貫通するものであるため、隣り合う貫通配線基板間を電気的に接続する際には小型化等に制約がある。
In SiP using such a through electrode and using a through wiring substrate, there are the following technical problems.
(1) In three-dimensional mounting, if the devices to be stacked are different devices, the number of electrodes required and the pitch of the electrodes differ from device to device, so surface wiring and wiring boards (interposers) to eliminate these differences ) Is required.
(2) Even in the through wiring substrate used in the SiP, there is a large difference between the electrode pitch of the device mounted on the substrate and the bump pitch when mounted on the mother board or the like. It is necessary to form a wiring for eliminating the difference.
(3) Although it is three-dimensional mounting using through wiring, since the through electrode basically penetrates the front and back of the board, it is reduced in size when electrically connecting adjacent through wiring boards. Etc. are limited.

上記問題点を解決する一例としては、所望の回路が形成されたチップ本体と、このチップ本体の表裏を貫通した複数の貫通孔にそれぞれ埋め込み形成された貫通電極とを備え、前記貫通孔が、前記チップ本体の主平面と垂直な方向に対し傾けて形成されている構成からなる半導体チップが挙げられる(特許文献1)。   As an example to solve the above problems, a chip body in which a desired circuit is formed and a through electrode embedded in a plurality of through holes penetrating the front and back of the chip body, the through hole, An example of the semiconductor chip is a structure in which the chip body is inclined with respect to a direction perpendicular to the main plane of the chip body (Patent Document 1).

上記半導体チップに採用された技術、すなわち基板を斜めに貫通する貫通電極を配線基板に応用すれば、単に基板表裏のピッチを変えることは可能となる。しかしながら、この場合においても、直線的な貫通電極であるが故に、貫通電極の位置的な制限が生じるので、電気的な接続手段となる貫通電極の露呈部はその配置が制限され、配線構造の設計自由度が低くなるため、より高密度な三次元実装を行うことは困難であった。
特開2003−347502号公報
If the technology employed in the semiconductor chip, that is, a through electrode that obliquely penetrates the substrate, is applied to the wiring substrate, it is possible to simply change the pitch between the front and back sides of the substrate. However, even in this case, since the position of the through electrode is limited because it is a straight through electrode, the arrangement of the exposed portion of the through electrode serving as an electrical connection means is limited, and the wiring structure Since the degree of freedom in design is low, it is difficult to perform higher-density three-dimensional mounting.
JP 2003-347502 A

本発明は上記事情に鑑みてなされたもので、配線構造の設計自由度が高く、高密度な三次元実装を可能とする貫通配線を備えた貫通配線基板や複合基板、及びこれらを用いた電子装置を提供することを目的とする。   The present invention has been made in view of the above circumstances, and has a high degree of freedom in designing a wiring structure, a through wiring substrate or a composite substrate having a through wiring that enables high-density three-dimensional mounting, and an electronic device using these. An object is to provide an apparatus.

本発明の請求項1に係る貫通配線基板は、基材を構成する少なくとも二面を結ぶように微細孔を配し、該微細孔に導電性物質を充填してなる貫通配線を備えた貫通配線基板であって、前記貫通配線は、少なくとも一部に、前記基材の厚み方向とは異なる方向に延びる部分を有することを特徴とする。
本発明の請求項2に係る貫通配線基板は、請求項1において、前記貫通配線の一端は前記基材の(一方の)主面に、前記貫通配線の他端は前記基材の(何れかの)側面に、それぞれ露呈されてなることを特徴とする。
本発明の請求項3に係る貫通配線基板は、請求項1において、前記貫通配線の一端は前記基材の一方の主面に、前記貫通配線の他端は前記基材の他方の主面に、それぞれ露呈されてなることを特徴とする。
本発明の請求項4に係る貫通配線基板は、請求項1において、前記貫通配線は、前記基材内に分岐する部分を備えていることを特徴とする。
本発明の請求項5に係る貫通配線基板は、請求項1において、前記貫通配線の一端及び/又は他端は、接合する他の基板の電極に対応する位置に配されていることを特徴とする。
本発明の請求項6に係る複合基板は、請求項1乃至5のいずれか1項に記載の貫通配線基板を複数用い、互いの主面同士及び/又は側面同士を重ね合わせ、互いの貫通配線基板を構成する貫通配線を電気的に接続してなることを特徴とする。
本発明の請求項7に係る電子装置は、請求項1乃至5のいずれか1項に記載の貫通配線基板又は請求項6に記載の複合基板に電子部品を実装してなることを特徴とする。
A through wiring board according to claim 1 of the present invention is a through wiring having a through hole in which a fine hole is arranged so as to connect at least two surfaces constituting a base material, and the fine hole is filled with a conductive substance. It is a board | substrate, Comprising: The said penetration wiring has a part extended in the direction different from the thickness direction of the said base material in at least one part, It is characterized by the above-mentioned.
The through wiring board according to claim 2 of the present invention is the through wiring substrate according to claim 1, wherein one end of the through wiring is on one side of the base material, and the other end of the through wiring is on the base material. It is characterized in that it is exposed on each side surface.
The through wiring board according to claim 3 of the present invention is the through wiring board according to claim 1, wherein one end of the through wiring is on one main surface of the base material, and the other end of the through wiring is on the other main surface of the base material. , Each of which is exposed.
According to a fourth aspect of the present invention, there is provided a through wiring substrate according to the first aspect, wherein the through wiring includes a portion branched into the base material.
The through wiring board according to claim 5 of the present invention is characterized in that, in claim 1, one end and / or the other end of the through wiring is arranged at a position corresponding to an electrode of another substrate to be joined. To do.
A composite substrate according to a sixth aspect of the present invention uses a plurality of the through wiring boards according to any one of the first to fifth aspects, and superimposes the main surfaces and / or the side surfaces to each other to form the through wirings. It is characterized in that the through wiring constituting the substrate is electrically connected.
An electronic device according to a seventh aspect of the present invention is characterized in that an electronic component is mounted on the through wiring board according to any one of the first to fifth aspects or the composite substrate according to the sixth aspect. .

本発明に係る貫通配線基板(請求項1)は、基材を構成する少なくとも二面を結ぶように微細孔を配し、該微細孔に導電性物質を充填してなる貫通配線を備え、この貫通配線が、少なくとも一部に、基材の厚み方向とは異なる方向に延びる部分を有するので、貫通配線はその一端を基材の一面に、他端を基材の全ての他面に、それぞれ露呈させる構成とすることができる。つまり、貫通配線の他端を露呈させる他面は、その一端を露呈させた一面と必ずしも対向する位置にある必要はない。ゆえに、本発明によれば、貫通配線を通じて基材を構成する、あらゆる面同士の間を電気的に接続できるので、より設計の自由度が高く、高密度実装あるいは三次元実装を可能とする貫通配線基板が得られる。   A through wiring board according to the present invention (Claim 1) includes a through wiring in which fine holes are arranged so as to connect at least two surfaces constituting a base material, and the fine holes are filled with a conductive substance. Since the through wiring has at least a part extending in a direction different from the thickness direction of the base material, the through wiring has one end on one surface of the base material and the other end on all other surfaces of the base material, respectively. It can be set as the structure to expose. In other words, the other surface that exposes the other end of the through wiring does not necessarily have to be in a position facing the one surface that exposes the other end. Therefore, according to the present invention, since all surfaces constituting the base material can be electrically connected to each other through the through wiring, the design freedom is high, and the penetration enabling high-density mounting or three-dimensional mounting is possible. A wiring board is obtained.

本発明に係る複合基板(請求項6)は、上記構成とした貫通配線基板を複数用い、互いの主面同士及び/又は側面同士を重ね合わせ、互いの貫通配線基板を構成する貫通配線を電気的に接続してなる。この構成によれば、同種あるいは異種の機能を備えた貫通配線基板を必要に応じて電気的に接続させることにより、接続能力の増加や接続機能の多角化などを適宜、図ることができる複合基板の提供が可能となる。ゆえに、本発明は、三次元実装やSiPにおいて、より高機能、高密度なパッケージをもたらし、ひいてはデバイスの高速化、高機能化に貢献する。   The composite substrate according to the present invention (Claim 6) uses a plurality of through-wiring boards having the above-described configuration, and superimposes the main surfaces and / or side surfaces of each other to electrically connect the through-wirings constituting each through-wiring substrate. Connected. According to this configuration, a composite circuit board capable of appropriately increasing connection capability and diversifying connection functions by electrically connecting through wiring boards having the same or different functions as necessary. Can be provided. Therefore, the present invention provides a higher-functionality and higher-density package in three-dimensional mounting and SiP, and thus contributes to higher speed and higher functionality of the device.

本発明の請求項7に係る電子装置は、上記構成とした貫通配線基板又は複合基板に電子部品を実装してなるので、電子装置の薄型化や小型化、低消費電力化などを図ることが可能となる。   Since the electronic device according to claim 7 of the present invention is formed by mounting electronic components on the through wiring board or the composite substrate having the above-described configuration, the electronic device can be reduced in thickness, size, power consumption, and the like. It becomes possible.

以下、本発明の一実施の形態について説明する。
図1〜7は、本発明に係る貫通配線基板の一例を示す断面図である。各図面に示すように、本発明の貫通配線基板は何れも、基材を構成する少なくとも二面を結ぶように微細孔を配し、該微細孔に導電性物質を充填してなる貫通配線を備えた貫通配線基板であり、前記貫通配線は、少なくとも一部に、前記基材の厚み方向とは異なる方向に延びる部分を有するので、貫通配線はその一端を基材の一面に、他端を基材の(全ての)他面に、それぞれ露呈させる構成とすることができる。これにより、貫通配線を通じて基材を構成する、あらゆる面同士の間を電気的に接続可能となる。
具体的は、次の4つの形態が挙げられる。なお、各形態の説明において直線部と表現した貫通配線の箇所は、これ(直線状)に限定されるものではなく、例えば曲線状や屈曲状としても構わない。
Hereinafter, an embodiment of the present invention will be described.
1-7 is sectional drawing which shows an example of the penetration wiring board based on this invention. As shown in each drawing, each of the through wiring boards of the present invention has a through hole formed by arranging a fine hole so as to connect at least two surfaces constituting a base material and filling the fine hole with a conductive substance. Since the through wiring has at least a part extending in a direction different from the thickness direction of the base material, the through wiring has one end on one surface of the base material and the other end. It can be set as the structure exposed to (all) other surfaces of a base material, respectively. Thereby, it becomes possible to connect electrically between all the surfaces which comprise a base material through penetration wiring.
Specifically, there are the following four forms. In addition, the location of the through wiring expressed as a straight portion in the description of each embodiment is not limited to this (straight shape), and may be a curved shape or a bent shape, for example.

<第一の形態>
第一の形態は、貫通配線の一端が基材の主面に、貫通配線の他端が基材の側面に、それぞれ露呈されてなる構成である。
図1に示すように、例えば貫通配線13が直線状をなし、貫通配線13自体が基材11の厚み方向(紙面の上下方向)とは異なる方向に延びている例が挙げられる。
図1(a)は貫通配線13の一端13αと他端13βがそれぞれ基材の一面(紙面の上面)11aと側面11cに露呈した場合を、図1(b)は貫通配線13の一端13αと他端13βがそれぞれ基材の他面(紙面の下面)11bと側面11cに露呈した場合を、各々示している。
<First form>
In the first form, one end of the through wiring is exposed on the main surface of the base material, and the other end of the through wiring is exposed on the side surface of the base material.
As shown in FIG. 1, for example, the through wiring 13 is linear, and the through wiring 13 itself extends in a direction different from the thickness direction of the base material 11 (up and down direction on the paper surface).
1A shows a case where one end 13α and the other end 13β of the through wiring 13 are exposed on one surface (upper surface of the paper) 11a and the side surface 11c of the substrate, respectively, and FIG. 1B shows one end 13α of the through wiring 13 and The cases where the other end 13β is exposed on the other surface (lower surface of the paper surface) 11b and the side surface 11c of the substrate are respectively shown.

また図2に示すように、例えば貫通配線23が2つの直線部と1つの屈曲部との組み合わせからなり、少なくとも1つの直線部が基材21の厚み方向(紙面の上下方向)とは異なる方向に延びている例も挙げられる。
図2(a)は貫通配線23をなす2つの直線部23a、23bが屈曲部24において接続されており、直線部23aは基材21の厚み方向に延びて紙面の上面21aに露呈する一端23αを、直線部23bは基材21の厚み方向と垂直をなす方向に延びて紙面の側面21cに露呈する他端23βを有する。
図2(b)は貫通配線23をなす2つの直線部23c、23dが屈曲部24において接続されており、直線部23cは基材21の厚み方向に延びて紙面の上面21aに露呈する一端23αを、直線部23dは基材21の厚み方向と傾斜をなす方向に延びて紙面の側面21cに露呈する他端23βを有する。
図2(c)は貫通配線23をなす2つの直線部23e、23fが屈曲部24において接続されており、直線部23eは基材21の厚み方向と傾斜をなす方向に延びて紙面の下面21bに露呈する一端23αを、直線部23fは基材21の厚み方向と垂直をなす方向に延びて紙面の側面21cに露呈する他端23βを有する。
As shown in FIG. 2, for example, the through wiring 23 is composed of a combination of two straight portions and one bent portion, and at least one straight portion is different from the thickness direction of the base material 21 (up and down direction on the paper surface). An example extending to
In FIG. 2A, two straight portions 23a and 23b constituting the through wiring 23 are connected at a bent portion 24, and the straight portion 23a extends in the thickness direction of the base material 21 and is exposed at one end 23α exposed on the upper surface 21a of the paper surface. The straight portion 23b has a second end 23β that extends in a direction perpendicular to the thickness direction of the substrate 21 and is exposed to the side surface 21c of the paper surface.
In FIG. 2B, two straight portions 23c and 23d forming the through wiring 23 are connected at the bent portion 24, and the straight portion 23c extends in the thickness direction of the base material 21 and is exposed at one end 23α exposed on the upper surface 21a of the paper surface. The straight portion 23d has the other end 23β that extends in a direction inclined with respect to the thickness direction of the base material 21 and is exposed to the side surface 21c of the paper surface.
In FIG. 2C, two straight portions 23e, 23f forming the through wiring 23 are connected at the bent portion 24, and the straight portion 23e extends in a direction that is inclined with respect to the thickness direction of the substrate 21, and is a lower surface 21b of the paper surface. The linear portion 23f has one end 23α that is exposed to the surface of the paper 21 and the other end 23β that extends in a direction perpendicular to the thickness direction of the substrate 21 and is exposed to the side surface 21c of the paper surface.

図1(図2)に示した構成例とするためには、基材11(21)をなす一方の主面11a(21a)又は他方の主面11b(21b)と、側面11c(21c)とを結ぶように、直線部をなす微細孔12(22)を設け、この微細孔12(22)に導電性物質を充填し、貫通配線13(23)を形成すればよい。   In order to obtain the configuration example shown in FIG. 1 (FIG. 2), one main surface 11a (21a) or the other main surface 11b (21b) forming the base material 11 (21), and a side surface 11c (21c) The fine holes 12 (22) forming a straight line portion may be provided so as to connect the conductive holes, and the through holes 13 (23) may be formed by filling the fine holes 12 (22) with a conductive substance.

<第二の形態>
第二の形態は、図3に示すように、貫通配線の一端が基材の一方の主面に、貫通配線の他端は基材の他方の主面に、それぞれ露呈されてなる構成である。
図3に示すように、例えば貫通配線33が複数の直線部と屈曲部との組み合わせからなり、少なくとも1つの直線部が基材31の厚み方向(紙面の上下方向)とは異なる方向に延びている例が挙げられる。図3(a)〜図3(d)は貫通配線33の一端33αと他端33βがそれぞれ基材の一面(紙面の上面)31aと他面(紙面の下面)31bに露呈している状態は共通しているが、以下の点において各々特長を有する。
図3(a)の構成例では、2つの直線部33a、33bが1つの屈曲部で結合されており、一方の直線部33bのみ基材31の厚み方向(紙面の上下方向)とは異なる方向に延びている。
図3(b)の構成例では、3つの直線部33c、33d、33eが2つの屈曲部で結合されており、中間の直線部33dのみ基材31の厚み方向(紙面の上下方向)とは異なる方向に延びている。
図3(c)の構成例では、2つの直線部33f、33gが1つの屈曲部で結合されている点は図2(a)と同様であるが、両方の直線部33f、33gとも基材31の厚み方向(紙面の上下方向)とは異なる方向に延びている。
図3(d)の構成例では、図3(b)の中間に配した1つの直線部に代えて、3つの直線部と2つの屈曲部33b、33cからなる部分33jを設けた点が図3(b)と異なる。図3(d)の33h、33jは、図3(b)の33c、33eに相当するものである。
図3に示した構成例とするためには、基材31をなす一方の主面31aと他方の主面31bとを結ぶように、複数の直線部と屈曲部とを組み合わせてなる微細孔32を設け、この微細孔32に導電性物質を充填し、貫通配線33を形成すればよい。
<Second form>
As shown in FIG. 3, the second form is a configuration in which one end of the through wiring is exposed on one main surface of the base material, and the other end of the through wiring is exposed on the other main surface of the base material. .
As shown in FIG. 3, for example, the through wiring 33 is composed of a combination of a plurality of straight portions and bent portions, and at least one straight portion extends in a direction different from the thickness direction of the base material 31 (up and down direction on the paper surface). An example is given. 3A to 3D show a state in which one end 33α and the other end 33β of the through wiring 33 are exposed on one surface (upper surface of the paper surface) 31a and the other surface (lower surface of the paper surface) 31b, respectively. Although common, each has the following features.
In the configuration example of FIG. 3A, two straight portions 33a and 33b are joined by a single bent portion, and only one straight portion 33b is different from the thickness direction of the base material 31 (vertical direction on the paper surface). It extends to.
In the configuration example of FIG. 3B, three straight portions 33c, 33d, and 33e are joined by two bent portions, and only the intermediate straight portion 33d is the thickness direction of the base material 31 (the vertical direction of the paper surface). It extends in different directions.
3C is the same as FIG. 2A in that the two straight portions 33f and 33g are joined by one bent portion, but both the straight portions 33f and 33g are base materials. It extends in a direction different from the thickness direction of 31 (the vertical direction of the paper).
In the configuration example of FIG. 3D, a portion 33j including three straight portions and two bent portions 33b and 33c is provided instead of one straight portion arranged in the middle of FIG. 3B. Different from 3 (b). 33h and 33j in FIG. 3 (d) correspond to 33c and 33e in FIG. 3 (b).
In order to obtain the configuration example shown in FIG. 3, the fine hole 32 formed by combining a plurality of linear portions and bent portions so as to connect one main surface 31 a forming the base material 31 and the other main surface 31 b. And the through hole 33 may be formed by filling the fine holes 32 with a conductive substance.

<第三の形態>
第三の形態は、図4に示すように、貫通配線の一端が基材の一方の主面に、貫通配線の他端は基材の他方の主面に、それぞれ露呈されてなる構成である。
図4に示すように、例えば貫通配線43が複数の直線部と分岐部との組み合わせからなり、少なくとも1つの直線部が基材41の厚み方向(紙面の上下方向)とは異なる方向に延びている例が挙げられる。
図4(a)〜図4(b)は分岐部から延びる貫通配線43の端部43α〜43δがそれぞれ基材の一面(紙面の上面)41aと他面(紙面の下面)41bに露呈している状態は共通しているが、以下の点において各々特長を有する。
図4(a)の構成例では、1つの分岐部44から直線部43a〜43cが個々に一面41a又は他面41bに延びている。
図4(b)の構成例では、2つの分岐部44a、44bから直線部43d〜43gが個々に一面41a又は他面41bに延びている。
図4に示した構成例とするためには、基材41をなす一方の主面41aと他方の主面41bとを結ぶように、複数の直線部と分岐部とを組み合わせてなる微細孔42を設け、この微細孔42に導電性物質を充填し、貫通配線43を形成すればよい。
<Third form>
As shown in FIG. 4, the third embodiment is configured such that one end of the through wiring is exposed on one main surface of the base material, and the other end of the through wiring is exposed on the other main surface of the base material. .
As shown in FIG. 4, for example, the through wiring 43 is composed of a combination of a plurality of straight portions and branch portions, and at least one straight portion extends in a direction different from the thickness direction of the base material 41 (up and down direction on the paper surface). An example is given.
4 (a) to 4 (b), the end portions 43α to 43δ of the through wiring 43 extending from the branch portion are exposed on one surface (upper surface of the paper surface) 41a and the other surface (lower surface of the paper surface) 41b, respectively. Although they are common, they have their respective features in the following points.
In the configuration example of FIG. 4A, straight portions 43a to 43c individually extend from one branch portion 44 to one surface 41a or the other surface 41b.
In the configuration example of FIG. 4B, the straight portions 43d to 43g individually extend from the two branch portions 44a and 44b to the one surface 41a or the other surface 41b.
In order to obtain the configuration example shown in FIG. 4, the fine holes 42 formed by combining a plurality of linear portions and branch portions so as to connect one main surface 41 a forming the base material 41 and the other main surface 41 b. And the through hole 43 may be formed by filling the fine holes 42 with a conductive substance.

また図5に示すように、例えば貫通配線53が直線部と屈曲部と分岐部の組み合わせからなり、少なくとも1つの直線部が基材51の厚み方向(紙面の上下方向)とは異なる方向に延びている例も挙げられる。図5(a)〜図5(c)は貫通配線53の一端または他端53α〜53δが基材の一面(紙面の上面)51a又は他面(紙面の下面)51bの何れかに露呈している状態は共通しているが、以下の点において各々特長を有する。
図5(a)の構成例では、5つの直線部53a〜53eが2つの屈曲部54b、54cと1つの分岐部54aで結合されており、分岐部54aと屈曲部54b、54cを繋ぐ直線部53b、53cのみ基材51の厚み方向(紙面の上下方向)とは異なる方向に延びている。
図5(b)の構成例では、基板の厚み方向に貫通する1つの直線部53fから分岐した複数の直線部53g、53hをもち、この2つの直線部は両方とも基材51の厚み方向(紙面の上下方向)とは異なる方向に延びている。また、一方の直線部53hは屈曲部を介して他の直線部53iに繋がっている。
図5(c)の構成例では、基板の厚み方向に貫通する1つの直線部53jから分岐した複数の直線部53k、53mをもち、この2つの直線部は両方とも基材51の厚み方向(紙面の上下方向)とは異なる方向に延びている。また、両方の直線部53k、53mはそれぞれ屈曲部54g、54jを介して他の直線部53l、53nに繋がっている。
As shown in FIG. 5, for example, the through wiring 53 includes a combination of a straight portion, a bent portion, and a branch portion, and at least one straight portion extends in a direction different from the thickness direction of the base material 51 (up and down direction on the paper surface). There are also examples. 5 (a) to 5 (c), one end or the other end 53α to 53δ of the through wiring 53 is exposed to either one surface (upper surface of the paper surface) 51a or the other surface (lower surface of the paper surface) 51b. Although they are common, they have their respective features in the following points.
In the configuration example of FIG. 5A, five straight portions 53a to 53e are connected by two bent portions 54b and 54c and one branch portion 54a, and a straight portion connecting the branch portion 54a and the bent portions 54b and 54c. Only 53b and 53c extend in a direction different from the thickness direction of the substrate 51 (up and down direction on the paper surface).
In the configuration example of FIG. 5B, a plurality of straight portions 53g and 53h branched from one straight portion 53f penetrating in the thickness direction of the substrate are included, and both of these two straight portions are in the thickness direction of the substrate 51 ( It extends in a direction different from the vertical direction). One straight line portion 53h is connected to another straight line portion 53i through a bent portion.
In the configuration example of FIG. 5C, a plurality of straight portions 53k and 53m branched from one straight portion 53j penetrating in the thickness direction of the substrate are included, and both of these two straight portions are in the thickness direction of the substrate 51 ( It extends in a direction different from the vertical direction). Further, both the straight portions 53k and 53m are connected to the other straight portions 53l and 53n through bent portions 54g and 54j, respectively.

さらに図6に示すように、例えば貫通配線53が直線部と屈曲部と分岐部の組み合わせからなり、少なくとも1つの直線部が基材61の厚み方向(紙面の上下方向)と垂直をなす方向に延びている例も挙げられる。図6(a)〜図6(c)は貫通配線63の一端または他端63α〜63δが基材を構成する3つ又は4つの面(紙面の上下面、左右面)61a〜61dの何れかに露呈している状態は共通しているが、以下の点において各々特長を有する。
図6(a)の構成例では、基板の厚み方向に貫通する1つの直線部63aから分岐した1つの直線部63bをもち、後者の直線部63bのみ基材61の厚み方向(紙面の上下方向)と垂直をなす方向に延びている。これにより、貫通配線63は基材の上下面と一つの側面に露呈された端部63α〜63γをもつ。
図6(b)の構成例では、基板の厚み方向と垂直をなす方向に貫通する1つの直線部63cから分岐した1つの直線部63dをもち、後者の直線部63dのみ基材51の厚み方向(紙面の上下方向)に延びている。これにより、貫通配線63は基材の上面と二つの側面に露呈された端部63α〜63γをもつ。
図6(c)の構成例では、基材61の一つの側面61dに露呈して、共通する一端63αを備えた、基板の厚み方向とは異なる方向に延びる3つの直線部63e、63f、63gをもつ。また、3つの直線部63e、63f、63gの他端はそれぞれ異なる面に露呈し、順に端部63γ、63β、63δをもつ。図6(c)では、分岐部64が共通する一端63αの近傍に位置する例を示したが、これに限定されるものではない。
Further, as shown in FIG. 6, for example, the through wiring 53 is composed of a combination of a straight portion, a bent portion, and a branch portion, and at least one straight portion is in a direction perpendicular to the thickness direction of the substrate 61 (up and down direction on the paper surface). An extended example is also given. 6 (a) to 6 (c) are any one of three or four surfaces (upper and lower surfaces, left and right surfaces) 61a to 61d of which one end or the other ends 63α to 63δ of the through wiring 63 constitute a base material. Although they are exposed in common, they have the following features.
In the configuration example of FIG. 6A, there is one straight line portion 63b branched from one straight line portion 63a penetrating in the thickness direction of the substrate, and only the latter straight line portion 63b is in the thickness direction of the base material 61 (the vertical direction of the paper surface). ) In a direction perpendicular to Accordingly, the through wiring 63 has end portions 63α to 63γ exposed on the upper and lower surfaces and one side surface of the base material.
In the configuration example of FIG. 6B, one straight portion 63d branched from one straight portion 63c penetrating in a direction perpendicular to the thickness direction of the substrate is provided, and only the latter straight portion 63d is in the thickness direction of the substrate 51. It extends in the vertical direction of the page. Accordingly, the through wiring 63 has end portions 63α to 63γ exposed on the upper surface and two side surfaces of the base material.
In the configuration example of FIG. 6C, three linear portions 63e, 63f, and 63g that are exposed to one side surface 61d of the base material 61 and that have a common end 63α and extend in a direction different from the thickness direction of the substrate. It has. The other ends of the three straight portions 63e, 63f, and 63g are exposed on different surfaces, respectively, and have end portions 63γ, 63β, and 63δ in order. Although FIG. 6C shows an example in which the branching portion 64 is located in the vicinity of the common end 63α, the present invention is not limited to this.

図4(図5、図6)に示した構成例とするためには、基材41(51、61)をなす一方の主面41a(51a、61a)、他方の主面41b(51b、61b)、及び/又は側面41c(51c、61c)を結ぶように、屈曲部や分岐部を介して直線部をなす微細孔42(52、62)を設け、この微細孔42(52、62)に導電性物質を充填し、貫通配線43(53、63)を形成すればよい。   In order to obtain the configuration example shown in FIG. 4 (FIGS. 5 and 6), one main surface 41a (51a, 61a) forming the base material 41 (51, 61) and the other main surface 41b (51b, 61b) are formed. ) And / or the side surfaces 41c (51c, 61c) are provided with fine holes 42 (52, 62) forming straight portions via bent portions or branch portions, and the fine holes 42 (52, 62) are provided in the fine holes 42 (52, 62). What is necessary is just to fill with an electroconductive substance and to form the penetration wiring 43 (53, 63).

なお、図1〜図6においては、一つの基材の中に一つの微細孔を設け、この微細孔に導電性物質を充填し、一つの貫通配線を形成した例を示した。
しかしながら、図7に示すように、一つの基材71の中に独立した複数の微細孔を設け、これらの微細孔に導電性物質を充填し、独立した複数の貫通配線73(73a〜73e)を形成しても構わない。図7には、基材の断面方向から見てパターンの異なる貫通配線を組合せた例を示したが、これに限定されず、一つの基材の中にパターンの同じ貫通配線を備えてもよい。特に、基材の側面近傍に配される貫通配線73a、73eは、その端部の一つが側面に露呈する形態を採用することが可能となる。
1 to 6 show an example in which one fine hole is provided in one base material, the fine hole is filled with a conductive material, and one through wiring is formed.
However, as shown in FIG. 7, a plurality of independent fine holes are provided in one base material 71, and these fine holes are filled with a conductive material, and a plurality of independent through wirings 73 (73a to 73e) are provided. May be formed. Although FIG. 7 shows an example in which through wirings having different patterns as viewed from the cross-sectional direction of the base material are combined, the present invention is not limited to this, and the same through wiring with the same pattern may be provided in one base material. . In particular, it is possible to adopt a form in which one of the end portions of the through wirings 73a and 73e disposed near the side surface of the base material is exposed on the side surface.

<第四の形態>
第四の形態は、図8に示すように、貫通配線の一端及び/又は他端は、接合する他の基板の電極に対応する位置に配されている構成である。
図8(a)、(b)は、図7と同様に、各々の基材81A、81Bの中に独立した複数の微細孔を設け、これらの微細孔に導電性物質を充填し、独立した複数の貫通配線(例えば、83A、83B)を形成したものである。2つの基材81A、81Bは、両者を接合する面81Ab、81Baにおいて、接合する相手方の基板の電極と位置が一致するように構成されている。
図8(c)は2つの基材81A、81Bを接合した状態を示しており、例えば、基材81Aに設けた貫通配線83Aの他端83Aβと、基材81Bに設けた貫通配線83Bの一端83Bαとが位置を一致させると、両者の基板に設けた他の端部同士も同様に位置が一致し、電気的な導通が可能となるように配されている状態を表している。
このような配置の採用は、2つの基材を重ね合わせる場合に限定されるものではなく、3つ以上の基材を重ねて接合した形態(以下、複合基板とも呼ぶ)にも適用できる。
<Fourth form>
In the fourth embodiment, as shown in FIG. 8, one end and / or the other end of the through wiring is arranged at a position corresponding to the electrode of another substrate to be joined.
8 (a) and 8 (b), as in FIG. 7, a plurality of independent micropores are provided in each of the base materials 81A and 81B, and these micropores are filled with a conductive substance and independent. A plurality of through wirings (for example, 83A and 83B) are formed. The two base materials 81A and 81B are configured such that the positions of the electrodes 81Ab and 81Ba that join the base materials coincide with the electrodes of the mating substrate to be joined.
FIG. 8C shows a state in which the two base materials 81A and 81B are joined. For example, the other end 83Aβ of the through wiring 83A provided in the base material 81A and one end of the through wiring 83B provided in the base material 81B. When the positions of 83Bα coincide with each other, the other end portions provided on both the substrates also coincide with each other in the same manner, indicating a state in which electrical conduction is possible.
Adoption of such an arrangement is not limited to the case where two base materials are overlapped, but can also be applied to a form in which three or more base materials are overlapped and joined (hereinafter also referred to as a composite substrate).

また図9は、基材91の一面91Aに機能素子95を埋設してなる点のみ図7の基材71と異なっている。図9に示すように、基材91はその内部に貫通配線93とは直接には電気的に接続されないように、機能素子95を配する形態(以下、機能素子を内包する複合基板とも呼ぶ)としてもよい。このような形態に好適な機能素子(以下、単にデバイスとも呼ぶ)95としては、例えば、コンデンサや抵抗などの受動素子、あるいは各種センサなどのMEMSデバイスが挙げられる。   9 differs from the base material 71 of FIG. 7 only in that the functional element 95 is embedded in one surface 91A of the base material 91. FIG. As shown in FIG. 9, the base material 91 has a configuration in which a functional element 95 is arranged so as not to be directly electrically connected to the through wiring 93 (hereinafter also referred to as a composite substrate containing the functional element). It is good. Examples of a functional element (hereinafter also simply referred to as a device) 95 suitable for such a configuration include passive elements such as capacitors and resistors, or MEMS devices such as various sensors.

図10は、図8と同様に、機能素子105を備えた基材101Bを一方の基板として用い、この基材に設けた貫通配線の一端及び/又は他端が、接合する他の基板(基材101A)の電極に対応する位置に配されている構成である。図10(a)は他方の基板、図10(b)は一方の基板であり、図10(c)は2つの基材101A、101Bを接合した状態を示している。この構成によれば、両者の基板に設けた端部同士の位置がそれぞれ一致し、電気的な導通が可能になるとともに、機能素子105が2つの基材101A、101B間に挟み込まれ、あるいは密閉された形態とすることができるので、外力に対して耐久性に優れた構成が得られる。また、機能素子105が外部環境に曝される虞がないので、耐環境性の改善も図れる。   In FIG. 10, similarly to FIG. 8, the base material 101B including the functional element 105 is used as one substrate, and one end and / or the other end of the through wiring provided in the base material is joined to another substrate (base The material 101A) is arranged at a position corresponding to the electrode. FIG. 10A shows the other substrate, FIG. 10B shows the one substrate, and FIG. 10C shows a state where the two base materials 101A and 101B are joined. According to this configuration, the positions of the end portions provided on both the substrates match each other and electrical conduction is possible, and the functional element 105 is sandwiched between the two base materials 101A and 101B or sealed. Therefore, a configuration having excellent durability against external force can be obtained. Further, since there is no possibility that the functional element 105 is exposed to the external environment, the environmental resistance can be improved.

本発明に係る貫通配線基板は、上述したように、基板内部で三次元的に自由な配線を可能とする貫通電極を基本構造としている。以下ではまず、上述した各種構成からなる貫通配線基板の製造方法について、図11〜図14に基づき、貫通配線基板が単板からなる場合を例として詳細に述べる。次いで、いくつかの具体的な態様を実施例1〜3として説明する。   As described above, the through wiring substrate according to the present invention has a basic structure of a through electrode that enables three-dimensional free wiring inside the substrate. Below, the manufacturing method of the penetration wiring board which consists of various structures mentioned above is described in detail based on the case where a penetration wiring board consists of a single board based on FIGS. 11-14. Next, some specific modes will be described as Examples 1 to 3.

図11〜図14は、本発明に係る貫通配線基板の作製方法を工程順に示した模式的な断面図である。本実施形態では、基材として厚さが500μmのガラス(石英)基板を用いた。また本実施形態における微細孔の作製方法は、レーザーを用いて石英基板の一部を改質した後、改質した部分をエッチングにより除去するものである。   11 to 14 are schematic cross-sectional views showing a method of manufacturing a through wiring board according to the present invention in the order of steps. In the present embodiment, a glass (quartz) substrate having a thickness of 500 μm is used as the base material. In addition, the method for producing a microscopic hole in the present embodiment is to modify a part of a quartz substrate using a laser and then remove the modified part by etching.

まず、図11に示すように、石英からなる基板111の少なくとも微細孔を形成したい箇所にレーザー光118を照射して基板111内に改質部114を形成する。本実施形態においてはレーザー光118の光源としてフェムト秒レーザーを用い、基板111内部に焦点113を結ぶようにレーザービームを照射し、例えば径が数μm〜数十μmとした改質部114を得る。その際、焦点113と基板位置とを制御することにより、図12に例示するように様々な形状の改質部114を形成することができる。なお、微細孔を形成する基板111は、石英基板に限定されるものではなく、例えばサファイア等の絶縁基板や、アルカリ成分等を含んだ他の他成分ガラス基板を用いることができ、その厚さも150μm〜1mm程度まで適宜設定できる。   First, as shown in FIG. 11, a laser beam 118 is irradiated to at least a portion of the substrate 111 made of quartz where a fine hole is to be formed, thereby forming a modified portion 114 in the substrate 111. In the present embodiment, a femtosecond laser is used as a light source of the laser beam 118, and a laser beam is irradiated so as to form a focal point 113 inside the substrate 111, thereby obtaining a modified portion 114 having a diameter of several μm to several tens of μm, for example. . At that time, by controlling the focal point 113 and the substrate position, the modified portions 114 having various shapes can be formed as illustrated in FIG. The substrate 111 for forming the fine holes is not limited to a quartz substrate, and for example, an insulating substrate such as sapphire or another component glass substrate containing an alkali component or the like can be used, and its thickness is also It can set suitably to about 150 micrometers-1 mm.

次いで、図13に示すように、容器116内に入れた所定の薬液115中に、改質部を形成した基板111を浸漬する。これにより、改質部は薬液115によりウェットエッチングされ、基板111内から除去される。その結果、改質部が存在した部分に、微細孔112が形成される。本実施形態では、薬液115としてフッ酸を主成分とする酸溶液を用いた。
本エッチングは、改質部114が改質されていない部分に比べて非常に早くエッチングされる現象を利用するものであり、結果として改質部114に起因した形状の微細孔112を形成することができる。本実施形態においては、微細孔112の孔径は50μmとした。なお、薬液115はフッ酸に限定されず、例えばフッ酸に硝酸等を適量添加したフッ硝酸系の混酸等を用いることができる。また、微細孔112の孔径も、貫通電極の用途に応じて10μm程度から300μm程度まで適宜設定することができる。さらに、形成する微細孔も、基板を貫通するもの、非貫通のもののどちらでも良い。
Next, as shown in FIG. 13, the substrate 111 on which the modified portion is formed is immersed in a predetermined chemical solution 115 placed in the container 116. Thereby, the modified portion is wet-etched with the chemical solution 115 and removed from the substrate 111. As a result, the fine hole 112 is formed in the portion where the modified portion is present. In the present embodiment, an acid solution containing hydrofluoric acid as a main component is used as the chemical solution 115.
This etching utilizes the phenomenon that the modified portion 114 is etched much faster than the portion where the modified portion 114 is not modified, and as a result, the fine hole 112 having a shape caused by the modified portion 114 is formed. Can do. In the present embodiment, the hole diameter of the fine hole 112 is 50 μm. Note that the chemical solution 115 is not limited to hydrofluoric acid, and for example, a hydrofluoric acid-based mixed acid obtained by adding an appropriate amount of nitric acid or the like to hydrofluoric acid can be used. Moreover, the hole diameter of the fine hole 112 can be appropriately set from about 10 μm to about 300 μm depending on the use of the through electrode. Furthermore, the fine holes to be formed may be either those that penetrate the substrate or those that do not penetrate.

上述した方法により、石英からなる基板の内部に三次元的に自由な構造を持つ微細孔を形成することができる。以下、いくつかの貫通電極の態様に応じた作製方法を説明する。   By the above-described method, a fine hole having a three-dimensional free structure can be formed inside a quartz substrate. Hereinafter, a manufacturing method according to some embodiments of the through electrode will be described.

(実施例1)・・・単板での実施
本例では、一枚の基板に貫通配線を配してなる貫通配線基板の作製方法について、図14に基づき詳述する。
まず、図14(a)に示すように、石英からなる基板141に前述した微細孔の形成方法により様々な形態をもつ微細孔142を形成する。ここで、基板141は厚さが500μmであり、微細孔142の孔径は50μmとした。なお、基板の厚さは孔径がこれに限定されないことは上述の通りである。
次いで、図14(b)に示すように、微細孔142の内部に導電性物質143を充填する。本例では、導電性物質143として金錫(Au−Sn)を用い、溶融金属充填法により微細孔内部に充填した。溶融金属充填法は、圧力差を用いて微細孔内部にも気密性よく短時間で充填できる方法である。なお、本例においては、充填金属として金錫(Au−Sn)を用いたが、本発明はこれに限定されず、異なる組成を有する金錫合金や、錫(Sn)、インジウム(In)等の金属、また錫鉛(Sn−Pb)系、錫(Sn)基、鉛(Pb)基。金(Au)基、インジウム(In)基、アルミニウム(Al)基等のはんだを使用することができる。また、充填方法も溶融金属吸引法を用いたが、本発明はこれに限定されず、めっき法による金属充填や印刷法による導電性ペーストの充填、またCVD等によるカーボンナノチューブの充填を利用することができる。
以上の方法により、三次元的に自由な貫通電極を有する貫通配線基板を提供することができる。
なお、本例においては、微細孔142は基板の主面あるいは側面を貫通するものであったが、本発明はこれに限定されず、微細孔は非貫通で形成しておき、金属充填後、基板を研磨することにより貫通電極を形成することも可能である。
(Embodiment 1)... Implementation with a single plate In this example, a method for manufacturing a through wiring substrate in which through wiring is arranged on a single substrate will be described in detail with reference to FIG.
First, as shown in FIG. 14A, fine holes 142 having various forms are formed in a substrate 141 made of quartz by the fine hole forming method described above. Here, the substrate 141 has a thickness of 500 μm, and the hole diameter of the fine holes 142 is 50 μm. As described above, the thickness of the substrate is not limited to the hole diameter.
Next, as shown in FIG. 14B, the conductive material 143 is filled into the micro holes 142. In this example, gold tin (Au—Sn) was used as the conductive material 143, and the inside of the fine holes was filled by a molten metal filling method. The molten metal filling method is a method in which the inside of a fine hole can be filled with good airtightness in a short time using a pressure difference. In this example, gold tin (Au—Sn) is used as the filling metal. However, the present invention is not limited to this, and gold tin alloys having different compositions, tin (Sn), indium (In), etc. Metals, tin-lead (Sn-Pb), tin (Sn) group, lead (Pb) group. A solder such as a gold (Au) group, an indium (In) group, or an aluminum (Al) group can be used. Also, although the molten metal suction method is used as the filling method, the present invention is not limited to this, and metal filling by plating method, filling of conductive paste by printing method, and filling of carbon nanotubes by CVD or the like can be used. Can do.
By the above method, a through wiring substrate having a three-dimensional free through electrode can be provided.
In this example, the fine hole 142 penetrates the main surface or side surface of the substrate. However, the present invention is not limited to this, and the fine hole is formed non-through, and after filling the metal, It is also possible to form the through electrode by polishing the substrate.

(実施例2)・・・複合基板の実施例
本例では、複数の貫通配線基板を積み重ねてなる複合基板の作製方法について、図15に基づき詳述する。ここでは、三通りの製法について例示する。
第一の製法(図15)は、実施例1において説明した方法により作製した貫通配線基板同士を積み重ねるものである。まず、図15(a)に示すように、既に貫通電極153(153a、153b)が形成された貫通配線基板151Aと151Bを対向させ、貫通電極153a、153bの端部同士の位置を合わせるようにアライメントを行う。その後、図15(b)に示すように、2つの貫通配線基板151A、151Bを積み重ねた。本例では、異方性導電接着剤157を用いて基板間を接着したが、これに限定されるものではなく、例えばはんだバンプを用いた接合など他の方法を用いてもよい。
第二の製法(図16)は、まず、図16(a)に示すように、微細孔162a、162bのみが形成された基板161A、161Bを、絶縁樹脂163を介して接合する。この際、微細孔162aと162bが重なる位置にある樹脂は、予め(貼り合わせ前に)除去しておいても良いし、貼り合わせ後にエッチング等により除去しても良い。次いで、図16(b)に示すように、接合後に形成された微細孔162a、162b、162cに一度に金属充填し、貫通電極を作製するものである。本例では、絶縁樹脂163を用いて両基板を接着したが、これに限定されるものではなく、例えば陽極接合など他の方法を用いてもよい。
第三の製法(図17)は、まず、図17(a)に示すように、基板171Aと171Bを用意し、低融点ガラス177を用いて接合した状態とする。次いで、接合後の基板に微細孔172を形成する。その後、微細孔172の内部に金属充填するものである。本例では、低融点ガラス177を用いて両基板を接着したが、これに限定されるものではなく、例えば陽極接合など他の方法を用いてもよい。
以上の方法により、三次元的に自由な貫通電極を有する貫通配線基板を積層することができる。
Example 2 Example of Composite Substrate In this example, a method for manufacturing a composite substrate in which a plurality of through wiring substrates are stacked will be described in detail with reference to FIG. Here, three types of manufacturing methods are illustrated.
The first manufacturing method (FIG. 15) is a method of stacking through wiring substrates produced by the method described in the first embodiment. First, as shown in FIG. 15A, the through wiring boards 151A and 151B on which the through electrodes 153 (153a and 153b) are already formed are opposed to each other, and the positions of the end portions of the through electrodes 153a and 153b are aligned. Align. Then, as shown in FIG.15 (b), two penetration wiring boards 151A and 151B were stacked. In this example, the substrates are bonded using the anisotropic conductive adhesive 157. However, the present invention is not limited to this, and other methods such as bonding using solder bumps may be used.
In the second manufacturing method (FIG. 16), first, as shown in FIG. 16A, substrates 161A and 161B in which only micro holes 162a and 162b are formed are joined via an insulating resin 163. At this time, the resin at the position where the micro holes 162a and 162b overlap may be removed in advance (before bonding), or may be removed by etching or the like after bonding. Next, as shown in FIG. 16 (b), the fine holes 162a, 162b, and 162c formed after the bonding are filled with metal at a time to produce a through electrode. In this example, both substrates are bonded using the insulating resin 163. However, the present invention is not limited to this, and other methods such as anodic bonding may be used.
In the third manufacturing method (FIG. 17), first, as shown in FIG. 17A, substrates 171A and 171B are prepared and bonded using a low-melting glass 177. Next, fine holes 172 are formed in the bonded substrates. Thereafter, the fine holes 172 are filled with metal. In this example, the low melting point glass 177 is used to bond both substrates, but the present invention is not limited to this, and other methods such as anodic bonding may be used.
By the above method, a through wiring substrate having a three-dimensional free through electrode can be laminated.

(実施例3)・・・パッケージへの応用例
実施例1、及び実施例2において説明した貫通電極及びそれを用いた貫通配線基板を適宜使用することにより、図18に示すように複数のデバイス(電子部品)185A〜185Dを三次元的に複合実装した機能キューブ(電子装置)を実現することができる。
なお、図18において、181A〜181Dは基板であり、特に複合実装した際、181Aは2つのデバイス185A、185Bを外面に、181Bはデバイス185Dを内面に、181Cはデバイス185Cを内面に、それぞれ載置している。
(Example 3) ... Application example to package By appropriately using the through electrode described in Example 1 and Example 2 and the through wiring substrate using the through electrode, a plurality of devices as shown in FIG. (Electronic component) A functional cube (electronic device) in which 185A to 185D are three-dimensionally combined and mounted can be realized.
In FIG. 18, reference numerals 181A to 181D denote substrates. In particular, when composite mounting is performed, 181A has two devices 185A and 185B on the outer surface, 181B has device 185D on the inner surface, and 181C has device 185C on the inner surface. It is location.

本発明によれば、基板内部を三次元的に自由に配線し、基板の表裏のみならず側面にも電気的な配線がなされるため、これまでの貫通配線と比べて、より設計の自由度が高く、高密度実装が可能となる。
また、本発明の貫通配線基板を提供することにより、三次元実装やSiPにおいて、より高機能、高密度なパッケージを実現することができ、ひいてはデバイスの高速化、高機能化に貢献する。
According to the present invention, the interior of the substrate is freely wired three-dimensionally, and electrical wiring is made not only on the front and back sides of the substrate, but also on the side surfaces. And high-density mounting is possible.
In addition, by providing the through wiring board of the present invention, it is possible to realize a package with higher functionality and higher density in three-dimensional mounting and SiP, thereby contributing to higher speed and higher functionality of the device.

本発明に係る貫通配線基板の一例を示す断面図である。It is sectional drawing which shows an example of the penetration wiring board which concerns on this invention. 本発明に係る貫通配線基板の他の一例を示す断面図である。It is sectional drawing which shows another example of the penetration wiring board which concerns on this invention. 本発明に係る貫通配線基板の他の一例を示す断面図である。It is sectional drawing which shows another example of the penetration wiring board which concerns on this invention. 本発明に係る貫通配線基板の他の一例を示す断面図である。It is sectional drawing which shows another example of the penetration wiring board which concerns on this invention. 本発明に係る貫通配線基板の他の一例を示す断面図である。It is sectional drawing which shows another example of the penetration wiring board which concerns on this invention. 本発明に係る貫通配線基板の他の一例を示す断面図である。It is sectional drawing which shows another example of the penetration wiring board which concerns on this invention. 本発明に係る貫通配線基板の他の一例を示す断面図である。It is sectional drawing which shows another example of the penetration wiring board which concerns on this invention. 本発明に係る貫通配線基板の他の一例を示す断面図である。It is sectional drawing which shows another example of the penetration wiring board which concerns on this invention. 本発明に係る貫通配線基板の他の一例を示す断面図である。It is sectional drawing which shows another example of the penetration wiring board which concerns on this invention. 本発明に係る貫通配線基板の他の一例を示す断面図である。It is sectional drawing which shows another example of the penetration wiring board which concerns on this invention. 本発明に係る貫通配線基板の作製方法の工程を示す断面図である。It is sectional drawing which shows the process of the manufacturing method of the penetration wiring board which concerns on this invention. 図11の次工程を示す断面図である。FIG. 12 is a cross-sectional view showing a next step of FIG. 11. 図12の次工程を示す断面図である。It is sectional drawing which shows the next process of FIG. 図13の次工程を示す断面図である。It is sectional drawing which shows the next process of FIG. 本発明に係る複合基板の一例における作製方法を示す断面図である。It is sectional drawing which shows the preparation methods in an example of the composite substrate which concerns on this invention. 本発明に係る複合基板の他の一例における作製方法を示す断面図である。It is sectional drawing which shows the preparation methods in another example of the composite substrate which concerns on this invention. 本発明に係る複合基板の他の一例における作製方法を示す断面図である。It is sectional drawing which shows the preparation methods in another example of the composite substrate which concerns on this invention. 本発明に係る電子装置の一例における作製方法を示す断面図である。It is sectional drawing which shows the preparation methods in an example of the electronic device which concerns on this invention. 従来の貫通配線基板の一例を示す断面図である。It is sectional drawing which shows an example of the conventional penetration wiring board.

符号の説明Explanation of symbols

10、20、30、40、50、60、70 貫通配線基板、
11、21、31、41、51、61、71 基材、
12、22、32、42、52、62、72 微細孔、
13、23、33、43、53、63、73 貫通配線、
81A、81B 基材、83A、83B 貫通配線、
91 基材、93 貫通配線、95 機能素子、
101A、101B 基材、105 機能素子、
111 基板、112 微細孔、113 焦点、114 改質部、115 薬液、116 容器、118 レーザー光、
141 基板、142 微細孔、143 導電性物質、
151A、151B 貫通配線基板、153a、153b 貫通電極、157 異方性導電接着剤、
161A、161B 基板、162a、162b 微細孔、163 絶縁樹脂、
171A、171B 基板、172 微細孔、177 低融点ガラス、
181A〜181D 基板、185A〜185D デバイス(電子部品)。
10, 20, 30, 40, 50, 60, 70 Penetration wiring board,
11, 21, 31, 41, 51, 61, 71 base material,
12, 22, 32, 42, 52, 62, 72
13, 23, 33, 43, 53, 63, 73 Through wiring,
81A, 81B base material, 83A, 83B through wiring,
91 base material, 93 through wiring, 95 functional elements,
101A, 101B base material, 105 functional elements,
111 substrate, 112 fine hole, 113 focal point, 114 modifying part, 115 chemical solution, 116 container, 118 laser beam,
141 substrate, 142 micropores, 143 conductive material,
151A, 151B through wiring board, 153a, 153b through electrode, 157 anisotropic conductive adhesive,
161A, 161B substrate, 162a, 162b micropore, 163 insulating resin,
171A, 171B substrates, 172 micropores, 177 low melting glass,
181A to 181D substrate, 185A to 185D device (electronic component).

Claims (7)

基材を構成する少なくとも二面を結ぶように微細孔を配し、該微細孔に導電性物質を充填してなる貫通配線を備えた貫通配線基板であって、
前記貫通配線は、少なくとも一部に、前記基材の厚み方向とは異なる方向に延びる部分を有することを特徴とする貫通配線基板。
A through-wiring board provided with a through-hole formed by arranging a fine hole so as to connect at least two surfaces constituting a base material, and filling the fine hole with a conductive substance,
The penetration wiring board, wherein the penetration wiring has at least a portion extending in a direction different from a thickness direction of the base material.
前記貫通配線の一端は前記基材の主面に、前記貫通配線の他端は前記基材の側面に、それぞれ露呈されてなることを特徴とする請求項1に記載の貫通配線基板。   2. The through wiring board according to claim 1, wherein one end of the through wiring is exposed on a main surface of the base material, and the other end of the through wiring is exposed on a side surface of the base material. 前記貫通配線の一端は前記基材の一方の主面に、前記貫通配線の他端は前記基材の他方の主面に、それぞれ露呈されてなることを特徴とする請求項1に記載の貫通配線基板。   2. The penetration according to claim 1, wherein one end of the through wiring is exposed on one main surface of the base material, and the other end of the through wiring is exposed on the other main surface of the base material. Wiring board. 前記貫通配線は、前記基材内に分岐する部分を備えていることを特徴とする請求項1に記載の貫通配線基板。   The through wiring board according to claim 1, wherein the through wiring includes a portion branched into the base material. 前記貫通配線の一端及び/又は他端は、接合する他の基板の電極に対応する位置に配されていることを特徴とする請求項1に記載の貫通配線基板。   2. The through wiring substrate according to claim 1, wherein one end and / or the other end of the through wiring is arranged at a position corresponding to an electrode of another substrate to be joined. 請求項1乃至5のいずれか1項に記載の貫通配線基板を複数用い、互いの主面同士及び/又は側面同士を重ね合わせ、互いの貫通配線基板を構成する貫通配線を電気的に接続してなることを特徴とする複合基板。   A plurality of through wiring boards according to any one of claims 1 to 5, wherein the main surfaces and / or side surfaces of the through wiring boards are overlapped to electrically connect the through wirings constituting each through wiring board. A composite substrate characterized by comprising 請求項1乃至5のいずれか1項に記載の貫通配線基板又は請求項6に記載の複合基板に電子部品を実装してなることを特徴とする電子装置。
An electronic device comprising an electronic component mounted on the through wiring substrate according to claim 1 or the composite substrate according to claim 6.
JP2005126244A 2005-04-25 2005-04-25 Through-wire board, composite board, and electronic apparatus Pending JP2006303360A (en)

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Cited By (33)

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JP2008203336A (en) * 2007-02-16 2008-09-04 Fujikura Ltd Opto-electric composite substrate, manufacturing method thereof and electronic equipment
JP2008288577A (en) * 2007-04-18 2008-11-27 Fujikura Ltd Substrate treatment method, through-wire substrate and its manufacturing method, and electronic component
JP2009064840A (en) * 2007-09-04 2009-03-26 Sanyo Electric Co Ltd Solar cell
JP2009088474A (en) * 2007-09-28 2009-04-23 Samsung Electro-Mechanics Co Ltd Inter layer conduction method for printed circuit board
EP2058855A2 (en) 2007-11-09 2009-05-13 Fujikura, Ltd. Method of manufacturing semiconductor package
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WO2010119652A1 (en) 2009-04-14 2010-10-21 株式会社フジクラ Electronic device mounting structure and electronic device mounting method
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Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5994441A (en) * 1982-11-19 1984-05-31 Nippon Denso Co Ltd Semiconductor device
JPH05259599A (en) * 1992-03-13 1993-10-08 Matsushita Electric Works Ltd Printed wiring board
JP2000216514A (en) * 1999-01-27 2000-08-04 Matsushita Electric Ind Co Ltd Wiring board and its manufacture
JP2001203457A (en) * 2000-01-18 2001-07-27 Ibiden Co Ltd Interlayer connection structure for laminated wiring board
JP2002210730A (en) * 2001-01-19 2002-07-30 Tokyo Instruments Inc Method for laser-aid working
JP2003020257A (en) * 2001-07-04 2003-01-24 Hitachi Ltd Wiring board, semiconductor device and method for manufacturing these
JP2003197811A (en) * 2001-12-27 2003-07-11 Hitachi Ltd Glass substrate, manufacturing method thereof, wiring base board and semiconductor module
JP2004160618A (en) * 2002-11-15 2004-06-10 Seiko Epson Corp Micro machine and method for manufacturing the same
JP2004311720A (en) * 2003-04-07 2004-11-04 Fujikura Ltd Multilayer wiring board, base material therefor and its manufacturing method
JP2004363212A (en) * 2003-06-03 2004-12-24 Hitachi Metals Ltd Wiring board with through-hole conductor
JP2005019576A (en) * 2003-06-25 2005-01-20 Hitachi Metals Ltd Wiring board having through hole conductor

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5994441A (en) * 1982-11-19 1984-05-31 Nippon Denso Co Ltd Semiconductor device
JPH05259599A (en) * 1992-03-13 1993-10-08 Matsushita Electric Works Ltd Printed wiring board
JP2000216514A (en) * 1999-01-27 2000-08-04 Matsushita Electric Ind Co Ltd Wiring board and its manufacture
JP2001203457A (en) * 2000-01-18 2001-07-27 Ibiden Co Ltd Interlayer connection structure for laminated wiring board
JP2002210730A (en) * 2001-01-19 2002-07-30 Tokyo Instruments Inc Method for laser-aid working
JP2003020257A (en) * 2001-07-04 2003-01-24 Hitachi Ltd Wiring board, semiconductor device and method for manufacturing these
JP2003197811A (en) * 2001-12-27 2003-07-11 Hitachi Ltd Glass substrate, manufacturing method thereof, wiring base board and semiconductor module
JP2004160618A (en) * 2002-11-15 2004-06-10 Seiko Epson Corp Micro machine and method for manufacturing the same
JP2004311720A (en) * 2003-04-07 2004-11-04 Fujikura Ltd Multilayer wiring board, base material therefor and its manufacturing method
JP2004363212A (en) * 2003-06-03 2004-12-24 Hitachi Metals Ltd Wiring board with through-hole conductor
JP2005019576A (en) * 2003-06-25 2005-01-20 Hitachi Metals Ltd Wiring board having through hole conductor

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* Cited by examiner, † Cited by third party
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