JP2006302966A - Wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily recognize the size of a bubble 13 generated between an integrated circuit chip (IC) 1 and a film substrate 4. <P>SOLUTION: A wiring substrate 20 has at least the film substrate 4 and a first wiring pattern 30 formed on one surface of the film substrate 4. A connection terminal 32 is formed on the end of the first wiring pattern 30, and the bump 2 of the IC 1 is connected to the connection terminal 32, thereby mounting the IC 1 on the wiring substrate 20. The wiring substrate 20 has a bubble measurement pattern formed on the other surface of the film substrate 4 and formed in a mounting region of the IC 1. The bubble measurement pattern consists of a film 6 having a plurality of openings 8 arranged in matrix. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to wiring in which various integrated circuit chips (hereinafter also referred to as “IC”), for example, bare chips such as drivers, memories, controllers, and graphics, are face-down mounted on an insulating substrate such as a film substrate having a wiring pattern. Regarding the substrate.

  In recent years, with the miniaturization and multi-functionalization of electronic devices such as mobile phone type, high-density mounting of ICs is rapidly progressing, and a wiring board having wiring patterns formed on both sides of a film substrate in order to increase the mounting density Is adopted. For example, Patent Document 1 discloses a wiring board in which wiring patterns are formed on both surfaces of a film substrate.

  FIG. 7 is a schematic bottom view of a wiring board described in Patent Document 1, and FIG. 8 is a schematic cross-sectional view thereof. A wiring substrate 100 described in Patent Document 1 includes a film substrate 4, and a front surface wiring pattern 30 and a back surface wiring pattern 31 formed on both surfaces of the film substrate 4, respectively. Connection terminals 32 connected to the bumps 2 of the IC 1 are formed at the ends of the surface wiring pattern 30. A resist 5 is printed so as to cover the surface wiring pattern 30 except for a region where the IC 1 is mounted, and the surface wiring pattern 30 is protected by the resist 5. Similarly, a resist 7 is printed on the entire back surface of the film substrate 4, and the back surface wiring pattern 31 is protected by the resist 7.

  In the wiring substrate 100 described in Patent Document 1, in order to reduce the connection failure by keeping the thickness of the wiring substrate in the IC connection portion constant, the entire surface including the entire area where the IC 1 is mounted on the back surface of the film substrate 4. A dummy pattern 16 is formed. Further, by injecting and curing the underfill resin 14 between the IC 1 and the film substrate 4, the electrical connection between the bumps 2 of the IC 1 and the connection terminals 32 is maintained.

  On the other hand, as face-down mounting methods of ICs on a film substrate, connection using an anisotropic conductive film (ACF) and Au—Sn metal eutectic bonding are mainly used. When mounting an IC using an ACF, the ACF is temporarily attached to the film substrate or the IC, the IC and the film substrate are aligned, and both are pressurized. At this time, moisture or gas may enter between the film substrate and the ACF. Also, in Au—Sn metal eutectic bonding, gas may be involved when an underfill resin is injected between the IC and the film substrate. At the time of thermocompression bonding or in the reflow heating process, moisture and gas between the IC and the film substrate are thermally expanded to form bubbles. When the size of the generated bubbles exceeds a certain size, the connection reliability between the IC and the film substrate is hindered. Therefore, it is important to confirm the size of the generated bubbles after the thermocompression bonding or reflow heating process.

However, in the wiring substrate 100 described in Patent Document 1, since the dummy pattern 16 is formed on the entire surface including the entire area where the IC 1 is mounted, it cannot be visually confirmed from the back side of the wiring substrate. X-ray inspection is required. In addition, even if no dummy pattern or wiring pattern is formed on the back surface of the film substrate, in order to check whether the generated bubbles are of a size that hinders the connection reliability between the IC and the film substrate, Template determination is required. Furthermore, X-ray inspection, measuring instruments, and template determination are factors that increase manufacturing costs such as difficulty in confirmation and complicated processes.
Japanese Patent No. 3026205

  An object of the present invention is to easily confirm the size of bubbles generated between an IC and a film substrate.

  The present invention solves the above problem by providing a wiring board on which a bubble measurement pattern is formed in the mounting area of an integrated circuit chip (IC) on the back surface of an insulating substrate. More specifically, the wiring board of the present invention has at least an insulating substrate and a first wiring pattern formed on one surface of the insulating substrate, and is formed at an end of the first wiring pattern. A wiring board on which the IC is mounted by connecting the bumps of the IC to the connection terminals, which is formed on the other surface of the insulating substrate and is formed in the mounting area of the IC. Has a pattern.

  The bubble measurement pattern has a pattern for determining whether or not the size of the bubble is greater than or equal to the size that hinders connection reliability. Thereby, by observing from the back surface side of the wiring board, the size of the bubble generated between the IC and the wiring board can be visually confirmed by the bubble measurement pattern. Therefore, if the observer determines that the size of the bubble is greater than or equal to the size that hinders connection reliability, the wiring board can be removed from the production line. That is, since an abnormality can be found before the electrical connection inspection is performed, the outflow to the next process can be prevented. In addition, it is possible to quickly feed back pressure and heat treatment condition settings when connecting the bump and the connection terminal.

  The wiring board of the present invention includes a configuration in which the wiring pattern is formed not only on one surface of the insulating substrate but also on both surfaces of the insulating substrate. That is, the wiring board of the present invention may further include a second wiring pattern formed on the other surface of the insulating substrate. The second wiring pattern is preferably formed in a region other than the mounting region of the IC. Since the second wiring pattern is formed in an area other than the IC mounting area, in other words, the second wiring pattern is not formed in the IC mounting area, the thickness of the wiring board in the IC mounting area is reduced. Since it can be made constant, poor connection between the bumps of the IC and the connection terminals can be reduced.

  According to the present invention, the size of bubbles generated between the IC and the film substrate can be easily confirmed.

  Hereinafter, embodiments of an electronic circuit element and a display device using the wiring board of the present invention will be described with reference to the drawings. In the following embodiments, a liquid crystal display device will be described as an example of a display device. However, the wiring board of the present invention is not limited to a liquid crystal display device, but various display devices such as an organic or inorganic electroluminescence display device, plasma. The present invention can be applied to various display devices such as display panels, vacuum fluorescent display devices, and electronic paper.

  FIG. 1 is a plan view schematically showing a liquid crystal display device according to an embodiment. The liquid crystal display device includes a liquid crystal panel P and a flexible printed wiring board FPC connected to an end of the liquid crystal panel P. The flexible printed wiring board FPC has a liquid crystal driving IC chip (hereinafter referred to as “driving IC”) 1 that is bare-chip mounted on the wiring substrate 20 by a COF (Chip On Film) method.

  The liquid crystal panel P includes an element substrate on which a switching element is formed, a counter substrate disposed to face the element substrate, and a liquid crystal layer interposed between the two substrates. Electrodes are formed on the surfaces of both substrates on the liquid crystal layer side. A plurality of pixel electrodes arranged in a matrix are formed on the surface of the element substrate, and a common electrode is formed on the surface of the counter substrate. The plurality of pixel electrodes arranged in a matrix are connected to TFTs (Thin Film Transistors) that control voltage application. The TFT is connected to a source wiring or a gate wiring connected to the driving IC 1. Switching of TFTs is controlled by a gate signal from the driving IC 1 and voltage application to a plurality of pixel electrodes arranged in a matrix is controlled. Thereby, the transmittance of the liquid crystal layer is controlled for each pixel, and gradation display is performed.

  A flexible printed wiring board FPC as an electronic circuit element according to the present embodiment has a structure in which a driving IC 1 is mounted face-down on a wiring board 20. FIG. 2 is a schematic bottom view of the wiring substrate 20 in the mounting area of the driving IC 1 and the vicinity thereof, and FIG. 3 is a schematic cross-sectional view of the wiring board 20 in the mounting area of the driving IC 1 and the vicinity thereof.

  The wiring substrate 20 includes an insulating film substrate 4 and wiring patterns 30 and 31 formed on both surfaces of the film substrate 4 and made of Cu or the like. The film substrate 4 is mainly made of polyimide. The driving IC 1 has a protruding bonding bump electrode (hereinafter referred to as “bump”) 2 made of Au. A wiring pattern (hereinafter referred to as “first wiring pattern”) 30 connected to a control substrate (not shown) and the liquid crystal panel P is formed on the surface (front surface) of the film substrate 4 on the side where the driving IC 1 is mounted. Has been. A connection terminal (Sn plated terminal) 32 that is connected to the bump 2 of the drive IC 1 and is subjected to Sn plating is formed at the end of the first wiring pattern 30 in the mounting area of the drive IC 1. A resist 5 made of an epoxy resin or the like is formed on the film substrate 4 except for the mounting area of the driving IC 1. A curing material 24 is interposed between the driving IC 1 and the wiring board 20. Thereby, the connection between the bump 2 and the connection terminal 32 is stably maintained.

  On the other hand, in order to prevent the first wiring pattern 30 from crossing on the surface of the film substrate 4 on the surface (back surface) of the film substrate 4 opposite to the side on which the driving IC 1 is mounted, A wiring pattern (hereinafter referred to as “second wiring pattern”) 31 in which a part of 30 is bypassed on the back surface is formed. As shown in FIG. 2, the second wiring pattern 31 on the back surface of the film substrate 4 is arranged away from the connection portion between the bump 2 and the connection terminal 32 (a region where the bump 2 and the connection terminal 32 overlap in plan view). ing. The reason why the second wiring pattern 31 is arranged away from the connection portion of the bump 2 is that when the second wiring pattern 31 crosses the region of the connection portion between the bump 2 and the connection terminal 32, the thickness of the second wiring pattern 31 is the same. This is because a difference in height (about 5 to 30 μm) can be made, so that stable connection between the bump 2 and the connection terminal 32 becomes difficult.

  A bubble measurement pattern is formed on the back surface of the film substrate 4 and in a region where the driving IC 1 is mounted. The bubble measurement pattern includes a film 6 having a plurality of openings 8 arranged in a matrix. The film 6 may be formed of the same material as the second wiring pattern 31, for example, Cu. If there is no particular problem, the second wiring pattern 31 may be connected to the film 6.

  In the present embodiment, the film 6 has a quadrangular shape having an outer periphery along the arrangement of the bumps 2 and has substantially the same film thickness as the second wiring pattern 31. The plurality of openings 8 are formed inside the bumps 2 of the driving IC 1, in other words, in a region surrounded by the bumps 2. Since the openings 8 are formed so as not to overlap the bumps 2, the thickness of the wiring substrate 20 at the connection portion between the bumps 2 and the connection terminals 32 becomes constant, and connection failures can be reduced.

  The film 6 may be formed in a region including at least the connection portion between the bump 2 and the connection terminal 32, and is not limited to the mode shown in FIG. For example, the film 6 may be formed in a region overlapping with the driving IC 1. In this case, an opening 8 may be further formed outside the bump 2.

  An elastic insulating film 7 is formed on the back surface of the film substrate 4. As the insulating film 7, for example, a resist made of epoxy resin can be used. The insulating film 7 is formed on the entire back side of the film substrate 4, and the second wiring pattern 31 and the film 6 are covered with the insulating film 7. Since the insulating coating 7 having elasticity is formed on the back surface of the film substrate 4, pressure non-uniformity due to the bump height variation of the bumps 2 and the terminal height variation of the connection terminals 32 is alleviated. Therefore, the bump 2 and the connection terminal 32 can be connected more stably. Further, a buffering effect can be obtained when foreign matter is caught between the wiring board 20 and the stage at the time of connection.

  In the wiring substrate 20 of this embodiment, the first and second wiring patterns 30 and 31 and the film 6 are formed on the film substrate 4 by a casting method or an additive method, and the resist 5 and the insulating film 7 are formed by a printing method or the like. By doing so, it can be manufactured. Note that the opening 8 may be formed in the film 6 by photolithography.

  Next, a process of face-down mounting the driving IC 1 on the wiring board 20 will be described. In the connection method using the anisotropic conductive film (ACF), the ACF is pasted on the film substrate 4 so as to cover the connection terminal 32, the driving IC 1 is aligned, and then heated with a tool (not shown). The bump 2 of the driving IC 1 and the connection terminal 32 are connected by pressing. The anisotropic conductive film has an adhesive whose main component is an epoxy resin and metal film-coated plastic fine particles dispersed in the adhesive. The metal film-coated plastic fine particles are conductive particles obtained by performing metal plating on plastic beads. The epoxy resin is a thermosetting type, and by applying heat and pressure at a connection temperature of 180 to 210 ° C., the conductive particles are sandwiched between the bumps 2 and the connection terminals 32, and the adhesive in the epoxy resin is thermoset. Electrical connection is maintained.

  In the connection method by Au—Sn metal eutectic bonding, the driving IC 1 on which the bump 2 made of Au is formed and the connection terminal 32 subjected to Sn plating are thermocompression bonded at 400 ° C. to melt the Sn plating, and Au -Metal eutectic bonding with Sn eutectic. After the driving IC 1 is metal eutectic bonded onto the film substrate 4, an insulating underfill resin such as an epoxy resin is injected into the gap between the driving IC 1 and the film substrate 4, and the connection portion is covered and stabilized. .

  In the low-temperature connection method using NCP (Non Conductive Paste) or NCF (Non Conductive Film), NCP (viscous liquid insulating resin) is applied to the driving IC1 mounting region on the wiring board 20, or NCF Affix (film-like insulating resin). The wiring board 20 and the driving IC 1 are aligned. Using a crimping tool (not shown), the bumps 2 of the IC 1 and the connection terminals 32 of the film substrate 4 are pressed while being heated at around 200 ° C., which is lower than in the case of the Au—Sn metal eutectic bonding. Join metal. Since the melting points of Sn and Au are 232 ° C. and 1064 ° C., respectively, both are not melted at the time of connection.

  In any of the connection methods described above, there is a risk that bubbles adhering between the driving IC 1 and the film substrate 4 may expand due to thermal expansion during the thermocompression bonding or the reflow heating process.

  FIG. 4 is a cross-sectional view schematically showing a state in which bubbles 13 are generated between the driving IC 1 and the film substrate 4. In the wiring substrate 20 of this embodiment, since the film 6 has the opening 8, the visible light transmittance is different between the region having the opening 8 and the region having no opening 8. In other words, the bubble measurement pattern is formed by the film 6 including a plurality of regions having different visible light transmittances. Thereby, the presence of the bubble 13 can be confirmed by the observer observing from the back side of the wiring board 20. Further, since the plurality of openings 8 are arranged in a matrix at a predetermined pitch, by counting the number of openings 8 overlapping the bubbles 13 or comparing the dimensions of the bubbles 13 and the openings 8, Dimensions can be measured. As a non-limiting example, the pitch of the openings 8 is about 0.2 μm to 0.4 μm, and the diameter of the openings 8 is about 0.1 μm to 0.2 μm.

  In the present embodiment, the film 6 having the plurality of openings 8 is formed of the same material (Cu) as the second wiring pattern 31, but the film 6 may be formed of a material different from that of the second wiring pattern 31. . For example, the film 6 may be formed of a non-conductive material such as a color filter material or a black matrix. In the present embodiment, a plurality of regions having different visible light transmittances are formed in the film 6 by forming openings in the film 6, but the present invention is not limited to this. For example, a plurality of regions having different color tones may be formed.

  In the present embodiment, the shape of the opening 8 is circular, but is not limited thereto. 5 and 6 are bottom views schematically showing modifications of the present embodiment. The wiring board 30 shown in FIG. 5 has a square shape in the opening 9, and the wiring board 40 shown in FIG. 6 has a diamond shape in the opening 10.

  In the present embodiment, the plurality of openings 8 are linearly arranged in the row direction and the column direction. However, for example, they may be arranged in a staggered pattern in the column direction and linearly in the row direction. Further, the plurality of openings 8 are evenly arranged in the region surrounded by the bumps 2. However, the openings 8 are arranged only in the region where the bubbles 13 are likely to be generated, and the openings 8 are formed in the IC mounting region. May be non-uniformly distributed.

  According to the present embodiment, the dimensions of the thermally expanded bubbles can be visually confirmed, and the wiring board 20 containing the bubbles 13 having dimensions that impair the connection reliability between the bumps 2 and the connection terminals 32 is manufactured on the production line. Can be removed from. An electronic circuit element (FPC) is manufactured by mounting chip parts such as capacitors and resistors, and a semiconductor package on the wiring board 20 determined to be normal by an observer using SMT (Surface Mount Technology). Further, the flexible printed wiring board FPC is connected to the end of the liquid crystal panel P using ACF or the like. The liquid crystal display device of this embodiment is manufactured through the above steps.

  As mentioned above, although this invention was demonstrated based on embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Those skilled in the art will understand that the above-described embodiments are exemplifications, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. By the way. For example, in the above embodiment, the active matrix liquid crystal display device using TFTs has been described as an example. However, the display device of the present invention may be an active matrix liquid crystal display device using not only a three-terminal element such as a TFT but also a two-terminal element such as an MIM (Metal Insulator Metal) as a switching element. The display device of the present invention can be applied not only to an active drive type display device but also to a passive (multiplex) drive type display device. Furthermore, the display device of the present invention can be applied to any type of display device of transmissive type, reflective type, and transmissive / reflective type.

  The present invention can be used for various display devices such as liquid crystal display devices, mobile phones, portable game devices, electronic notebooks, portable information terminals, music information terminals, video information terminals, and the like.

It is a top view which shows the liquid crystal display device of embodiment typically. FIG. 5 is a schematic bottom view of the wiring board 20 in the mounting area of the driving IC 1 and in the vicinity thereof. 2 is a schematic cross-sectional view of a wiring board 20 in a mounting area of the driving IC 1 and in the vicinity thereof. FIG. FIG. 4 is a cross-sectional view schematically showing a state in which bubbles 13 are generated between the driving IC 1 and the film substrate 4. It is a bottom view showing typically the modification of an embodiment. It is a bottom view showing typically the modification of an embodiment. It is a typical bottom view of the wiring board described in patent documents 1. It is a typical sectional view of a wiring board indicated in patent documents 1.

Explanation of symbols

1 Driving IC
2 Bump 4 Film substrate 5 Resist 6 Film 7 Insulating coating (resist)
8, 9, 10 Opening 13 Air bubbles 14 Underfill resin 16 Dummy pattern 20, 21, 22 Wiring board 24 Curing material 30 First wiring pattern (surface wiring pattern)
31 Second wiring pattern (back wiring pattern)
32 Connection terminal 100 Wiring board

Claims (7)

It has at least an insulating substrate and a first wiring pattern formed on one surface of the insulating substrate, and bumps of the integrated circuit chip are connected to connection terminals formed at end portions of the first wiring pattern. A wiring board on which the integrated circuit chip is mounted,
A wiring substrate having a bubble measurement pattern formed on the other surface of the insulating substrate and formed in a mounting region of the integrated circuit chip. The wiring board according to claim 1, further comprising a second wiring pattern formed on the other surface of the insulating substrate and formed in a region other than the mounting region of the integrated circuit chip. The wiring substrate according to claim 1, wherein an anisotropic conductive film or a curing material is interposed between the integrated circuit chip and the insulating substrate. The wiring board according to claim 1, wherein the bubble measurement pattern is formed of a film including a plurality of regions having different visible light transmittances. The wiring board according to claim 1, wherein the bubble measurement pattern is formed of a film having a plurality of openings arranged in a matrix. An electronic circuit element comprising the wiring board according to claim 1 and the integrated circuit chip. A display device comprising the electronic circuit element according to claim 6.

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