JP2006301029A - On-screen display apparatus and on-screen display creating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain low power consumption by reducing processing load when displaying an image. <P>SOLUTION: In the invention, a thumbnail video face SBR, a background face BGGR overlapped with a back face side and a foreground face FGGR overlapped with a front face side of the thumbnail video face SBR are independently created, and the on-screen image D3 is created by sequentially overlapping them. Thereby, when the background face BGGR and the foreground face FGGR are overlapped with the thumbnail video face SBR, the on-screen image D3 is created only by adding the background face BGGR and the foreground face FGGR like components, without newly redrawing. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an on-screen display device and an on-screen display generation method, and is suitable for application to, for example, a video camera for a broadcasting station.

Conventionally, in a video camera used for production of a television broadcast program, various processing processes are applied to a video signal, and as one of them, a menu or the like is superimposed on a base image. A device having an on-screen display function is known (for example, see Patent Document 1).
JP-A-6-303521

  By the way, in a video camera having such a configuration, signal processing when an on-screen image is generated by superimposing a menu or the like on a base image is performed in software by a drawing engine such as a CPU (Central Processing Unit).

  For this reason, in a video camera, for example, if the on-screen image cursor is moved in response to a user operation, the on-screen image must be redrawn each time. In this case, there is a problem that the processing load on the CPU is very large and the power consumption increases.

  The present invention has been made in view of the above points, and intends to propose an on-screen display device and an on-screen display generation method that reduce the processing load when generating an on-screen image and reduce power consumption. Is.

  In order to solve this problem, in the on-screen display device of the present invention, a video plane generating means for generating a video plane composed of layers for displaying a video image, and a background image located on the back side with respect to the video plane Background surface generation means for generating a background surface composed of layers for display and foreground surface generation for generating a foreground surface composed of layers for displaying a surface image located on the surface side with respect to the video surface And an on-screen image is generated by sequentially superimposing the background surface, the video surface, and the foreground surface in a predetermined order.

  In this way, the video surface, the background surface superimposed on the back side of the video surface, and the foreground surface superimposed on the surface side are separately generated, and sequentially superimposed to generate an on-screen image. When a background surface or foreground surface is superimposed on a surface, it is only necessary to add the background surface or foreground surface like a component, and an on-screen image can be generated without redrawing.

  In the on-screen display generation method of the present invention, a background for generating a background plane composed of a layer for displaying a background image positioned on the back side with respect to a video plane composed of a layer for displaying a video image. A plane generation step, a video plane generation step of generating a video plane and overlaying the video plane on a background plane, and a fore comprising a layer for displaying a surface image located on the front side of the video plane A foreground plane generation step for generating an on-screen image by generating a ground plane and superimposing the foreground plane on the video plane;

  By generating a background surface that is superimposed on the back side of the video surface in this way, overlaying the video surface on top of it, and further overlaying the foreground surface on top of that, an on-screen image is generated. It is only necessary to add a background surface or a foreground surface to the video surface like a component, and an on-screen image can be generated without redrawing.

  According to the present invention, the video screen, the background surface overlaid on the back side of the video surface, and the foreground surface overlaid on the surface side are separately generated, and are sequentially stacked to generate an on-screen image. Therefore, when a background surface or foreground surface is superimposed on a video surface, it is only necessary to add the background surface or foreground surface like a component, and an on-screen image can be generated without redrawing. Thus, it is possible to realize an on-screen display device and an on-screen display generation method that reduce the processing load when displaying an image and reduce power consumption.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

(1) Configuration of Video Camera In FIG. 1, reference numeral 1 denotes a video camera as a whole, for example, main line video data S1 recorded by the MPEG (Moving Picture Experts Group) 2 system is decoded by the MPEG decoder 2, and the result The obtained video signal S2 having an image size of 1440 × 1080 (number of horizontal pixels × number of lines) is sent to the switch circuit 3.

  Here, the video signal S2 has an image size conforming to the MPEG2 video (profile & level: MP @ H-14) standard, and the first horizontal pixel conversion circuit 6 and the second horizontal pixel conversion provided in the subsequent stage. The circuit 8 has an optimum number of pixels in consideration of the processing load when converting the number of horizontal pixels of the video signal S2.

  On the other hand, for example, the video camera 1 has a luminance of 352 × 288 corresponding to a CIF (Common Intermediate Format) picture format recorded by the MPEG4 system, an image size of two color differences of 180 × 144, or SIF (Source Input Format). The proxy video data D1 of the reference video having an image size of 352 × 240 corresponding to the picture format and two color differences of 176 × 120 is decoded by the proxy decoder 4, and the resulting proxy video signal D2 is on-screen. It is sent to a display generation unit (hereinafter referred to as OSD generation unit) 5.

  The OSD generation unit 5 generates a thumbnail list image having an image size of 1440 × 1080 (the number of horizontal pixels × the number of lines), which is a collection of a plurality of proxy video signals D2, as a thumbnail video surface, and a background ( An on-screen image D3 obtained by arranging a background image on the back surface side as a background surface and a menu on the foreground (front) side of the thumbnail video surface and overlaying them. The data is sent to the switch circuit 3.

  Here, the on-screen image D3 also has an image size compliant with the MPEG2 video (profile & level: MP @ H-14) standard, and the first horizontal pixel conversion circuit 6 and the second horizontal pixel provided in the subsequent stage. This is the optimum number of pixels considering the processing load when the number of horizontal pixels is converted by the pixel conversion circuit 8.

  The switch circuit 3 is switched in accordance with an instruction from a user operation button (not shown), and either the video signal S2 from the MPEG decoder 2 or the on-screen image D3 from the OSD generation unit 5. Is output.

  When the video signal S2 is selectively output, the switch circuit 3 sends the video signal S2 to the first horizontal pixel conversion circuit 6 and the second horizontal pixel conversion circuit 8 in the down-conversion unit 7, respectively.

  The first horizontal pixel conversion circuit 6 converts the number of horizontal pixels of the video signal S2 from 1440 to 1920 by multiplying the number of horizontal pixels of the video signal S2 by 4/3, that is, 1920 × 1080 (number of horizontal pixels × A main HD (High Definition) image S3 having an image size of the number of lines) is generated, and this is lined out as a main HD output.

  The second horizontal pixel conversion circuit 8 converts the number of horizontal pixels of the video signal S2 from 1440 to 720 by halving the number of horizontal pixels of the video signal S2, that is, 720 × 1080 (number of horizontal pixels × A video signal S4 having an image size of (number of lines) is generated and sent to the vertical line conversion circuit 9.

  The vertical line conversion circuit 9 converts the number of lines of the video signal S4 having an image size of 720 × 1080 (the number of horizontal pixels × the number of lines) at a predetermined conversion ratio, and thereby various methods (finally output) ( For example, main line SD of image size (720 × 480 (number of horizontal pixels × number of lines) or 720 × 576 (number of horizontal pixels × number of lines)) adapted to NTSC (National Television System Committee) or PAL (Phase Alternation by Line)) (Standard Definition) An image S5 is generated and is lined out as a main line SD output.

  Incidentally, the vertical line conversion circuit 9 may multiply the number of lines of the video signal S2 by 4/9 when converting from 1080 to 480, and 8 when converting the number of lines from 1080 to 576. / 15 times.

  On the other hand, when the switch circuit 3 selectively outputs the on-screen image D3 instead of the video signal S2, the switch circuit 3 sends the on-screen image D3 to the first horizontal pixel conversion circuit 6 and the second horizontal pixel conversion circuit 8, respectively. To do.

  As in the case of the video signal S2, the first horizontal pixel conversion circuit 6 converts the number of horizontal pixels from 1440 to 1920 by multiplying the number of horizontal pixels of the on-screen image D3 by 4/3, that is, 1920 × A proxy HD (High Definition) image D4 having an image size of 1080 (the number of horizontal pixels × the number of lines) is generated, and this is lined out as a proxy HD output.

  Similarly to the case of the video signal S2, the second horizontal pixel conversion circuit 8 converts the horizontal pixel number from 1440 to 720 by halving the horizontal pixel number of the on-screen image D3, that is, 720 × An on-screen image D 5 having an image size of 1080 (the number of horizontal pixels × the number of lines) is generated and sent to the vertical line conversion circuit 9.

  The vertical line conversion circuit 9 converts the number of lines of the on-screen image D5 having an image size of 720 × 1080 (the number of horizontal pixels × the number of lines) at a predetermined conversion ratio, and thereby various methods to be finally output. A proxy SD on-screen image D6 having an image size (720 × 480 or 720 × 576) adapted to (for example, NTSC or PAL) is generated, and this is lined out as a proxy SD output.

  As described above, in the video camera 1, 1920 × 1080 (the number of horizontal pixels × the number of lines) is obtained by up-converting the number of horizontal pixels of the video signal S 2 decoded by the MPEG decoder 2 by the first horizontal pixel conversion circuit 6. A main line HD image S3 having an image size can be generated, and this can be lined out as a main line HD output, and the horizontal pixel number and line number of the video signal S2 are down-converted by the down-conversion unit 7, thereby It is possible to generate a main SD image S5 having an image size adapted to the method or the PAL method, and line it out as a main SD output.

  Similarly, in the video camera 1, 1920 × 1080 (the number of horizontal pixels × the number of lines) is obtained by up-converting the number of horizontal pixels of the on-screen image D3 generated by the OSD generation unit 5 by the first horizontal pixel conversion circuit 6. By generating a proxy HD image D4 having the image size of the image and line-out it as a proxy HD output, the down-converter 7 down-converts the number of horizontal pixels and the number of lines of the on-screen image D3. It is possible to generate a proxy SD on-screen image D6 having an image size adapted to the NTSC system or the PAL system, and line it out as a proxy SD output.

  By the way, in the video camera 1, the image size of the video signal S2 and the on-screen image D3 is 1440 × 1080 (the number of horizontal pixels × the number of lines) conforming to the MPEG2 video (profile & level: MP @ H-14) standard. When the number of horizontal pixels is converted from 1440 to 1920 by the first horizontal pixel conversion circuit 6, it may be multiplied by 4/3 according to the ratio of 1440: 1920, and the horizontal pixel number is converted by the second horizontal pixel conversion circuit 8. When converting the number from 1440 to 720, it is only necessary to multiply by 1/2 according to the ratio of 1440: 720, so that the processing burden associated with the calculation can be greatly reduced compared to the case where a complicated conversion ratio is used. ing.

  Incidentally, in the video camera 1, the image size of the video signal S2 and the on-screen image D3 is 1440 × 1080 (the number of horizontal pixels × the number of lines), but this is 1920 × 1080 (the number of horizontal pixels × (Number of lines).

  In this case, the video camera 1 does not require the first horizontal pixel conversion circuit 6, and the second horizontal pixel conversion circuit 8 converts the number of horizontal pixels of the video signal S2 and the on-screen image D3 from 1920 to 720. What is necessary is just to multiply 3/8 according to the ratio of 1920: 720.

  Furthermore, in the video camera 1, the image size of the video signal S2 and the on-screen image D3 is set to 1440 × 1080 (the number of horizontal pixels × the number of lines), but this is 720 × 1080 (the number of horizontal pixels × (Number of lines).

  In this case, the video camera 1 does not require the second horizontal pixel conversion circuit 8, and the first horizontal pixel conversion circuit 6 converts the number of horizontal pixels of the video signal S2 and the on-screen image D3 from 720 to 1920. What is necessary is just to multiply 8/3 according to the ratio of 1920: 720.

(2) Circuit Configuration of OSD Generating Unit As shown in FIG. 2, the OSD generating unit 5 temporarily stores the proxy video signal D2 supplied from the proxy decoder 4 (FIG. 1) in the internal buffer 11, and then the resizing circuit 12 The thumbnail image data D2A obtained by the size conversion to generate a thumbnail image of a predetermined size and cached as a result is cached in an external memory 40 such as an SDRAM (Synchronous Dynamic Random Access Memory) via the memory controller 13.

  The memory controller 13 accumulates a plurality of thumbnail image data D2A sequentially supplied from the resize circuit 12 in the external memory 40, reads out the thumbnail image data D2A from the external memory 40 as necessary, and The data is output to the layer 5 generation circuit 24.

  The layer 5 generation circuit 24 arranges a plurality of thumbnail image data D2A read from the external memory 40 via the memory controller 13 in a listable state according to a predetermined order and arrangement, thereby providing a plurality of thumbnail image data D2A as shown in FIG. A thumbnail video screen SBR layer is formed based on the thumbnail image data D2A for the number of sheets, and this is output to the fourth synthesis circuit 23.

  By the way, the OSD generation circuit 5 (FIG. 2) generates a background surface BGGR (to be described later) composed of a background image or the like to be arranged on the background (back surface) side with respect to the thumbnail video surface SBR (FIG. 3). A background graphics generation unit 14, and a foreground graphics generation unit 15 for generating a foreground surface FGGR (described later) including a menu or the like to be arranged on the foreground (front) side with respect to the thumbnail video surface SBR; The video plane generation unit 10, the background graphics generation unit 14, and the foreground graphics generation unit 15 are controlled by the CPU 35.

  Incidentally, the CPU 35 can also control the resize circuit 12, and thereby, the image size and the like of the thumbnail image data D2A constituting the thumbnail video surface SBR can be arbitrarily adjusted. .

  As shown in FIG. 4, the background graphics generation unit 14 generates a background surface BGGR to be positioned on the back side of the thumbnail video surface SBR (layer 5) by using five types of layer configurations (layer 0 to layer 4). The foreground graphics generation unit 15 generates the foreground surface FGGR to be positioned on the front side of the thumbnail video surface SBR by using three types of layer configurations (layer 6 to layer 8).

  The background surface BGGR is positioned above the background image plane BB (layer 0) positioned at the lowest layer, the first background texture BT1 (layer 1) positioned above it, and the first background texture BT1. The second background texture BT2 (layer 2), the cursor window plane CW (layer 3) positioned on the second background texture BT2, and the monochrome rectangular plane (layer 3) positioned on the cursor window plane CW ( It is formed by combining with layer 4).

  That is, the background graphics generation unit 14 (FIG. 2) sends the background image plane BB generated by the layer 0 generation circuit 16 to the first synthesis circuit 17 and the first background generated by the layer 1 generation circuit 18. The texture BT1 is sent to the first synthesis circuit 17.

  The first synthesis circuit 17 synthesizes the first background texture BT1 on the background image plane BB, and sends the synthesis result to the second synthesis circuit 19.

  Here, the background image plane BB generated by the layer 0 generation circuit 16 has “color” of the background image plane BB as its attribute information, and the background is changed according to the parameter change from the CPU 35 to the layer 0 generation circuit 16. The “color” of the image plane BB is changed.

  Similarly, the first background texture BT1 generated by the layer 1 generation circuit 18 has a texture “pattern pattern” as its attribute information, and in response to a parameter change from the CPU 35 to the layer 1 generation circuit 18 The “pattern pattern” of the first background texture BT1 is changed.

  The second synthesis circuit 19 receives the second background texture BT2 generated by the layer 2 generation circuit 20, and superimposes the second background texture BT2 on the synthesis result supplied from the first synthesis circuit 17. The two are combined again, and the combined result is sent to the third combining circuit 21.

  The second background texture BT2 generated by the layer 2 generation circuit 20 also has a texture “pattern pattern” as an attribute thereof, and the second background texture BT2 is changed according to the parameter change to the layer 2 generation circuit 20 from the CPU 35. The “pattern pattern” of the ground texture BT2 is changed.

  The third synthesis circuit 21 receives the cursor window plane CW and the monochrome rectangular plane RT generated by the layers 3 and 4 generation circuit 22 and receives the cursor window plane for the synthesis result supplied from the second synthesis circuit 19. By sequentially superimposing the CW and the monochrome rectangular plane RT, a background surface BGGR composed of a total of five types of layers (layer 0 to layer 4) as shown in FIG. Output to the fourth synthesis circuit 23.

  Here, the cursor window plane CW generated by the layer 3 and 4 generation circuit 22 forms a frame for each thumbnail image of the thumbnail list image D50, and is all formed by a rectangular figure. Incidentally, the cursor window plane CW is generated by the number of frames preset by the layer 3 and 4 generation circuit 22, and the number of frames cannot be increased later.

  Note that the cursor window plane CW and the monochrome rectangular plane RT have “color”, “vertical and horizontal dimensions”, “transparency”, and “position” as attribute information, and the layers from the CPU 35. The “color”, “vertical / horizontal dimension”, “transparency”, and “position” of the rectangular figure can be changed according to the parameter change to the 3, 4 generation circuit 22.

  The fourth synthesizing circuit 23 of the video plane generating unit 10 performs the thumbnail video plane SBR supplied from the layer 5 generating circuit 24 on the background plane BGGR supplied from the third synthesizing circuit 21 of the background graphics generating unit 14. By superimposing (FIG. 3), a combined result in a state where the thumbnail video surface SBR is superimposed on the background surface BGGR is generated, and this is transmitted to the fifth combining circuit 25 of the foreground graphics generating unit 15. To do.

  Incidentally, the thumbnail video plane SBR generated by the layer 5 generation circuit 24 has “transparency”, “arrangement”, and the like of the thumbnail image as its attribute information. The “transparency” of each thumbnail image can be changed according to the parameter change, and the “arrangement” of each thumbnail image can be changed.

  The fifth synthesis circuit 25 superimposes the first foreground character plane FC1 (layer 6) having the predetermined font supplied from the layer 6 generation circuit 26 on the synthesis result supplied from the fourth synthesis circuit 23. And the result of the synthesis is sent to the sixth synthesis circuit 28.

  The layer 6 generation circuit 26 has a character generator therein and is connected to the font memory 27. A plurality of layers stored in the font memory 27 according to parameter changes to the layer 6 generation circuit 26 from the CPU 35. The font used for the first foreground character plane FC1 (layer 6) can be selected from the types of fonts, and the color and display position of the characters can be changed.

  The sixth synthesis circuit 28 receives the supply of the menu frame plane BC generated by the layer 7 generation circuit 29, and again superimposes the menu frame plane BC on the synthesis result supplied from the fifth synthesis circuit 25. The synthesized result is sent to the seventh synthesis circuit 30.

  The menu frame plane BC generated by the layer 7 generation circuit 29 has “size” and “shape” of the menu frame as its attribute information, and responds to parameter changes to the layer 7 generation circuit 29 from the CPU 35. The menu frame “size” and “shape” can be changed. This menu frame plane CB is also generated by the number of frames preset by the layer 7 generation circuit 29, and the number of menu frames cannot be increased later.

  The seventh synthesis circuit 30 is supplied with the second foreground character plane FC2 generated by the layer 8 generation circuit 31, and receives the second foreground character plane FC2 for the synthesis result supplied from the sixth synthesis circuit 28. Are combined again, and the combined result is output as an on-screen image D3 as shown in FIG. 6 to the subsequent switch circuit 3 (FIG. 1).

  By the way, the foreground graphics generation unit 15 synthesizes layers 6, 7, and 8 through the fifth synthesis circuit 25, the sixth synthesis circuit 28, and the seventh synthesis circuit 30 when viewed as a single unit. Foreground surface FGGR as shown in FIG. 7 is generated.

  As described above, the OSD generation unit 5 is provided with the background graphics generation unit 14 and the foreground graphics generation unit 15 before and after the video plane generation unit 10 so that the thumbnail video plane SBR is positioned on the back side. The background surface BGGR and the foreground surface FGGR positioned on the front side can be individually generated.

  Accordingly, the CPU 35 of the OSD generation unit 5 controls the output to the background graphics generation unit 14 and the foreground graphics generation unit 15 located before and after the video plane generation unit 10, so that the background plane with respect to the thumbnail video plane SBR. Whether or not the BGGR and the foreground surface FGGR are superimposed can be freely controlled.

  The layer 8 generation circuit 31 also has an internal character generator and is connected to the font memory 32, and is stored in the font memory 32 in accordance with parameter changes to the layer 8 generation circuit 31 from the CPU 35. A font used for the second foreground character plane FC2 (layer 8) can be selected from a plurality of types of fonts, and the color and display position of the characters can be changed.

  Incidentally, with respect to the fonts stored in the font memories 27 and 32, a new font can be written from the host CPU 34 via the host interface 33.

(3) Operation and Effects In the above configuration, the video camera 1 converts the video signal S2 and the number of horizontal pixels of the on-screen image D3 by the first horizontal pixel conversion circuit 6 and the second horizontal pixel conversion circuit 8. Since the image size of 1440 × 1080 (the number of horizontal pixels × the number of lines) is selected in consideration of the processing load, the conversion ratio when converting the number of horizontal pixels to HD output or SD output is 4/3 times or Calculations can be made using a relatively simple magnification such as 1/2 times.

  For this reason, in the video camera 1, the calculation processing burden of the first horizontal pixel conversion circuit 6 and the second horizontal pixel conversion circuit 8 can be greatly reduced as compared with the case where conversion processing is performed using a complicated conversion ratio. Power consumption can be reduced by that amount.

  In particular, in the video camera 1, the video signal S2 and the on-screen image D3 are selected as the number of horizontal pixels 1440 from the value of the number of pixels between the horizontal pixel number 1920 of HD output and the horizontal pixel number 720 of SD output. For this reason, when performing two-line output of HD output and SD output at all times, the calculation processing load and calculation processing time for performing HD output are substantially equal to the calculation processing load and calculation processing time for performing SD output, It is possible to produce an effect that it is difficult to cause a time shift between the HD output and the SD output.

  Further, in the video camera 1, when generating an on-screen image adjusted from the beginning to the HD output or generating an on-screen image adjusted from the beginning to the SD output, the first horizontal pixel conversion circuit 6 or the second horizontal pixel is generated. Although either one of the conversion circuits 8 is unnecessary, the processing load on the second horizontal pixel conversion circuit 8 or the first horizontal pixel conversion circuit 6 on the other side is increased, and the image quality difference between the HD output and the SD output is large. It gets bigger and the balance is bad.

  On the other hand, in the video camera 1, the on-screen image D3 generated by the OSD generation unit 5 is up-converted by a first horizontal pixel conversion circuit 6 and a second horizontal pixel conversion circuit 8 at a relatively simple conversion ratio. Since down-conversion can be performed, the processing burden on the first horizontal pixel conversion circuit 6 and the second horizontal pixel conversion circuit 8 can be reduced, and the image quality difference can be minimized.

  In the OSD generation unit 5, when generating the on-screen image D <b> 3, the CPU 35 does not generate all the software, but the background graphics generation unit 14 and the foreground graphics generation unit 15 are provided before and after the video plane generation unit 10. Are provided as hardware, and the video plane generation unit 10, the background graphics generation unit 14, and the foreground graphics generation unit 15 are used as components for generating an on-screen image D3 to be finally output.

  Therefore, in the OSD generation unit 5, the parameter setting for the background graphics generation unit 14, the video plane generation unit 10, and the foreground graphics generation unit 15 is enormous, but the specific gravity of software processing is small compared to the conventional case, and the CPU 35 Can significantly reduce the processing burden.

  Further, the CPU 35 of the OSD generation unit 5 only controls the output to the background graphics generation unit 14 and the foreground graphics generation unit 15 located before and after the video plane generation unit 10, and the background plane with respect to the thumbnail video plane SBR. Whether or not BGGR and foreground surface FGGR are to be overlaid can be determined freely, and the processing burden associated with the calculation at that time is much lighter than when rendering in software.

  That is, the OSD generation unit 5 controls the output of the background graphics generation unit 14 when adding the background plane BGGR to the thumbnail video plane SBR, and stops outputting the background graphics generation unit 14 when erasing the background plane BGGR. Control the output of the foreground graphics generator 15 when adding the foreground plane FGGR to the thumbnail video plane SBR, and control the output stop of the foreground graphics generator 15 when deleting the foreground plane FGGR. Well, there is no need to redraw each time the content of the on-screen image D3 is rewritten as in the prior art, and the processing load on the CPU 35 can be greatly reduced.

  The CPU 35 of the OSD generation unit 5 only needs to stop the output of the foreground graphics generation unit 15 when erasing the foreground plane FGGR constituting the menu from the on-screen image D3, and there is almost no processing load. .

  Further, in the OSD generation unit 5, the data to be transferred from the external memory 40 to the layer 5 generation circuit 24 is only the thumbnail image D2A and does not include the background surface BGGR or the foreground surface FGGR. Can be suppressed. For this reason, the OSD generation unit 5 has a margin in the bandwidth when transferring from the external memory 40 to the layer 5 generation circuit 24 via the memory controller 13, thereby enabling buffering for delay adjustment.

  According to the above configuration, the video camera 1 has a comparative conversion ratio of 4/3 times or 1/2 times as a conversion ratio when converting the number of horizontal pixels of the video signal S2 and the on-screen image D3 to HD output or SD output. Since the calculation can be performed using a simple integer ratio, the calculation processing load by the first horizontal pixel conversion circuit 6 and the second horizontal pixel conversion circuit 8 can be greatly reduced, and the power consumption can be reduced.

  Further, the OSD generation unit 5 of the video camera 2 is provided with a background graphics generation unit 14 and a foreground graphics generation unit 15 before and after the video plane generation unit 10 as hardware components, and these are used as an on-screen image D3. By generating, the specific gravity of software processing can be reduced and the processing load on the CPU 35 can be greatly reduced.

  As a result, the video camera 1 has both a reduction in the processing load at the camera level by using a simple conversion ratio and a reduction in the processing load in the OSD generation unit 5, and a significant processing burden compared to the conventional case. Reduction and power consumption can be achieved.

(4) Other Embodiments In the above-described embodiments, the background graphics generation unit 14, the video plane generation unit 10, and the foreground graphics generation unit 15 are arranged in order and overlapped sequentially in time series. Although the case where the image D3 is generated has been described, the present invention is not limited to this, and the background graphics generation unit 14, the video plane generation unit 10, and the foreground graphics generation unit 15 are arranged in parallel and generated individually. A superposition circuit or the like for superimposing the background surface BGGR, thumbnail video surface SBR, and foreground surface FGGR last in a predetermined order may be provided.

  In this case, the superimposing circuit can generate an on-screen image in which the order of superposition is changed by changing the superposition relationship with respect to the background surface BGGR, the thumbnail video surface SBR, and the foreground surface FGGR.

  In the above-described embodiment, the case where the video signal S2 having the number of horizontal pixels 1440 and the on-screen image D3 are converted into the number of horizontal pixels according to the HD output and the SD output has been described. The present invention is not limited to this, and a video signal and an on-screen image having a horizontal pixel number of 960 and a horizontal pixel number of 640 may be converted into an HD output and an SD output as long as they can be converted into HD output and SD output with a simple conversion ratio. .

  Further, in the above-described embodiment, the case where the on-screen image D3 is generated by superimposing the background surface BGGR and the foreground surface FGGR on the thumbnail video surface SBR has been described, but the present invention is not limited thereto. Alternatively, as shown in FIG. 8, an on-screen image may be generated by superimposing the background surface BGGR and the foreground surface FGGR on the video surface based on the video signal S2 of the main line video.

  Furthermore, in the above-described embodiment, the case where the on-screen image D3 is generated by superimposing the background surface BGGR and the foreground surface FGGR on the thumbnail video surface SBR has been described, but the present invention is not limited thereto. Instead, as shown in FIG. 8, an on-screen image may be generated by superimposing the background surface BGGR and the foreground surface FGGR on the video surface based on the video signal S2 of the main line video.

  Further, in the above-described embodiment, the case where the on-screen image D3 having a total number of 9 layers is generated by superimposing the background surface BGGR and the foreground surface FGGR on the thumbnail video surface SBR has been described. The present invention is not limited to this, and on-screen images of various other numbers of layers may be generated.

  Further, in the above-described embodiment, the video camera 1 capable of simultaneously performing 1920 × 1080 (horizontal pixel number × line number) HD output and 720 × 1080 (horizontal pixel number × line number) SD output is used. Although the present invention is not limited to this, the present invention is not limited to this, and video that can simultaneously output a standard-definition television signal composed of various numbers of horizontal pixels × number of lines and a high-definition television signal. A camera may be used.

  Furthermore, in the above-described embodiment, the case where the on-screen image D3 is lined out as HD output and SD output has been described. However, the present invention is not limited to this, and in addition to HD output and SD output, so-called view You may make it output a finder.

  The on-screen display device and on-screen display generation method of the present invention can be applied not only to a video camera but also to a stationary video deck.

It is a rough-line perspective view which shows the structure of the video camera in one embodiment of this invention. It is a rough-line block diagram which shows the circuit structure of an OSD production | generation part. It is a basic diagram which shows a thumbnail video surface. It is an approximate line figure used for explanation of composition of a plurality of layers. It is a basic diagram which shows a background surface. It is a basic diagram which shows an on-screen image. It is a basic diagram which shows a foreground surface. It is a basic diagram which shows the structure of the video camera in other embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Video camera, 2 ... MPEG decoder, 3 ... Switch circuit, 4 ... Proxy decoder, 5 ... OSD production | generation part, 6 ... 1st horizontal pixel conversion circuit, 7 ... Down conversion circuit, 8 2nd horizontal pixel conversion circuit, 9 ... vertical line conversion circuit, 10 ... video plane generation unit, 11 ... internal buffer, 12 ... resizing circuit, 13 ... memory controller, 14 ... background graphics Generation unit, 15... Foreground graphics generation unit, 35... CPU.

Claims (4)

Video plane generating means for generating a video plane composed of layers for displaying video images;
Background surface generating means for generating a background surface composed of layers for displaying a background image located on the back side with respect to the video surface;
Foreground surface generating means for generating a foreground surface composed of layers for displaying a surface image located on the surface side with respect to the video surface,
An on-screen display device that generates an on-screen image by sequentially superimposing the background surface, the video surface, and the foreground surface in a predetermined order. The on-screen display device is
Control means for changing the video image, the background image, and the surface image by issuing a change instruction to a predetermined parameter to the video plane generation means, the background plane generation means, and the foreground plane generation means; The on-screen display device according to claim 1, comprising: The on-screen display device according to claim 1, wherein the surface image forming the foreground surface is a menu screen. A background plane generating step for generating a background plane consisting of a layer for displaying a background image located on the back side with respect to a video plane consisting of a layer for displaying a video image;
Generating a video plane and superimposing the video plane on the background plane; and
A foreground surface composed of a layer for displaying a surface image located on the surface side with respect to the video surface is generated, and a foreground surface that generates an on-screen image by superimposing the foreground surface on the video surface is generated. An on-screen display generation method comprising: a ground plane generation step.

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