JP2006294798A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reliable wiring structure, especially a contact structure, for further micronization and higher sensitivity. <P>SOLUTION: The semiconductor device comprises a pad for external connection. The pad comprises: a first layer pad 3ap whose surface is flat and consists of a first layer conductive film; a second layer pad 3bp of such pattern form as to comprise a rough pattern on its surface on the first layer pad; and a metal pad 9p for bonding which reflects the rough pattern on the second layer pad to have a rough surface. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a pad structure of a solid-state image sensor.

  The pad for external connection that can be placed on the semiconductor device has a certain size while selecting an appropriate material as a wiring member in order to obtain stability of electrical connection such as bonding wires and bumps to be connected or to reduce contact resistance. It is necessary to ensure the thickness and prevent peeling.

  In such a situation, as shown in FIG. 8, a concavo-convex pattern is formed in the interlayer insulating film 101S, and a metal pad Bp made of an aluminum layer formed with a concavo-convex shape reflecting this concavo-convex pattern is formed. A structure in which a bonding wire is connected as a bonding pad has been proposed (Patent Document 1).

  According to this configuration, the contact area with the bonding wire is increased due to the uneven shape, and the bondability is improved. However, this structure has a problem that the film thickness of the aluminum layer is substantially reduced and the contact resistance is high. In addition, when there is a wiring layer on the base, it has a substantial capacitance, which may adversely affect device performance.

  By the way, a solid-state imaging device using a CCD used for an area sensor or the like includes a photoelectric conversion unit including a photodiode and the like, and a charge transfer unit including a charge transfer electrode for transferring a signal charge from the photoelectric conversion unit, Have A plurality of charge transfer electrodes are arranged adjacent to each other on a charge transfer path formed on the semiconductor substrate, and are sequentially driven.

In recent years, with the increase in the number of pixels of a CCD, the demand for higher resolution and higher sensitivity is increasing in solid-state imaging devices, and the number of imaging pixels is increasing to more than gigapixels.
In order to ensure high sensitivity in such a situation, it is extremely important to make the region other than the imaging region as small as possible due to problems such as limitations on the optical structure and yield.

  The same applies to the bonding pads for external connection arranged at the peripheral edge of the solid-state imaging device chip, and miniaturization is being promoted. Under such circumstances, in the solid-state imaging device, it is necessary to perform a probe test for the device characteristic inspection after completion, and the probe test needle is a serious problem. For this reason, when it is going to apply the bonding pad which reflects the unevenness | corrugation of the foundation | substrate as mentioned above, there exists a problem that a needle penetrates easily. Also, if the wiring layer has a multi-layer structure, it may not be possible to sufficiently concentrate light on the element region. Usually, a single-layer wiring is often used, so that the film thickness of the bonding pad may be increased by stacking. It was difficult.

JP 2002-305217 A

Thus, in the conventional semiconductor device, it has been difficult to achieve both needle penetration and bonding strength. This is particularly serious in a solid-state imaging device, and a pad structure that can withstand further miniaturization cannot be obtained, which has been a big problem that prevents miniaturization and high quality.
The present invention has been made in view of the above circumstances, and an object thereof is to provide a highly reliable wiring structure, particularly a contact structure, which can be miniaturized and highly sensitive.

Accordingly, the semiconductor device of the present invention is a semiconductor device having a pad portion for external connection, wherein the pad portion is composed of a first layer conductive film and has a flat surface, and a second layer conductivity. A bonding layer comprising a film and having a pattern on the surface of the first layer pad and having a pattern on the surface; And a pad.
According to this configuration, the first layer pad having a flat surface, the second layer pad having a pattern shape having irregularities on the surface, and the irregularities on the surface reflecting the irregularities on the second layer pad. Since the pad portion is composed of the metal pad for bonding, the probe does not pass through even in the inspection process. In addition, the presence of irregularities on both sides of the front and back enables strong bonding to the bonding wire and bonding to the ground and good electrical contact, enabling highly reliable mounting even when downsizing. Become. In addition, since it can be formed without increasing the number of steps only by changing the mask pattern in photolithography, the productivity is good.

  The semiconductor device of the present invention includes one in which the first layer pad is in an electrically floating state.

In the semiconductor device of the present invention, the semiconductor device includes a photoelectric transfer unit, a charge transfer unit including a charge transfer electrode that transfers charges generated in the photoelectric conversion unit, and the silicon substrate. In a solid-state imaging device comprising a wiring portion including a wiring layer connected to
The charge transfer electrode includes a first layer electrode made of a first layer conductive film and a second layer electrode made of a second layer conductive film.

  In the semiconductor device of the present invention, the first layer pad is formed in the same step as the first layer electrode, and the second layer pad is formed in the same step as the second layer electrode.

  In the semiconductor device of the present invention, the first layer pad may be formed in the same step as the first layer electrode, and the second layer pad may be formed in the same step as the light shielding film.

  In the semiconductor device of the present invention, the first layer pad includes the second layer electrode, and the second layer pad includes the same layer as the light shielding film.

  In the semiconductor device of the present invention, the first layer conductive film and the second layer conductive film include polycrystalline silicon.

  In the semiconductor device of the present invention, the metal pad is formed in the same process as the wiring layer. This wiring layer is preferably an aluminum wiring.

  The semiconductor device manufacturing method of the present invention is a method for manufacturing a semiconductor device having a pad portion for external connection, the step of forming an element region on the surface of the semiconductor substrate, and the first layer conductivity on the surface of the semiconductor substrate. Forming a conductive film, forming a first layer electrode wiring on the element region, and patterning the first layer conductive film so as to form a first layer pad on a peripheral portion; A step of forming an interlayer insulating film; a second layer conductive film is formed on the first interlayer insulating film; a second layer electrode wiring is formed on the element region; Patterning the second layer conductive film, forming a second interlayer insulating film so as to form a second layer pad having a small pattern of the pitch, and a second layer pad of the pad portion Reflect the shape of the small pattern on the top A metal film is formed to, and forming a metal pad having an uneven surface by patterning.

  Also, the method for manufacturing a semiconductor device of the present invention includes a method of patterning the first layer pad so as to be in an electrically floating state.

  Further, in the method of manufacturing a semiconductor device according to the present invention, the semiconductor device includes a charge transfer unit including a photoelectric conversion unit and a charge transfer electrode that transfers charges generated in the photoelectric conversion unit on a silicon substrate surface, A solid-state imaging device including a wiring portion including a wiring layer connected to the silicon substrate, wherein the charge transfer electrode includes a first layer electrode made of a first layer conductive film and a second layer conductive film. Including a step of forming a second layer electrode.

  The method for manufacturing a semiconductor device of the present invention includes a method in which the first layer pad is formed in the same step as the first layer electrode, and the second layer pad is formed in the same step as the second layer electrode.

  In the method for manufacturing a semiconductor device according to the present invention, the first layer pad may be formed in the same step as the first layer electrode, and the second layer pad may be formed in the same step as the light shielding film.

  The method for manufacturing a semiconductor device of the present invention includes a method in which the first layer pad is formed by the second layer electrode, and the second layer pad is formed in the same step as the light shielding film.

  In the method of manufacturing a semiconductor device according to the present invention, the first layer conductive film and the second layer conductive film may be polycrystalline silicon.

  In the method of manufacturing a semiconductor device according to the present invention, the step of forming the metal pad includes a step performed in the same step as the step of forming the wiring layer. This wiring layer is preferably an aluminum wiring.

  In the solid-state imaging device, the charge transfer electrode having a single-layer electrode structure is often formed in two steps, as in the case of the charge transfer electrode having a multilayer electrode structure. In this case, the first transfer electrode is formed. The electrode to be formed is called a first layer electrode, and the electrode formed for the second time is called a second layer electrode.

  According to the present invention, it is possible to form a semiconductor device having a highly reliable pad structure that has both a margin for needle penetration during probe inspection and an improvement in wire bonding, and can be miniaturized. Become.

Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1 is an explanatory diagram showing a pad portion of a solid-state imaging device according to an embodiment of the present invention. 2 is a cross-sectional view showing the main part of the solid-state imaging device, FIG. 3 is a plan view of the main part of the imaging region, and FIG. 4 is a plan view. 2 is a cross-sectional view taken along line AA in FIG. 4 and a cross section taken along line BB in FIG. 3 corresponds to an enlarged view of the imaging region 100 of FIG. 4, and FIG. 5 is a correspondence diagram of the imaging unit and the peripheral circuit unit. As shown in FIG. 1, the solid-state imaging device includes a first layer pad 3ap whose pad portion is made of doped amorphous silicon as a first layer conductive film and whose surface is flat and electrically floating. On the first layer pad 3ap, the second layer pad 3bp is made of doped amorphous silicon as the second layer conductive film and has a pattern shape having an uneven surface, and the unevenness is formed on the second layer pad 3bp. Reflecting, a metal pad 9p for bonding having unevenness on the surface is provided. Since the surface of the metal pad 9p is uneven, the connection with the bonding wire Bw is strong, and the base is an imaging unit as a first layer conductive film that forms the first layer electrode 3a. Of the doped amorphous silicon and the doped amorphous silicon as the second layer conductive film for forming the second layer electrode 3b are the same as the wiring layer connecting the image pickup unit and the peripheral circuit unit thereon. A metal pad 9p made of an aluminum layer formed in the process is formed so that there is no risk of the probe slipping during probe inspection.

  That is, as shown in a schematic plan view of FIG. 4, this solid-state imaging device includes an imaging region 100 composed of a photodiode and a charge transfer unit on a semiconductor substrate, and a peripheral circuit such as an amplifier formed in the periphery thereof. And a pad portion 300 as an external connection terminal on the peripheral portion. As shown in FIG. 2, a plurality of photodiode portions 30 are formed in the p-well 12 separated in the element isolation region 11, and a charge transfer portion 40 for transferring signal charges detected by the photodiodes It is formed so as to have a meandering shape between the diode portions 30. Although not shown in FIG. 3, the charge transfer channel 14 through which the signal charge transferred by the charge transfer unit 40 moves has a meandering shape in a direction crossing the direction in which the charge transfer unit 40 extends. It is formed.

  Further, an overdrain buffer layer 13 made of a high-concentration p-type semiconductor layer is formed below the p-well 12 so that charges can be drawn out by applying a voltage. On the surface of the charge transfer section 40, a first layer electrode 3a and a second layer electrode 3b are arranged via a gate oxide film 2 via an interelectrode insulating film 4 made of a silicon oxide film and an HTO film. The photodiode section 30 is formed of an n-type impurity region 31 that forms a pn junction with the p-well 12 and a high-concentration p-type impurity region 32 formed on the surface of the n-type impurity region 31.

  An antireflection film 6 made of a silicon nitride film with a thickness of 30 nm is formed on the first layer electrode 3a and the second layer electrode 3b so as to cover the surface of the photodiode portion with a silicon oxide film 5 interposed therebetween. Yes. The upper layer is formed with a tungsten thin film having a thickness of 200 nm as the light shielding layer 7 through a titanium nitride layer (not shown) having a thickness of 50 nm formed by sputtering. Further, this upper layer is covered with a planarizing film 10 of a translucent film made of the silicon oxide film 8 and the BPSG film. The gate oxide film 2 has a three-layer structure of a bottom oxide film 2a, a silicon nitride film 2b, and a top oxide film 2c.

  As described above, the color filter 50, the planarizing film 70, and the microlens 60 are sequentially stacked above the solid-state imaging device via the planarizing film 10 made of the BPSG film.

  Next, the manufacturing process of this solid-state imaging device will be described with reference to FIGS. In this example, an n-type impurity region 31, a p-type impurity (diffusion) region 32 for forming a photodiode region, and an n-type impurity region as a transfer channel 14 are sequentially formed by ion implantation, and then a gate oxide film and a gate electrode are formed. Form. In the following steps, the photodiode region and the transfer channel formed in the semiconductor substrate are omitted for simplification. In the drawing, the left side shows an image pickup unit (pixel unit), and the right side shows a pad portion on the periphery of the chip. An insulating film 1S made of a silicon oxide film for element isolation is formed on the pad portion.

  First, in the imaging unit, the gate oxide film 2 is formed on the surface of the n-type silicon substrate 1. As the gate oxide film, a silicon oxide film 2a having a thickness of 25 nm is formed by thermal oxidation, a silicon nitride film 2b having a thickness of 50 nm is formed by a CVD method, and a top oxide film 2c is further formed by a CVD method by a thickness of 8 nm. The silicon oxide film is formed to form a three-layer structure.

Subsequently, a doped amorphous silicon layer for forming the first layer electrode 3 a is formed on the gate oxide film 2.
That is, a phosphorous-doped first-layer doped amorphous silicon film having a thickness of 0.4 μm is formed on the gate oxide film 2 by a low pressure CVD method using SiH ₄ added with PH ₃ and N ₂ as a reactive gas. Form. The substrate temperature at this time shall be 600-700 degreeC. Then, patterning is performed by photolithography to form the first layer electrode 3a and the first layer pad 3ap (FIG. 6A). At this time, the first layer doped amorphous silicon film is selectively formed by reactive ion etching using a mixed gas of HBr and O ₂ with the mask pattern as a mask and the silicon nitride film 2b of the gate oxide film 2 as an etching stopper. Then, the first electrode 3a, the wiring of the peripheral circuit, and the first layer pad 3ap are formed. Here, it is desirable to use an etching apparatus such as an ECR (Electron Cyclotron Resonance) system or an ICP (Inductively Coupled Plasma) system.

Then, after the interelectrode insulating film 4 is formed by thermal oxidation over the entire substrate surface including the first layer electrode 3a and the first layer pad 3ap, PH ₃ and the like are formed in the same manner as the first layer doped amorphous silicon film. A 0.4 μm-thick phosphorus-doped second layer doped amorphous silicon film is formed by a low pressure CVD method using SiH ₄ added with N ₂ as a reactive gas, and patterned by photolithography to form a first layer. The second layer electrode 3b is formed, and the second layer pad 3bp is formed. The second layer pad is formed so as to have irregularities on the surface at intervals of 2 μm to 10 μm. Further, an insulating film 5 made of silicon oxide is formed on the surface of the second layer electrode by thermal oxidation (FIG. 6B). At this time, an insulating film is also formed on the surface of the second layer pad 3bp.

  6A to 6D showing process diagrams, the photodiode region is not shown, but a silicon nitride film is formed as an antireflection film 6 on the upper layer, and is patterned so as to cover the photodiode region. . Further, a TEOS film (6, 6S: see FIG. 2) is formed, a tungsten film as a light shielding film 7 is formed through TiN (not shown) as an adhesive layer, and the light shielding film 7 is formed using a resist pattern as a mask. After patterning, a silicon oxide film 8 having a thickness of 100 nm and a BPSG film having a thickness of 200 to 700 nm are formed by a CVD method, and reflowed and planarized at 850 ° C. to obtain a planarizing film 10 (FIG. 6C). ). At this time, the peripheral circuit portion is removed in this embodiment, but the light shielding film 7 may be left as a small pattern in the peripheral circuit portion and formed as a second layer pad. In this case, the first layer pad is formed of the first layer conductive film or the second layer conductive film. (Described later in Embodiment 2)

The silicon oxide film thus formed is patterned by photolithography to form a contact (FIG. 6D).
Then, an aluminum layer having a thickness of about 500 nm is formed by sputtering and patterned to form the metal pad 9p together with the wiring layer, and the pad portion as shown in FIG. 5 is formed.

  Finally, the filter layer 50, the flattening layer 70, and the lens 60 are formed, and the solid-state imaging device whose sectional view is shown in FIG. 2 is formed.

  Then, it is mounted on a mounting substrate (not shown), sealed with a cover glass, and in the wire bonding step, as shown in FIG. 1, the bonding wire Bw is fused to the pad portion.

  According to this configuration, the first layer pad 3ap that is formed in the same process as the first layer electrode and has a flat surface, and the second layer electrode that is formed in the same process as the second layer electrode and has a pattern shape having irregularities on the surface. Since the pad portion is composed of a layer pad 3bp and a bonding metal pad which is formed in the same process as the aluminum wiring layer and reflects the unevenness on the second layer pad and has an unevenness on the surface, There is no probe in the inspection process, and there are irregularities on the front and back surfaces of the metal pad, so that not only bonding with the bonding wire but also bonding with the ground is strong and has good electrical contact. Therefore, highly reliable mounting is possible even when downsizing. In this structure, the insulating film 4 is interposed between the first layer pad 3ap and the second layer pad 3bp. However, the insulating film 4 is electrically connected via the metal pad 9p covering the upper layer, and is divided. There is no problem in electrical contact because it is a small pattern region.

  In particular, since it has a laminated structure of an amorphous silicon layer and an aluminum layer, even when the temperature is high during bonding, the permeation of aluminum is stopped by amorphous silicon which is an inorganic film, and good contact can be maintained. In addition, since it can be formed without increasing the number of steps only by changing the mask pattern in photolithography, the productivity is good.

  In addition, the size of the interval between these small patterns is not particularly limited, but depending on the film thickness of the aluminum layer formed on the upper layer, it may be formed at a pitch that can reflect irregularities on the surface. desirable. Further, the pattern may not be a completely independent pattern as long as it can reflect the unevenness of the base surface.

(Embodiment 2)
Next, a second embodiment of the present invention will be described.
As shown in FIG. 2, in this solid-state imaging device, the pad portion is made of doped amorphous silicon as the second layer conductive film, the surface is flat, and the second layer pad 3bp1 is in an electrically floating state. On the second layer pad 3bp1, the second layer pad 7p is formed of a tungsten layer as a light-shielding film and has a pattern shape with irregularities on the surface, and the irregularities are reflected on the surface by reflecting the irregularities on the second layer pad 7p. And a bonding metal pad 9p having unevenness.

  Since the surface of the metal pad 9 is uneven, the connection with the bonding wire Bw is strong, and the base is a second-layer conductive film that forms the second-layer electrode in the imaging unit. Metal composed of an aluminum layer formed in the same process as the wiring layer connecting the imaging unit and the peripheral circuit unit on the laminated structure of the doped amorphous silicon and the tungsten layer constituting the light shielding film 7 in the imaging unit A pad is formed, and there is no risk of the probe slipping during probe inspection.

  Note that the conductive film constituting the first layer electrode and the second layer electrode is not limited to amorphous silicon, and may be appropriately changed such as a polycrystalline silicon layer or a microcrystalline silicon layer. Further, the metal constituting the silicide is not limited to tungsten, but may be appropriately changed such as titanium (Ti), cobalt (Co), nickel (Ni).

  In the above embodiment, the case where the charge transfer electrode having the two-layer electrode structure is used is described. However, when the charge transfer electrode having the single-layer electrode structure is formed by the flattening process after forming the conductive film having the two-layer structure. It goes without saying that is also applicable.

  Furthermore, although the solid-state imaging device has been described in the above embodiment, it is needless to say that the present invention can also be applied to a normal semiconductor device.

  As described above, according to the present invention, the pad portion is formed on the first layer pad having a flat surface, the second layer pad having a pattern shape having irregularities on the surface, and the second layer pad on the second layer pad. Reflecting the unevenness, the pad part is composed of a bonding metal pad with unevenness on the surface, so the probe does not pass through in the inspection process and the bonding property is extremely good, so it is fine and reliable Therefore, it is effective for forming a fine and highly sensitive solid-state imaging device such as a small camera.

It is principal part sectional drawing which shows the bonding state of the solid-state image sensor of Embodiment 1 of this invention. It is sectional drawing which shows the solid-state image sensor of Embodiment 1 of this invention. It is a principal part top view which shows the solid-state image sensor of Embodiment 1 of this invention. It is a top view of the solid-state image sensor of Embodiment 1 of this invention. FIG. 3 is a correspondence diagram between an imaging unit and a peripheral circuit unit of the solid-state imaging device according to the first embodiment of the present invention. It is a figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. It is principal part explanatory drawing which shows the solid-state image sensor of Embodiment 2 of this invention. It is a figure which shows the pad part of the semiconductor device of a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Gate oxide film 3a 1st layer conductive film 3b 2nd layer conductive film 3ap 1st layer pad 3bp 2nd layer pad 3bp1 1st layer pad 5 Insulating film 6 Insulating film 7 Light-shielding film 7p 2nd layer pad
8 Insulating film 9p Metal pad

Claims (16)

A semiconductor device having a pad portion for external connection,
The pad portion is composed of a first layer pad made of a first layer conductive film and a flat surface, and a second layer conductive film, and has a pattern shape having irregularities on the surface on the first layer pad. A semiconductor device comprising: a two-layer pad; and a bonding metal pad having irregularities on the surface reflecting the irregularities on the second layer pad. The semiconductor device according to claim 1,
The semiconductor device in which the first layer pad is in an electrically floating state. The semiconductor device according to claim 1, wherein
The semiconductor device includes, on the surface of a silicon substrate, a photoelectric conversion unit, a charge transfer unit including a charge transfer electrode that transfers charges generated in the photoelectric conversion unit, and a wiring layer connected to the silicon substrate. In a solid-state imaging device having a wiring portion,
A semiconductor device in which the charge transfer electrode includes a first layer electrode made of a first layer conductive film and a second layer electrode made of a second layer conductive film. The semiconductor device according to claim 2,
The first layer pad is a semiconductor device formed by the same process as the first layer electrode, and the second layer pad is formed by the same process as the second layer electrode. The semiconductor device according to claim 2,
The first layer pad is the first layer electrode, and the second layer pad is a semiconductor device formed in the same process as the light shielding film. The semiconductor device according to claim 2,
The first layer pad is a semiconductor device formed by the same process as the second layer electrode, and the second layer pad is formed by the same process as the light shielding film. A semiconductor device according to claim 1,
The semiconductor device in which the first layer conductive film and the second layer conductive film are polycrystalline silicon. A semiconductor device according to any one of claims 2 to 6,
The metal pad is a semiconductor device formed in the same process as the wiring layer. A method of manufacturing a semiconductor device having a pad portion for external connection,
Forming an element region on a semiconductor substrate surface;
A first layer conductive film is formed on the surface of the semiconductor substrate, a first layer electrode wiring is formed on the element region, and a first layer pad is formed on a peripheral portion. Patterning
Forming a first interlayer insulating film;
A second layer conductive film is formed on the first interlayer insulating film, a second layer electrode wiring is formed on the element region, and a second pattern having a small pattern with a desired pitch at least on the periphery. Patterning the second layer conductive film to form a layer pad;
Forming a second interlayer insulating film;
Forming a metal film on the second layer pad of the pad portion so as to reflect the shape of the small pattern, and forming a metal pad having irregularities on the surface thereof by patterning. A method of manufacturing a semiconductor device according to claim 9,
The method of manufacturing a semiconductor device, wherein the first layer pad is patterned to be in an electrically floating state. It is a manufacturing method of the semiconductor device according to claim 9 or 10,
The semiconductor device includes, on the surface of a silicon substrate, a photoelectric conversion unit, a charge transfer unit including a charge transfer electrode that transfers charges generated in the photoelectric conversion unit, and a wiring layer connected to the silicon substrate. A solid-state imaging device comprising a wiring portion,
A method of manufacturing a semiconductor device, comprising: forming the charge transfer electrode by a first layer electrode made of a first layer conductive film and a second layer electrode made of a second layer conductive film. A method of manufacturing a semiconductor device according to claim 9,
The method of manufacturing a semiconductor device, wherein the first layer pad is formed in the same step as the first layer electrode, and the second layer pad is formed in the same step as the second layer electrode. A method of manufacturing a semiconductor device according to claim 9,
The method of manufacturing a semiconductor device, wherein the first layer pad is formed in the same step as the first layer electrode, and the second layer pad is formed in the same step as the light shielding film. A method of manufacturing a semiconductor device according to claim 9,
The semiconductor device manufacturing method, wherein the first layer pad is formed in the same step as the second layer electrode, and the second layer pad is formed in the same step as the light shielding film. A method of manufacturing a semiconductor device according to claim 9,
The method for manufacturing a semiconductor device, wherein the first layer conductive film and the second layer conductive film are polycrystalline silicon. A method for manufacturing a semiconductor device according to claim 11, comprising:
The step of forming the metal pad is a method for manufacturing a semiconductor device, which is performed in the step of forming the wiring layer.

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