JP2006293641A - Register setting value monitoring module, system, and register setting value monitoring method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a register setting value monitoring module which can find an error in a register setting value in an early stage in software development. <P>SOLUTION: A register checking module 4 has a control register group 22, which stores expected values of setting values for control registers in function blocks 6, 7 and 8, and a comparison circuit 23 which compares the setting values, which are set to the control registers in the function blocks 6, 7 and 8 by a CPU, with the expected values stored in the control register group 22. The register checking module 4 outputs a notification of errors to a CPU 2 when the result of the comparison made by the comparison circuit 23 indicates that the setting values set to the control register group 22 are not in agreement with the expected values stored in the control register group 22. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a register set value monitoring module, a system, and a register set value monitoring method for monitoring a set value set for a control register of a functional block by a central processing unit.

  Many of the causes of problems that occur in the actual machine test environment at the start-up are incorrect setting values for the control registers in the function block. There are a plurality of types of setting value errors, but there are the following types.

(1) Careless mistakes in coding that set a set value that exceeds the limit described in the module specifications (2) When there is a set value limit among multiple modules and adjustment of the set value is required (3) Module alone When the difference between the specification and the module specification when the module is incorporated into the system is overlooked Here, for the item (2), when signals are exchanged between a plurality of functional modules, There are often specification restrictions between modules. In addition, when the specification restriction is caused by an event specific to hardware implementation, the specification restriction becomes even more difficult for software personnel.

  The cause of the item (3) is largely related to “reuse of design assets” which is taken up as an effective means for shortening the ASIC development period in recent years. When a function module having a general-purpose function is mounted on the ASIC so that it can be reused in the future, the function module has a function that is not normally required, that is, a redundant function, from the viewpoint of the system.

  Here, a versatile DMAC (DMA controller) (for example, Patent Document 1) will be described in consideration of reusability. There is a general-purpose DMAC that supports both the direction of DMA from an IO device (input / output device) to external memory and the direction of DMA from external memory to IO device. This DMAC statically sets the DMA direction with a specific register. The specification can be switched. If the IO device connected to the DMAC supports bi-directional, the register is switched according to the access direction. On the other hand, when the general-purpose DMAC is connected to an IO device that supports only one direction, the value of the DMA direction switching register should always be constant. However, as long as the general-purpose DMAC is used, the direction switching register can be freely accessed, so the software may erroneously rewrite the value of the direction switching register, which causes a problem.

  Conventionally, in order to find such a malfunction in the actual machine environment, the designer specifies the module from the phenomenon that has occurred in the actual machine, and in the specification document whether there is a setting error in software coding in the identified module. Check according to the above, or check the specifications by exchanging with the hardware designer.

In addition, the module is provided with a function to determine whether or not the setting restrictions are observed, as hardware, and when it is determined that the setting restrictions are not observed by this function, an interrupt notification or bus error processing is performed. There is a way to do it.
JP 2002-342259 A

  However, in the above-described conventional method for identifying a module from a problem that has occurred in a real machine environment, if there is a problem with the setting of the first identified module, usually, a lot of time is not spent on correcting the problem. However, when the setting error is caused by the setting of another module, a lot of time is spent on finding and correcting the defect. For example, this is the case when there is an error in the restriction on the frequency of the clock signal generated by the clock generation block.

  In addition, the method of using a function for determining whether or not the setting restrictions provided in a module are used is applicable to restrictions that can be completed by the module, but exists in a system configuration exceeding the module level. It is not possible to adapt to the constraints.

  In addition, when the cause of a failure is caused by a hardware bug, the software workaround is often applied to avoid the failure. In this case, it is necessary to check whether the software workaround is correctly performed and the prohibited setting is not repeated.

  An object of the present invention is to provide a register setting value monitoring module, a system, and a register setting value monitoring method capable of finding a register setting value error in an early stage of software development.

  In order to achieve the above object, the present invention provides a register setting expected value storage means for storing an expected value for a setting value of a control register of a functional block, a setting value set for the control register by a central processing unit, Comparison means for comparing the expected value stored in the register setting expected value storage means, and the comparison result by the comparison means is stored in the setting value set for the control register and the register setting expected value storage means When a mismatch with the expected value is indicated, an error notification means for outputting an error notification to the central processing unit is provided.

  In order to achieve the above object, the present invention provides a system comprising the register set value monitoring module.

  In order to achieve the above object, the present invention provides a set value set for the control register of the functional block by the central processing unit and an expectation for the set value of the control register stored in the register set expected value storage means. A comparison step for comparing values, and a comparison result in the comparison step indicates a mismatch between a set value set for the control register and an expected value stored in the register setting expected value storage means; And a register setting value monitoring method comprising: an error notification step of outputting an error notification to the central processing unit.

  According to the present invention, it is possible to find an error in a register setting value at an early stage of software development.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a system configuration including a register check module (register set value monitoring module) according to the first embodiment of the present invention.

  As shown in FIG. 1, the system is provided with a CPU 2 as one of the bus masters. The CPU 2 controls the control registers (not shown) in the function modules 6, 7, and 8 via the system bus 1. Register settings for. Access to the control registers of the function modules 6, 7, and 8 is performed via the slave I / F 5 that collectively controls the function modules 6, 7, and 8. The slave I / F 5 decodes the bus address from the bus master (including the CPU 2), and if it is an address assigned to each functional module, transmits an access start signal to the functional module and writes the register address and the address. Send data. These signals 13, 14, 15, 16 are once received by the register check module 4, and then transmitted to the function modules 6, 7, 8 as signals 10, 11, 12.

  One of the signals 13, 14, 15 and 16 is a signal dedicated to access to the control register in the register check module 4. The protocols of the signals 10 to 16 are all common, and when the register check module 4 is not mounted, the slave I / F 5 and the function modules 6, 7, and 8 can be directly connected. Receiving the access start signal, the functional modules 6, 7, and 8 decode the address and write to the accessed register. When the writing is completed, the register check module 4 transmits an access end signal to the slave I / F 5, and the slave I / F 5 returns ready to the system bus 1 in response to the access end signal and completes the bus transaction. To do.

  Although register write access has been described here, the same applies to read access. Specifically, in the case of read access, read data is transmitted from each functional module to the slave I / F 5 via the register check module 4 simultaneously with the access end signal, and is transmitted to the read data bus of the system bus 1 via the selector. The This completes the bus transaction.

  Next, the configuration of the register check module 4 will be described with reference to FIGS. FIG. 2 is a block diagram showing an internal configuration of the register check module of FIG. 1, and FIG. 3 is a diagram showing control registers included in the control register group 22 of FIG. 2 and respective data formats.

  As shown in FIG. 2, the register check module 4 includes a register I / F 21, a control register group 22, a comparison circuit 23, a comparison result processing circuit 24, and a peripheral I / F 25. The control register group 22 includes a plurality of control registers (not shown) in the same manner as the function modules 6, 7, and 8 that are peripherals (peripheral devices), and each control register can be accessed from the CPU 2. It is. The register I / F 21 performs access control from the CPU 2 to each control register in the control register group 22.

  As shown in FIG. 3, each control register in the control register group 22 includes a comparison enable register 221, an interrupt enable register 222, a mismatch write enable register 223, a history enable register 224, a status register 225, a comparison target address register 226, Nine types of registers are prepared: comparison mode register 227, expected value registers 228 and 229, and comparison result history registers (here, address history register 230 and data history register 231). These registers are all 32-bit registers.

  Here, the comparison enable register 221, the interrupt enable register 222, the mismatch write enable register 223, the history enable register 224, and the status register 225 exist as one set, but the comparison target address register 226, the comparison mode register 227, the expected value The registers 228 and 229 exist as a plurality of sets. As many sets as the number of IO (input / output) registers to be checked are prepared. The comparison result history registers (address history register 230 and data history register 231) also exist as a plurality of sets, and the number of sets is required by the number of types of data to be left as history.

  The comparison enable register 221 is assigned to the register address “address 0x0000”, and is a register for selecting whether or not to execute the comparison sequence. When this register value is 0, the comparison sequence is not executed and is skipped, and the control registers of the function modules 6, 7, and 8 are accessed as usual. This register 221 is for disabling the entire comparison function, and the comparison enable field in the comparison mode register 227 assigned to the register address “0x0100 + 0x10 * i + 0x4” is Different. This will be described in detail in the description of the comparison mode register 227.

  The interrupt enable register 222 is assigned to the register address “address 0x0004”, and is a register for selecting whether or not to perform interrupt notification. This register 222 disables the interrupt signal at the last stage of the module, and is different from the interrupt enable field in the comparison mode register 227. This will be described in detail in the description of the comparison mode register 227.

  The mismatch write enable register 223 is assigned to the register address “0x0008”, and is a register for selecting whether to write to the control register or cancel when a comparison mismatch occurs. This register 223 is for masking register writing at the last stage of the module, and is different from the mismatch writing field in the comparison mode register 227. This will be described in detail in the description of the comparison mode register 227.

  The history enable register 224 is assigned to the register address “0x000C address”, and whether or not to leave a history for the comparison result history registers (the address history register 230 and the data history register 231) when a comparison mismatch occurs. Is a register for selecting. This register 224 is a function for masking the history function at the last stage of the module, and is different from the history enable field in the comparison mode register 227. This will be described in detail in the description of the comparison mode register 227.

  The status register 225 is assigned to the register address “address 0x0010” and has a status flag field, an error count field, and a history number field. In the status flag field, a predetermined value is set when a mismatch occurs in the comparison result and the interrupt field of the cause of the mismatch is 1. This predetermined value does not depend on the value of the interrupt enable register 222. An interrupt signal to the CPU 2 is generated when the AND condition of the status field and the interrupt enable register is satisfied. To clear the interrupt factor, 0 can be written in the status field. The error count field is a field for recording the number of comparison mismatches, and does not depend on whether or not the interrupt is set to be valid, and the number is incremented every time a mismatch occurs. This error count field can be cleared to zero. The history number field is a field indicating the number stored in the comparison result history register (the address history register 230 and the data history register 231). The value of the history number field is incremented at the same time as the history is written to the comparison result history register when a comparison mismatch occurs for the comparison target set to leave a history. This field can also be cleared to zero. However, all non-zero writes in all fields of the status register 225 are invalid.

  The comparison target address register 226 is assigned to a register address “0x0100 + 0x10 * i + 0x0”, and is a register for setting a control register address of a module that performs expected value comparison. Here, i in the register address indicates the number of control registers to be compared.

  The comparison mode register 227 is assigned to the register address “0x0100 + 0x10 * i + 0x4”, and has five types of register fields. Each register field includes a comparison enable field, a comparison mode field, an interrupt enable field, a mismatch write field, and a history enable field.

  The comparison enable field is a field for determining whether to enable the comparison function. Unlike the comparison enable register 221, this field is a field for individually setting enable of the control register to be compared.

  The comparison mode field is a field for setting the type of comparison mode. As a comparison mode, a mode for comparing with simple immediate data, a mode for comparing a specific bit field with a mask pattern, a range is determined from two expected value registers, and whether or not the register write data is within the range is determined. There are modes for checking and modes for comparing with other control register values.

  In the present embodiment, the following types of comparison modes are supported, and these comparison modes can be implemented.

Comparison mode field = 0x0 → immediate comparison Comparison mode field = 0x1 → specific bit field comparison: expected value = 0
Comparison mode field = 0x2 → Specific bit field comparison: Expected value = 1
Comparison mode field = 0x3 → range comparison (expected value A <comparison target <expected value B)
Comparison mode field = 0x4 → Comparison of other registers Here, a typical use example of the supported comparison mode will be briefly described.

  The immediate comparison mode is used when there is a function that is supported by a single module, but the system in which the module is mounted cannot use the function. For example, the module A is a timer, and in order to select a method of starting the timer, which method to use is selected from a starting method by register setting and a starting method by detecting an external trigger signal. It is assumed that a selection register is provided. Here, the module A has a port for inputting an external trigger signal, so that the module alone supports activation by the external trigger signal. However, in the system equipped with the module A, only software activation is performed, and the external trigger input is clamped in the upper layer. In this case, the selection register itself can of course be accessed, but even if hardware activation is enabled, it cannot be used because it does not have that means. Therefore, the immediate comparison mode is effective for detecting an illegal setting value in such a case.

  The specific bit field comparison mode can perform a specific bit unit check finer than the immediate comparison, and is a very effective mode particularly when a plurality of setting fields are included in one control register. For example, a mode setting register of a certain DMAC has an access direction field, a burst transfer mode field, a burst length field, and the like. Furthermore, the DMAC is designed for general use, and supports both DMA from an external memory to an IO device and DMA from an IO device to an external memory, and the switching can be performed using an access direction field. it can. However, in a system in which an IO device connected to the DMAC supports only one direction, the access direction field should be fixed. This “fixed” cannot be sufficiently checked in the immediate comparison mode. This is because the immediate comparison mode cannot cope with a case where only a specific field in the same register is checked. In the specific bit field comparison mode, the bit field of the expected value register for the bit corresponding to the access direction field is set to 1, and the other fields are not checked, so the other fields may be set to 0. For the check value for the bit field to be checked, 0 or 1 may be selected in comparison mode 1 or 2.

  The range comparison mode will be described by taking as an example a type in which a transfer area for a DMAC memory is given by a start address and an end address. Here, in the DMAC specification, both addresses are given as 32-bit addresses. However, there is a case where a 64-MBit DRAM is placed from address 0 on the actual system, and it is necessary to perform DMA transfer only in this space. . In this case, the end address should be less than 0x100_0000. Placing this value in the two expected value registers 228 and 229 makes it possible to find an illegal setting value.

  The other register comparison mode is used when the serial I / O connected to the DMAC performs serial transfer with the external serial interface and performs transfer with the external memory using the DMA. In this case, there is a register for setting the number of frames in the serial I / O, and a register for setting the DMA transfer length is also installed in the DMAC. There may be a restriction that the DMA transfer length is the same due to system restrictions and serial I / O specifications. When checking such a restriction, if the address of one control register is designated in the expected value registers 228 and 229, a comparison can be made with a register matching that address.

  The interrupt enable field can be an interrupt factor only when its value is 1. Unlike the interrupt enable register 222, the interrupt enable field is used to individually enable the control registers to be compared.

  The non-matching write field is used to determine whether to write to the functional module or cancel when the expected value comparison result does not match. Unlike the mismatch write enable register 223, the mismatch write field is used to individually enable the control registers to be compared.

  In the history enable field, only when the value is 1, the function of leaving a history when the expected value does not match is effective. Unlike the history enable register 224, this history enable field is used to individually enable the control registers to be compared.

  The expected value registers 228 and 229 are assigned to register addresses “0x0100 + 0x10 * I + 0x08” and “0x0100 + 0x10 * I + 0x0C”, respectively, and are expected values to be compared with the write data for the comparison target address. This is a register for storing data. The expected value registers 228 and 229 not only store data to be compared like immediate data, but also set the register address of the comparison target register when the comparison mode is “comparison with other registers”. The two expected value registers exist in order to cope with the case where “range comparison” is selected in the comparison mode.

  The comparison result history register is a register group for storing a register address and data when the comparison result is NG. In this embodiment, the address history register 230 (register address: 0x1000 + 0x10 * j + 0x0) and data history register 231 (register address: 0x1000 + 0x10 * j + 0x4). When the comparison result history register is enabled and the history enable field in the comparison mode register 227 for the control register that caused the comparison mismatch is enabled, the history is stored in the comparison result history register. Each time this history is saved, the value in the history number field of the status register 225 is counted up.

  Among the above control registers, regarding the control registers 226 to 229 from the comparison target address register to the expected value register, there are hardware restrictions even after the completion of the ASIC, in addition to the registers for the number of comparison target control registers. It is preferable to provide an extra register in advance in consideration of the addition.

  As shown in FIG. 2, the comparison circuit 23 compares the register write data sent from the slave I / F 5 (FIG. 1) with a certain expected value in the control register group 22 in a corresponding comparison mode, and the comparison result To the comparison result processing circuit 24. When the comparison mode is “comparison with other control register”, the register check module 4 itself needs to perform read access to the control register in the peripheral device. Notify F25. As a result, the peripheral I / F 25 performs read access to the control register in the peripheral device, and returns register read data to the comparison circuit 23. Then, the comparison circuit 23 compares the write data from the slave I / F 5 with the read data returned from the peripheral I / F 25. The comparison result is passed to the comparison result processing circuit as in the other modes.

  Based on the comparison result, the comparison result processing circuit 24 performs processing control to execute access to each functional module, to perform an interrupt notification when the comparison result is NG, or to leave a history.

  When the peripheral I / F 25 causes a comparison mismatch and the mismatch write field of the comparison mode register is “disabled”, the peripheral I / F 25 masks the access start signal from the slave I / F 5 and cancels the access. On the other hand, in the case of access to a control register that is not a comparison target, if the comparison result matches, or the mismatch write field is “enabled”, the peripheral I / F 25 masks the register access start signal from the slave I / F 5. It outputs as it is without. However, the mask of the register access start signal needs to be managed by a state machine because it takes a plurality of cycles from receiving the access start signal from the slave I / F 25 to completing the comparison process. In particular, when comparing with other control registers, a comparison period of a plurality of cycles is surely required.

  Next, a procedure in the present embodiment from register access to comparison processing to completion of register access will be described with reference to FIGS. 4 and 5. FIG. 4 and 5 are flowcharts showing the procedure from the execution of register access to the completion of register access through comparison processing in the system of FIG. The flowcharts shown in FIGS. 4 and 5 are described separately for each of the CPU 2, the slave I / F 5, the register check module 4, and the peripheral (functional block).

  As shown in FIG. 4, when the CPU 2 starts to access the register a0 (not shown) of the peripheral (functional module 6, 7, or 8) (step S1), the slave I / F 5 receives the register access start signal. Is asserted (step S2). In the same cycle, the register address and the register write data become valid. The register check module 4 receives the register address and the register write data, and first checks the value of the comparison enable register 2211 (step S3). Then, the register check module 4 determines whether or not the result of the check is enabled (Step S4).

  If it is determined in step S4 that the result of the check is disabled, the register comparison function is not required in the later stage of software development. When disabled, the register check module 4 outputs an access start signal, an address, and write data to the peripheral control register as shown in FIG. 5 (step S18).

  The peripheral (functional module) receives the access start signal, the address, and the write data, writes the corresponding register a0 (step S20), and outputs the access completion signal to the register check module 4 when the write ends. (Step S21).

  The register check module 4 receives the access completion signal and outputs an access completion signal to the slave I / F 5 (step S30), and the slave I / F 5 returns a ready signal to the system bus 1 (step S31), Release, that is, terminate the process (step S32).

  On the other hand, when it is determined that the comparison enable register 221 is enabled (step S4), the register check module 4 determines whether the address from the slave I / F 5 matches the address of the comparison target register. (Step S5). If there is no matching address in the comparison target address register 226, normal register access is performed in the same manner as when the comparison enable register 221 is disabled (steps S1-> S2-> S3-> S4->). S5-> S6-> S8-> S18-> S20-> S21-> S30-> S31-> S32). In the present embodiment, there is provided a state (step S8) for checking whether or not all the comparison target control register addresses have been checked, but this compares all the target addresses within one cycle. This state is not necessary when possible hardware is implemented.

  On the other hand, when it is determined in step S6 that the address corresponding to the register address is in the comparison target address register 226, the register check module 4 compares the comparison enable in the comparison mode register 226 corresponding to the comparison target register address. The field is checked (step S7). Then, the register check module 4 determines whether or not the result of the check is enabled (Step 9). Here, if the result of the check is disabled, normal register access (S18 → S20 → S21 →,... → S32) is performed.

  If it is determined in step S9 that the comparison enable field is enabled, the register check module 4 checks the value of the comparison mode field in the comparison mode register 227 (step S10), and determines the set comparison mode. (Step S11).

  If the comparison mode determined in step S11 is the immediate comparison mode, the register check module 4 simply compares the write data with the value stored in the expected value register 228 (step S12).

  When the comparison mode determined in step S11 is the specific bit field comparison mode, the register check module 4 uses the bit “1” in the bit pattern to be compared of 32 bits stored in the expected value register 228. A check is performed only for (step S13). Here, the expected comparison value is 0 when the comparison mode is 1 and 1 when the comparison mode is 2.

  When the comparison mode determined in step S11 is the range comparison mode, the register check module 4 refers to the lower limit expected value and the upper limit expected value stored in the expected value registers 228 and 229, respectively, and the write data is lower limit. It is checked whether it is between the expected value and the upper limit expected value (step S14).

  When the comparison mode determined in step S11 is the other register comparison mode (step S15), the register check module 4 first uses the data stored in the expected value register 228 as a register address, and actually uses each function module 6 , 7 and 8 are read-accessed (step S15). Therefore, an equivalent of the address decoder in the slave I / F 5 is also present in the register check module 4, and a register access start signal is generated by this address decoder circuit. Then, the peripheral (functional block) returns the corresponding register data to the register check module 4 (step S16). The register check module 4 compares the data returned from the peripheral with the write data from the CPU 2 (step S17).

  When the processing in the set comparison mode is completed, the register check module 4 evaluates the comparison result by the comparison result processing circuit 24 as shown in FIG. Here, three types of processing are performed simultaneously. The comparison result processing circuit 24 first checks the history enable register 224 and the history enable field in the comparison mode register 227 (step S22), and determines whether or not the result of the check is enabled (step S23). . If the result of the check is enabled, the register check module 4 saves the register address and write data in the address history register 230 and the data history register 231 which are comparison result history registers, respectively (step S24). When the history enable field is 0, although not shown, the comparison result processing circuit 24 does not perform anything and ends this processing.

  At the same time, the comparison result processing circuit 24 checks the interrupt enable register 222 and the interrupt enable field in the comparison mode register 227 corresponding to the control register address that caused the comparison mismatch (step S25). Based on this, it is determined whether or not both are enabled (step S26). If both the interrupt enable register 222 and the corresponding interrupt enable field are enabled, the comparison result processing circuit 24 sets the status flag of the status register 225 and further asserts an interrupt signal (step S27).

  If only the interrupt field of the interrupt mode register 222 is enabled, the status field of the status register 225 is set to 1. However, the interrupt signal is not asserted because the interrupt enable register 222 is disabled. Then, the comparison result processing circuit 24 ends this process.

  At the same time, the comparison result processing circuit 24 checks the mismatch write enable register 223 and the mismatch write field in the comparison mode register 227 corresponding to the comparison target register address that caused the mismatch (step S28), and both are enabled. Whether or not (step S29). If both are enabled, the comparison result processing circuit 24 starts register access to a normal peripheral (step S18). The subsequent procedure is the same as that for normal register access.

  If it is determined in step S29 that the mismatched write field is disabled, the register check module 4 passes an access completion signal to the slave I / F 5 without accessing the peripheral (step S30). Then, the slave I / F 5 returns a ready signal to the system bus 1 (step S31), releases the bus, that is, ends the processing (step S32).

  As described above, according to the present embodiment, it is possible to find an error in the register setting value at an early stage of software development.

  In addition, the expected value is immediate data, a specific bit field, a value given by at least an upper limit expected value and a lower limit expected value, and / or a setting value of another control register, thereby comparing with simple immediate data. A mode in which a specific bit field is compared with a mask pattern, a mode in which a range is determined from two expected value registers, and whether or not the register write data is within the range, and a comparison with other control register values It becomes possible to carry out the mode.

  In addition, register access is delayed during the comparison process, and if the comparison results do not match, the writing itself is canceled, thereby avoiding a fatal problem on the real machine caused by an incorrect setting. Depending on the hardware implementation means, this comparison function may slow down the IO access to the peripheral of the CPU 2 itself, but by providing a function for disabling this, a normal speed that is not low in the late stage of software development Access is guaranteed.

  Also, by leaving a history of comparison results, it is possible to confirm a history of inappropriate register settings in the interrupt handler.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS. 6 is a block diagram showing a configuration of a system including a register check module (register set value monitoring module) according to a second embodiment of the present invention, and FIG. 7 is a block diagram showing a configuration of the register check module of FIG. FIG. 8 is a diagram schematically showing each of the control registers provided in the SRAM of FIG. In the figure, the same blocks as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 6, the present embodiment is different from the first embodiment in that a register relating to a comparison mode, an expected value, and the like is provided in a general-purpose SRAM 103. Specifically, the general-purpose SRAM 103 is connected to the system bus 1 via the SRAM I / F 101 and the slave I / F 100 and can be accessed from each bus master including the CPU 2. This SRAM module has a connection path to the register check module 4 as well as a connection path to the slave I / F 100.

  When the register check module 4 reads expected value data including the comparison mode and other information, the register check module 4 sends a signal 105 to the SRAM 103 for access. The SRAM 103 is used for general purposes. In this case, the SRAM 103 is also accessed from the system bus 1. The above two accesses to the SRAM 103 are switched by the selector 102. The switching operation of the selector 102 is controlled by a switching signal 104 from the register check module 4.

  As shown in FIG. 7, the register check module 4 differs from the register check module 4 of the first embodiment in that it includes a control register group 122 in which an SRAM I / F 123 is provided. As in the first embodiment, the control register group 122 includes a comparison enable register, an interrupt enable register, a mismatch write register, a history enable register, and a status register. The control register group 122 includes a comparison target number register, a comparison target register address base address register, a comparison mode base address register, an expected value (A, B) base address register, an address history base address register, and data. A history base address register is newly added. All these registers are only one set.

  The SRAM 103 is provided with all of the comparison target address register, the comparison mode register, the expected value data register, the address history register, and the data history register, which are composed of a plurality of sets other than the above registers.

  In the newly added comparison target number register, a number for specifying at least one control register to be compared is set. This can be set as long as the capacity of the SRAM 103 is allowed. By specifying each base address register as an address in the SRAM 103, each set value (comparison target register address, comparison mode, expected value A, B) can be continuously arranged from an arbitrary address in the SRAM 103. To do. Similarly, the newly added history number register designates the size of the area to be secured in the SRAM 103 as the history area, and the address history base address register and the data history base address register are stored in the SRAM 103. By specifying the address, the history information can be continuously arranged in the SRAM 103.

  In FIG. 8, reference signs A, B,..., L in the figure are control register numbers to be compared, and here, 12 comparison target control registers are assumed. The comparison target number register is set to 0xC at this time. Here, if one more comparison target register (for example, control register of address 0xCC00_0024) is to be added, the comparison target number register is set to 0xD, and the address of (base address register for comparison target register address + 0xD * 4) on the SRAM 103 is set. Write 0xCC00_0024. Similarly, in the comparison mode, a desired mode may be set at the address (comparison mode base address register + 0xD * 4) on the SRAM 103. The other settings are the same.

  As for the history, a history area may be secured in the SRAM 103 using a history number register dedicated to history, an address history base address register, and a data history base address register. In FIG. 8, a, b,..., J are history numbers, and here, histories up to 10 comparison mismatches can be stored.

  In the present embodiment, the procedure from register access to comparison processing through register access is the same as in the first embodiment. However, since each comparison parameter is stored in the SRAM 103, it takes time to access the SRAM 103. In particular, when searching for a comparison target address that matches the register address from the slave I / F 5 (step S5 in FIG. 4), it is necessary to continuously access and check the area in the SRAM 103 where the comparison target register address is stored. Therefore, the greater the number of registers to be compared, the greater the number of repetitions of the search sequence (steps S5 → S6 → S8 → S5 → S6). Further, since it is necessary to access and read the expected value and the comparison mode to the SRAM 103, it may occupy the system 1 for a long time only by register access from the CPU 2 once. However, since the register set value check function is only used during software debugging, if the comparison enable register is disabled in the later stage of development, all comparison sequences are skipped, and a high-speed response can be realized.

  In the later stage of development, the SRAM 103 can be used for other general purposes other than register check. The switching signal 104 of the SRAM 103 normally instructs the selection of the SRAM I / F 101, and instructs the selection of the SRAM I / F 123 in the register check module 4 only when the comparison parameter is accessed. When the comparison parameter is read from the register check module 4 to the SRAM 103, the bus transaction of the system bus 1 is not closed, so that the access to the SRAM 103 is surely an exclusive access.

  Of the SRAM 103 area accessible to all bus masters including the CPU 2 as a slave, an area not used for actual product software can be used as the comparison parameter storage area. In this case, the comparison target number register and each base address register in the register check module 4 are designated so as not to exceed the area allowed for the comparison parameter storage area in the SRAM 103 area.

  Further, in the present embodiment, the register setting expected value storage means has been described as a register or SRAM 103 that can be rewritten by software, but it is naturally possible to implement this as a logically fixed value. However, it is possible to select a mounting method based on a trade-off between the degree of freedom and the circuit scale.

  Further, by using the SRAM 103, an expected value can be added or rewritten after the LSI is completed.

  Also, the SRAM 103 is implemented as a general-purpose slave device, each comparison parameter that can exist in a plurality of sets is moved into the SRAM 103, and only the minimum control registers are left in the register check module 4, whereby the register check module 4 itself The circuit scale can be minimized. In addition, since all the registers remaining in the register check module 4 do not depend on the number of comparison targets, it is possible to design with a high degree of freedom.

1 is a block diagram showing a system configuration including a register check module (register set value monitoring module) according to a first embodiment of the present invention. It is a block diagram which shows the internal structure of the register | resistor check module of FIG. It is a figure which shows each control register contained in the control register group 22 of FIG. 2, and each data format. 2 is a flowchart showing a procedure from execution of register access to completion of register access through comparison processing in the system of FIG. 2 is a flowchart showing a procedure from execution of register access to completion of register access through comparison processing in the system of FIG. It is a block diagram which shows the structure of the system containing the register check module (register set value monitoring module) which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the register | resistor check module of FIG. FIG. 7 is a diagram schematically showing each of control registers provided in the SRAM of FIG. 6.

Explanation of symbols

1 System bus 2 CPU
4 Register check module 5 Slave I / F
6, 7, 8 Function module 21 Register I / F
22 control register group 23 comparison circuit 24 comparison result processing circuit 25 peripheral I / F
102 selector 103 SRAM
123 SRAM I / F

Claims (14)

Register setting expected value storage means for storing an expected value for the setting value of the control register of the functional block;
Comparison means for comparing a set value set for the control register by the central processing unit with an expected value stored in the register setting expected value storage means;
If the comparison result by the comparison means indicates a mismatch between the set value set for the control register and the expected value stored in the register setting expected value storage means, an error notification is sent to the central processing unit. A register set value monitoring module comprising: an error notification means for outputting.   2. The register set value monitoring module according to claim 1, wherein the expected value stored in the register set expected value storage means is immediate data.   2. The register setting value monitoring module according to claim 1, wherein the expected value stored in the register setting expected value storage means is a specific bit field.   2. The register set value monitoring module according to claim 1, wherein the expected value stored in the register set expected value storage means is a value given by at least an upper limit expected value and a lower limit expected value.   2. The register set value monitoring module according to claim 1, wherein the expected value stored in the register set expected value storage means is a set value of another control register different from the control register to be compared.   During the period when the comparison is performed by the comparison unit, setting of a set value for the control register by the central processing unit is delayed, and when the comparison result by the comparison unit indicates a mismatch, the control register by the central processing unit 6. The register setting value monitoring module according to claim 1, further comprising a data write delay canceling unit that cancels setting of the setting value for.   The register set value monitoring module according to claim 1, further comprising a comparison invalidation unit that invalidates a comparison operation performed by the comparison unit. A comparison result history storage means for storing a comparison result by the comparison means;
Storage means for storing, in the comparison result history storage means, a set value set for the control register by the central processing unit and an address of the control register when the comparison result by the comparison means indicates a mismatch; 8. The register set value monitoring module according to claim 1, wherein   2. The register setting value monitoring module according to claim 1, wherein the expected value stored in the register setting expected value storage means is a fixed value.   The register set value monitoring module according to claim 1, wherein the register expected value storage unit includes a rewritable register or SRAM.   11. The register set value monitoring module according to claim 10, wherein the rewritable register or SRAM is a bus slave device provided outside the module and accessible from all bus masters including the central processing unit.   12. The register set value monitoring module according to claim 11, further comprising a specifying unit that specifies an unused storage area as the register expected value storage unit among the storage areas of the SRAM.   A system comprising the register set value monitoring module according to claim 1. A comparison step of comparing a set value set for the control register of the functional block by the central processing unit with an expected value for the set value of the control register stored in the register setting expected value storage means;
If the comparison result in the comparison step indicates a mismatch between the set value set for the control register and the expected value stored in the register set expected value storage means, an error notification is sent to the central processing unit. A register setting value monitoring method comprising: an error notification step of outputting

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