JP4015025B2 - MEMORY TEST METHOD, INFORMATION RECORDING MEDIUM, AND SEMICONDUCTOR INTEGRATED CIRCUIT - Google Patents

Description

Technical field
The present invention relates to an on-chip memory test technique in a semiconductor integrated circuit, for example, a technique effective when applied to a test method for a system LSI such as a data processing apparatus, a microprocessor, and a single chip microcomputer incorporating a memory.
Background art
With the development of microfabrication technology, it has become possible to mount a very large scale circuit on a semiconductor integrated circuit (LSI). Therefore, the capacity of memory circuits such as SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and flash memory mounted on a system LSI such as a single-chip microcomputer has been dramatically increased. These memory circuits are mounted at higher density than logic circuits such as CPU (Central Processing Unit), and circuits such as memory cells and sense amplifiers are analog circuits. Necessary. For this reason, a test mode that enables operation or control of an LSI as if it were a single memory IC (Integrated Circuits) is provided only during testing, and a test similar to a single memory IC is performed from an external tester. A method has been used. However, as the operating speed of the system LSI increases, there is a problem that a higher-function and expensive tester corresponding to both the logic IC and the memory IC becomes necessary, or the test time is extended because the test is divided into two paths. . Therefore, a memory BIST (Built-In Self Test) circuit that supports a test by generating a test pattern inside the chip has been provided.
As the memory BIST technology, as described in Japanese Patent Application Laid-Open No. 2000-30484, a sequencer for generating a test pattern and a data generation device for reading and writing are fixedly embedded as hardware in a chip, As described in Japanese Patent Application Publication No. 11-15740, a simple memory test processor is built in, a test program is supplied to the processor from the outside during the test, and the program is executed to generate a test pattern by software Etc. have been devised. However, in the former method, it is necessary to determine a test method at the time of design, and it is difficult to cope with various defective events in the memory. Recently, CPU cores are distributed as IP (Intellectual Property) module data and can be created by processes of various manufacturers. Therefore, it is a good idea that test patterns are fixed because various memory failure events are assumed. Not. The latter method is flexible because it can determine the test pattern at the actual test, not at the time of design, and it can be said that it is suitable for CPU core IP. However, a simple processor for testing other than the original CPU can be used. This requires a large amount of hardware resources and increases the chip area, which is problematic in terms of cost. Moreover, it is necessary for the test designer to write a test program in a special language, and it is not preferable if module data used by various users is assumed.
As a processor for executing a test program, there is a case where a CPU used during normal operation is used in addition to a test-dedicated processor. For example, as described in JP-A-10-511790, a test program is stored in a built-in memory. There is a method of placing a part of a kind of cache memory, causing the CPU to execute the test program, and testing the rest of the cache memory. If this method is used, the amount of hardware to be added for testing can be reduced, and there is an advantage that the manufacturing cost of the chip can be reduced. In addition, since the test program is not limited to a dedicated processor but may be provided for a CPU that is normally used, there is an advantage that the test program can be created in an assembly language familiar to the user.
However, the above-described conventional technique of executing a program by causing the CPU to execute a program performs the test of the remaining internal memory in a state where the test program is arranged in a part of the internal memory such as a cache memory, and therefore the following problems It has been found by the present inventors.
First, if memory access for instruction fetch and test competes on the bus connecting the CPU and the built-in memory, there is a possibility that a stall may occur with respect to CPU instruction execution, resulting in a decrease in test efficiency. It was. In addition, since the CPU determines whether the cache memory is good or bad, it is necessary for the CPU to execute an instruction for determining whether the data read from the cache memory matches the expected value. There is a problem that the ratio of instructions to be performed is reduced, and the test time is longer than that of the BIST technique using a dedicated test sequencer. In short, in addition to instruction execution for memory read access and write access for memory test, instruction execution for comparison and the like increase, and the memory test time increases relatively. Also, the memory test program is a program that executes certain operations such as memory read / write over the entire memory area by changing only the address, so it must be a loop type program. Instructions are required, and the ratio of read / write instructions also decreases in this respect. In a CPU without a branch prediction function, the branch instruction itself requires a plurality of execution cycles, so that the number of cycles required for the test increases more than the increase in the number of instructions. Furthermore, since the CPU cannot normally access multiple normal memories with different address mappings at the same time, when there are multiple test target memories, or when the memory is divided into multiple pages (multiple memory blocks) However, the test cannot be performed by accessing these memories in parallel, and there is a problem that the test must be performed sequentially and the test time becomes long.
For example, there is a technique called a 13N test as a memory test sequence. The 13N test is discussed in I.E.E. Design and Test of Computers February (1989), pages 26 to 34 (IEEE DESIGN & TEST OF COMPUTERS, FEBRUARY 1989, pp. 26-34). This is a test method for SRAM that is generally known as a test for a built-in memory of a system LSI. In the 13N test, for example, the pattern 0 is written in the ascending order of addresses in the entire memory area, and the processes of reading the written pattern 0, writing the pattern 1 and reading the pattern 1 are executed in ascending order for each address. The read data is compared with the expected value. In order to perform such processing by the program execution of the CPU, the pattern 0 read command, the pattern 1 write command, the pattern 1 read and address increment command, the pattern 0 data match determination command, and the pattern 0 did not match. Branch instruction for error handling, pattern 1 data match judgment instruction, branch instruction for error handling when pattern 1 does not match, loop counter decrement and loop end judgment instruction, loop not finished In this case, a program including a branch instruction to the top of the loop must be used. As is clear from this program example, the number of instruction execution cycles such as coincidence determination, branching, and decrementing instructions of the loop counter becomes larger than memory read instructions and write instructions.
The purpose of the present invention is to efficiently determine the test sequence at the time of test execution rather than at the time of chip design, and by using the CPU as a sequencer, the hardware resources required for the test can be reduced. It is to provide a way that can be tested.
Another object of the present invention is to provide a semiconductor integrated circuit that makes it possible to easily implement the test method for the built-in memory.
Still another object of the present invention is to provide an information recording medium storing IP module data such as a CPU, which can contribute to shortening the development period of a semiconductor integrated circuit that makes it possible to easily implement the built-in memory test method. There is.
Another object of the present invention is to record a test program and circuit design data that can contribute to improving the development efficiency of a semiconductor integrated circuit in terms of the development of a CPU and a test method for an on-chip memory accessed by the CPU. It is to provide a recording medium.
The above and other objects and novel features of the present invention will become apparent from the following description of the present specification and the accompanying drawings.
Disclosure of the invention
[1] << Memory Test Method >> A memory test method for testing a memory of a semiconductor integrated circuit having a CPU having an instruction queue, a memory, and a bus connecting the CPU and the memory stores a test program in the instruction queue. The CPU executes a test program to perform memory access via the bus, and once the test program is stored in the instruction queue, fetching of the test program is repeatedly performed from the instruction queue instead of the bus. To do.
Similarly, a memory test method for testing the memory of a semiconductor integrated circuit having a CPU having an instruction queue, a memory connected to the CPU via a bus, and a determination circuit connected to the memory and the bus includes: The test program is stored in the instruction queue, the CPU executes the test program to perform memory write access and memory read access, the memory read access data is compared with the expected value by the determination circuit, and the test program is temporarily stored in the instruction queue. The fetch of the test program after being performed is repeated from the instruction queue instead of the bus.
First, the memory test method employs a repeat operation in which the read information of the FIFO (First-In First-Out) type instruction queue is cyclically looped and the same stored information is used multiple times. There is no need to use a branch instruction to make the program repeatable. Second, a test program to be repeatedly executed may be repeatedly fetched from the instruction queue, and memory read / write access for memory test and memory access for instruction fetch do not compete on the bus. Therefore, branch instructions can be eliminated from the test program, and there is no need to repeatedly fetch the same instructions from the bus connected to the CPU, so memory access instructions such as move instructions for true memory tests are executed As a result, the test efficiency for the on-chip memory of the semiconductor integrated circuit can be improved.
The content of the above test method is determined by the CPU test program, and the test sequence can be determined not at the time of chip design but at the time of test execution. This makes it very easy to adopt the BIST method that requires fewer hardware resources for testing.
[2] << IP module data >> Focusing on CPU IP module data. Design data such as CPU IP module data read by a computer is recorded on a recording medium and provided. The design data includes an instruction queue, a bus, an instruction decoder for decoding instructions supplied via the instruction queue or the bus, and circuit data of the control unit. The instruction decoder decodes a predetermined repeat instruction and allows the control unit to repeat fetching of the program to be repeated from the instruction queue after the program to be repeated is temporarily stored in the instruction queue. Has the function of setting. If the CPU is designed using the circuit data stored in this recording medium, the development period of the semiconductor integrated circuit enabling the built-in memory test method can be shortened.
Focusing on IP module data such as a CPU and a test program, CPU design data and a test program that can be executed by the CPU realized by the design data are provided in a computer-readable manner recorded on an information recording medium. . The design data includes circuit data of an instruction queue, a bus, an instruction decoder, and a control unit. The instruction decoder decodes a predetermined repeat instruction and temporarily stores the program to be repeated in the instruction queue. A function for setting an operation mode in which fetching of the program to be repeated after being repeated can be repeated from the instruction queue. The test program is a program for a memory test that is stored in the instruction queue in the operation mode and causes the CPU to repeatedly execute a memory access process via the bus and a memory access address update process.
According to this computer-readable information recording medium, design data as IP module data facilitates the design and development of a semiconductor integrated circuit using a CPU. In such a memory test for the on-chip memory of the semiconductor integrated circuit, the on-chip CPU may execute the test program. Since the on-chip CPU supports the repeat operation of the instruction queue as a memory test function and enables the elimination of branch instructions from the test program, a memory test program optimized for the CPU hardware is developed from the beginning. You don't have to. Therefore, a user who develops a semiconductor integrated circuit using IP module data such as a CPU can improve the efficiency of the circuit design of the CPU and the test design for the on-chip memory, and the development of the semiconductor integrated circuit can be made more efficient.
Since the test program for the memory test is executed by an on-chip CPU, it can be described in an assembly language or the like used for CPU program development, and can be easily changed in accordance with the use of the semiconductor integrated circuit and a defective event. . Therefore, when providing the IP module data of the CPU, the user of the IP module data can easily cope with various memory tests only by providing a sample program as a test program for the memory test.
[3] << LSI >> Attention is focused on a semiconductor integrated circuit to which the on-chip memory test method can be applied. The semiconductor integrated circuit has a CPU, a memory, and a bus for connecting the CPU and the memory in a semiconductor chip. The CPU includes an instruction queue, an instruction decoder for decoding an instruction supplied via an instruction queue or a bus, and a control unit. The instruction decoder decodes a predetermined repeat instruction, thereby controlling the operation mode in which the program to be repeated can be repeatedly fetched from the instruction queue after the program to be repeated is temporarily stored in the instruction queue. Can be set in the section.
According to the semiconductor integrated circuit, the on-chip CPU supports the instruction queue repeat function as a memory test function, and enables the branch instruction to be excluded from the test program.
In the operation mode, when the CPU executes the program, a data read from the memory is input, and a determination circuit that compares the logical value of the input data with an expected value is provided. You may comprise so that it can output to the exterior of a chip | tip. Comparison instructions for comparison and determination can be removed from the test program executed by the CPU, and the memory test efficiency can be further increased.
At this time, by providing a dedicated bus separated from the bus as a path for supplying read data from the memory to the determination circuit, it is possible to avoid a situation in which the read data and the write data compete on the bus, thereby improving the memory test efficiency. Can be further improved.
From the viewpoint of further improving the test efficiency, when the memory has a plurality of memory blocks, each memory block may be mapped to the same address and enabled to operate in parallel in response to the setting of the operation mode. At this time, the determination circuit only needs to be able to compare and determine the memory read data output from the plurality of memory blocks in parallel with the expected value. As a result, a parallel test can be performed, and the memory test can be made more efficient.
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a system LSI such as a microcomputer as an example of a semiconductor integrated circuit according to the present invention. A system LSI 100 shown in the figure includes a CPU core 101, a DMA (Direct Memory Access Controller) controller 119, a bus controller 120, a peripheral module 121, and a fuse circuit 115, which are formed on a single semiconductor substrate (semiconductor chip such as single crystal silicon). ) By a semiconductor integrated circuit manufacturing technology such as CMOS.
The CPU core 101 includes a CPU 102, a DSP (Digital Signal Processor) 104, a cache memory 106, a general-purpose memory 107, an XY memory 108, and a BIST 110. The CPU 102 has an instruction control unit, an operation unit, and the like. The instruction control unit fetches and decodes instructions constituting the program, and the operation unit performs arithmetic processing and memory access processing according to the decoding result, and executes the instructions. To do. The DSP 104 is an arithmetic unit such as a coprocessor specialized for speeding up digital signal processing. The DSP 104 uses an XY memory 108 connected by an XY bus 109 for various digital signal processing operations such as product-sum operation. The cache memory 106 temporarily stores relatively frequently used programs and data among the programs and data stored in the ROM 131 and the RAM 132 outside the chip. The general-purpose memory 107 is used as a work area for the CPU 102 or a temporary storage area for data. The BIST module 110 is a test circuit used for an on-chip memory test or the like.
The CPU 102, DSP 104, cache memory 106, general-purpose memory 107, XY memory 108, and BIST module 110 are connected by a high-speed CPU bus 105. Further, the cache memory 106, the general-purpose memory 107, the XY memory 108, and the BIST module 110 are also connected to a system bus 118 for connecting to the outside of the CPU core 101. The cache memory 106 is configured to operate as a bridge circuit between the CPU bus 105 and the system bus 118 during non-cache access. That is, when the memory access target by the CPU 102 is a non-target area of the cache by the cache memory 106, the cache memory 106 functions as a bridge circuit that enables the bus 105 and the bus 118 to be connected. The general-purpose memory 107 and the XY memory 108 are each divided into four pages (four memory blocks).
The CPU 102 has a built-in instruction queue 103. Instructions are prefetched into the instruction queue 103 using the empty timing of the buses 105 and 118. In particular, in the present invention, the instruction queue 103 is operated as a repeat queue or loop queue in which a test program is stored when the general-purpose memory 107 and the XY memory 108 are tested, and the stored test program can be repeatedly used. In short, it is not necessary to fetch a test program that is repeatedly executed from the bus 105 through the cache memory 106 every time. Accordingly, it is possible to suppress or reduce the occurrence of a state in which the memory read / write data of the memory test competes with the test program on the bus 105, thereby realizing an efficient memory test. Details of the instruction queue 103 will be described later.
The BIST module 110 outputs a BIST enable signal (BISTEN) 140 indicating whether or not the memory test mode is set to the general-purpose memory 107 and the XY memory 108. Read data read from the general-purpose memory 107 in the memory test operation is supplied to the BIST module 110 via the dedicated data bus 141, and read data read from the XY memory 108 in the memory test operation is supplied to the BIST module 110 via the dedicated data bus 142. Is done. The BIST module 110 compares and determines the read data from the buses 141 and 142 with the expected value data, and outputs a test result signal 111 thereby from the external terminal 112 to the outside of the chip. As a result, read data and write data of the memory test do not compete on the bus 105. In this respect, the memory test can be made more efficient.
In addition, the BIST module 110 uses a general memory 107 such as address information (relief address information) to be relieved for relieving by replacing a defective portion with a redundant memory area when a part of the memory is defective. The relief information is output to the general-purpose memory 107 via the signal 113. In addition, a fuse circuit 115 for storing repair information obtained in the memory test in a nonvolatile manner is provided, and the repair information is input / output between the fuse circuit 115 and the BIST module 110 via a data signal 114. The fuse circuit 115 is controlled to write relief information from the BIST module 110 in accordance with a fuse circuit control signal 116 input via an external terminal 117 for controlling the fuse circuit.
The DMAC 119 performs data transfer control between the memories and data transfer between the memory and the input / output circuit according to the initial setting of the CPU. The bus controller 120 performs interface control relating to the bus width and transfer speed of information transmission via the external bus 130. The peripheral module 121 has peripheral functions such as a timer and a serial interface. The external bus 130 is not particularly limited, but includes a mask ROM (Read Only Memory), an EPROM (Erasable and Programmable Read Only Memory), an EEPROM (Electrically Erasable and Programmable Read Only Memory (SRAM), and a programmable read only memory (SRAM). The RAM 132 and the ASIC module 133 are connected.
In the normal operation mode of the system LSI 100, when the CPU 102 accesses the general-purpose memory 107 and the XY memory 108 via the CPU bus 105, only one page in each of the memories 107 and 108 designated by the address is targeted for access. In the case of read access, read data is read into the CPU 102 via the CPU bus 105, and in the case of write access, the write data on the CPU bus 105 is written into the memory cell of the access target page.
When a test program for a memory test is executed, writing is performed to a specific register in the BIST module 110, and a memory test mode (a state in which BISTEN is “1”) is set. In this memory test mode, if there is a read access by the CPU 102, the read data from the general-purpose memory 107 and the XY memory 108 is not output to the CPU bus 105 but is supplied to the BIST module 110 via the dedicated buses 141 and 142. . In this memory test mode, the pages of the general-purpose memory 107 and the XY memory 108 are read in parallel, and the BIST module 110 outputs data of 32 bits × 4 (number of pages) × 2 (number of memories) = 256 bits. Is done. When writing, the same data is simultaneously written to each page. The BIST module 110 compares the read data sent from each page of the memories 107 and 108 with the expected value data written in advance in the internal register of the module. Notify that a mismatch has occurred. The memory address related to the mismatch is held in the BIST module 110 as relief information. This relief information is stored in the fuse circuit 115 composed of a non-volatile storage element so as not to disappear even when the power is turned off.
Here, a 13N test method, which is one of the on-chip memory test sequences, will be described in advance with reference to FIG. This test is divided into five phases L0 to L4, and a pattern 0 (all bits 0, checker pattern, etc.) and its inverted pattern 1 (all bits 1, inversion checker pattern, etc.) are read / written. It has become. In the L0 phase (850), the pattern 0 is written in the ascending order of addresses in the entire memory area. In the L1 phase (851), the process of reading pattern 0, writing pattern 1 and reading pattern 0 written in the L1 phase is executed in ascending order for each address. In the L2 phase (852), the process of reading pattern 1 written in the L1 phase, writing pattern 0, and reading pattern 0 is executed in ascending order for each address. The L3 phase (853) and the L4 phase (854) are obtained by changing the address order of the L1 and L2 phases in descending order. Although the details will be described later, the test program executed by the CPU 102 is a program for performing the 13N test.
In FIG. 16, R0 means pattern 0 read, W0 means pattern 0 write, R1 means pattern 1 read, and W1 means pattern 1 write.
FIG. 2 illustrates in detail the connection state of circuit blocks related to the memory test. During the memory test, the CPU 102 repeatedly executes the test program using the repeat function, but the CPU 102 issues an instruction fetch to the CPU bus 105 only in the first loop of the test program repeated execution (repeat loop) at that time. The instruction fetch is issued to the cache memory 106, and is read from the cache memory 106 when a cache hit occurs, or from the outside of the chip via the system bus 118 and the bus controller 120 when a cache miss or cache is not used. become. The instruction is read from the instruction queue 103 in the CPU 102 after the second loop, and no instruction fetch is issued to the CPU bus 105. In short, once the test program is stored in the instruction queue 103, fetching of the test program is repeated from the instruction queue 103 instead of the bus 105.
When the CPU 102 executing the test program executes a write access to the test target memory, the bus command bus (CPU bus command bus) 201, the address bus (CPU address bus) 203, and the data bus (CPU data bus) 203 of the CPU bus 105 are executed. The value required for is output. When the control signal BISTEN 140 output from the BIST module 110 is “L”, writing is performed only on the single page specified by the address, but when BISTEN is “H”, writing to all pages in parallel is performed. Is done. When the CPU 102 executes read access, necessary values are output to the bus command bus 201 and the address bus 202 of the CPU bus 105. When the control signal BISTEN is “L”, only the page designated by the address outputs data to the CPU data bus 203, but when the control signal BISTEN is “H”, all pages are read in parallel. The general-purpose memory 107 and the XY memory 108 output read data to dedicated data buses 141 and 142 connected to the BIST module 110. The dedicated data buses 141 and 142 are prepared for 32 bits × 8, that is, 256 bits according to the number of pages (8 pages). At this time, read data is not supplied to the CPU data bus 203. The BIST module 110 decodes the values of the CPU bus command bus 201 and the CPU address bus 202. If the control signal BISTEN is “H” and a read cycle, it is output to the dedicated data buses 141 and 142 from the memories 107 and 108. The data is compared with the expected value previously set in the register in the BIST module 110, and if a mismatch occurs, the signal (FAIL) 204 is asserted and the signal is output to the outside of the chip via the external terminal (FAIL) 205. Notify discrepancy. In addition, the occurrence of mismatch is recorded in the status register in the BIST module 110, and the operation is performed so that the occurrence of mismatch can be later read from the CPU 102 and recognized. When a mismatch occurs, it is determined whether the bit can be repaired. If the bit cannot be repaired, a repair disable signal 206 is output from the repair disable terminal 207 to the outside of the chip, and this is notified to the outside. The BIST module 110 can also store the address where the mismatch occurred in an internal register. When the relief bit (redundant bit) of the general-purpose memory 107 is used, the BIST module 110 outputs the fuse data 114 to the fuse circuit 115 so that the address of the bit to be saved can be written in the fuse circuit 115. The BIST module 110 can output a relief information signal 113 indicating an address to be rescued to the general-purpose memory 107 based on data read from the fuse circuit 115 or a value of an internal register. . The data writing operation to the fuse circuit 115 is performed by writing data from the BIST module 110 according to an instruction from the fuse control terminal 117 of the chip (generally, from a tester during a pre-shipment test). The fuse circuit 115 is a non-volatile memory, and is configured by a small-capacity flash memory in this embodiment.
FIG. 3 illustrates details of the BIST module 110. The BIST module 110 includes a comparator 251, an address decoder 252, a register unit 253, a repair determination unit 254, and a fuse control unit 255. Here, eight 32-bit comparators 251 are provided in order to perform simultaneous parallel tests on four pages in each of the general-purpose memory 107 and the XY memory 108, for a total of eight pages.
The comparator 251 notifies the address decoder 252, the relief determination unit 254, and the register unit 253 of an 8-bit comparison result signal 263 as to whether or not there is a mismatch in the comparison results of the eight pages. The address decoder 252 decodes the values of the CPU bus command bus 201 and the CPU address bus 202 and determines whether it is a read cycle. If it is a read cycle, the comparison enable signal 256 is asserted to each comparator 251 and the comparator 251 is activated. The expected value used by the comparator 251 can be selected from two types according to the address, and the expected value selection signal 257 is notified to the comparator 251. For example, in the 13N test, the pattern 0 and the pattern 1 can be switched dynamically. Further, when the comparison result from the comparator 251 does not match, the address decoder 252 outputs the corresponding error address 258 to the relief determination unit 254 and the register unit 253. The repair determination unit 254 determines whether repair is possible based on the error address, and outputs a repair disable signal 206 from the repair disable terminal 207. When a mismatch occurs in the comparator 251, the FAIL signal 204 is output from the FAIL terminal 205. The assertion of the FAIL signal 204 and the repair impossible signal 206 can be masked according to the setting contents of the register unit 253. In addition, the repair determination unit 254 generates repair data to be written in the fuse circuit 115 based on the error address information, and outputs this to the register unit 253 as a repair data signal 264. The fuse control unit 255 inputs / outputs a fuse data signal 114 to / from the fuse circuit 115, and outputs a relief information signal 113 as relief data to the general-purpose memory 107. Although details of the register unit 253 will be described later, two types of expected value signals 260 and 261 and an MS signal 262 for designating ON / OFF of the comparator for each page of the memory are output to the comparator 251. . In addition, a signal 265 that masks assertion of the FAIL terminal 205 and the repair impossible terminal 207 is output to the repair determination unit 254 based on the register setting. In addition, an address limit signal 266 that determines the upper limit of the addresses of the general-purpose memory 107 and the XY memory 108 based on the setting of the register unit 253 is output to the address decoder 252. The register unit 253 can input / output an FD signal 267 as relief data to the fuse control unit 255.
FIG. 4 shows a plurality of registers held by the register unit 253. The register unit 253 includes registers 301 to 307, which are accessible via the CPU bus 105, the cache memory 106, and the system bus 118 by non-cache access of the CPU 102.
Expected value registers (BISTDR0 and BISTDR1) 301 hold two types of expected values for comparison. An address register (BISTFAR0, BISTFAR1, BISTFAR2, BISTFAR3) 302 stores an error address where a mismatch has occurred. The fuse data register (BISTFDR) 303 stores data for writing relief address information generated from the error address in the fuse circuit. A status register (BISTSR) 304 records that there is a mismatch for each page. A module select register (BISTMS) 305 holds control information for controlling whether to test each page. A control register (BISTCR1) 306 holds control information for controlling on / off of the memory test mode, fail-stop mode, and relief information. The address limit control register (BISTCR2) 307 holds control information for determining the test range of each page when simultaneously testing memories of different sizes.
The expected value registers (BISTDR0, BISTDR1) 301 are 32-bit registers, each holding an expected value for comparison. If bit 18 of the CPU address bus 202 is “0”, one register ( If BISTDR0) is "1", the other register (BISTDR1) is used. These are used for switching between pattern 0 and pattern 1 in the 13N test. The address registers (BISTFAR0, BISTFAR1, BISTFAR2) 302 are 32-bit registers, and four general purpose memories can be relieved for each page, and four error addresses need to be held. A fuse data register (BISTFDR) 303 is a 32-bit register for holding data to be written in the fuse circuit 115, and data is automatically generated by the repair determination unit 254 based on the error address and written to the register. The status register (BISTSR) 304 is an 8-bit register, and the initial value is all bits “0”. However, when a mismatch occurs due to a test, “1” is written in the bit corresponding to each page. S13 to S10 correspond to each page of the XY memory 108, and S03 to S00 correspond to each page of the general-purpose memory 107.
A module select register (BISTMS) 305 is an 8-bit register that controls whether a test is performed for each page. When each bit is “1”, the test is on, and when it is “0”, the test is off. However, even if the test is set to OFF, the read / write operation of the memory itself is not stopped, and the comparator 251 operates so as not to perform comparison. M13 to M10 correspond to each page of the XY memory 108, and M03 to M00 correspond to each page of the general-purpose memory 107.
The control register (BISTCR1) 306 is an 8-bit register, and there is an enable bit EN for turning on / off the entire memory test function. When “1” is written in this bit, the memory test function is enabled. The BISTEN signal 140 becomes “H”, and the operation of each memory is switched to the memory test mode. The C0 bit controls the mask of the FAIL signal 204. When set to “1”, the FAIL signal 204 is not asserted even if a mismatch occurs. Similarly, the C1 bit controls the mask of the unrepairable signal 206, and when it is set to “1”, the unrepairable signal is not asserted even if an unrepairable error occurs. The C2 bit is used to control whether the relief information for the general-purpose memory is generated from the data from the fuse circuit 115 or from the data in the fuse data register (BISTFDR) 303. Then, the fuse data register (BISTFDR) 303 is selected. The initial value is “0”.
A control register (BISTCR2) 307 is an 8-bit register and designates the size of one page of the XY memory 108 and the general-purpose memory 108. SZ12 to SZ10 correspond to the XY memory 107, and SZ02 to SZ00 correspond to the general-purpose memory 107. The set values and storage capacities are combinations of 000: 4k, 001: 8k, 010: 16k, 011: 32k, 100: 64k, 101: 128k, 110: 256k, 111: 512k bytes.
FIG. 5 illustrates the configuration of one page of the XY memory 108 as a representative of the general-purpose memory 107 and the XY memory 108 to be subjected to the memory test.
In the example shown in FIG. 5, the size of one page is 4 kbytes, and a memory mat 357 of 4 kbytes is provided.
The XY memory 108 is connected to three buses: a CPU bus 105, an XY bus 109, and a system bus 118. An arbitration circuit 351 has a bus command bus 201 for the CPU bus, an address bus 202 for the CPU bus, and a bus command bus for the XY bus. 211, the address bus 212 of the XY bus, the bus command bus 221 of the system bus, and the address bus 222 of the system bus are decoded to determine from which bus the access is to be processed. The priority order is system bus> XY bus> CPU bus, but the test program is configured to access only from the CPU bus 105 during the memory test. An address selector 353 selects an address in accordance with an address selection signal 352 from the arbitration circuit 351. The upper bits of the address signal selected by the address selector 353 are supplied to the enable control circuit 356 and used for selecting the memory mat, and the remaining lower address bits are supplied to the address decoder 360 and used for selecting the memory cells. The
At the time of write access, write data to the memory mat 357 is selected by the write data selector 355 according to the data selection signal 354. The output buffer 203B, 213B, or 223B selects to which data bus the read data from the memory mat 357 is to be output at the time of reading.
The enable control circuit 356 decodes the command, address and control signal (BISTEN) 140 selected by the arbitration circuit 351, and determines whether to activate the memory mat 357, the write control circuit 358, and the sense amplifier 359. . That is, when BISTEN 140 is “L”, the upper address bits are decoded so that each page responds to a different address, but when BISTEN 140 is “H”, all pages respond to the same address. Decode as you do.
Although not shown, the configuration of one page of the general-purpose memory 107 is the same as that shown in FIG. 5 except that the XY bus 109 is not connected and the memory size is different. .
FIG. 6 illustrates an address map of the general-purpose memory 107. This figure shows an example in which the general-purpose memory 107 has four pages of 32 kbytes per page and a total of 128 kbytes. Although not particularly limited, 4 Mbytes of space is allocated to the general-purpose memory in consideration of expandability, and in this embodiment, the actual memory exists in 128 kbytes. In the case of this configuration, the address map when BISTEN 140 is “L (= 0)” is as shown in FIG. The four pages are allocated to “U0L: 0xA55F0000 to 0xA55F7FFF”, “U0H: 0xA55F8000 to 0xA55FFFFF”, “U1L: 0xA5600000 to 0xA5607FFF”, and “U1H: 0xA5600000 to 0xA5608FFF”. The symbol 0x means that the subsequent value is a hexadecimal number. The shaded area 401 in FIG. 6 (a) becomes a shadow, and the enable signals UPAGE0LEN, UPAGE0HEN, UPAGE1LEN, and UPAGE1HEN of each page have values as shown on the right side of FIG. 6 (a). On the other hand, the address map when BISTEN 140 is “H (= 1)” is as shown in FIG. In this case, all pages are allocated to 32 kbytes of 0xA50000000 to 0xA5007FFF, and the enable signal of each page is asserted at the same address. In this case, access to the area 402 indicated by “x” in FIG. 6B does not react to any page and becomes invalid.
FIG. 7 illustrates the configuration of the enable control circuit 356 for realizing the address map of FIG. FIG. 7 collectively shows the logic for four pages. The upper address decoder 451 is 0xA500 when the command 452 is read or write and when the BISTEN 140 is “L”, the upper 31 bits to 20 bits (A31 to A20) of the address are 0xA540 to 0xA57F, and when the BISTEN 140 is “H”. In the case of ˜0xA53F, the enable signal (UMEMEN) 453 is operated to be asserted. The enable signals (UPAGE0LEN, UPAGE0HEN, UPAGR1LEN, UPAGE1HEN) for each page are UMEMEN453, BISTEN140, and address bits A21 and A15, decode circuits (U0LDEC) 460, (U0HDEC) 461, (U1LDEC) 462, (U1HDEC) ) 463 is generated by decoding. The address bit A21 is an address bit for determining 0xA5400000 to 0xA55FFFFF or 0xA5600000 to 0xA57FFFFF, and the address bit A15 is an upper half or a lower half with respect to the region of 0xA5400000 to 0xA55FFFFF, and an upper half with respect to the region of 0xA5600000 to 0xA57FFFFF Or the lower half of the address bits. When BISTEN 140 is “L”, ENOR (exclusive negative OR gate) 480 functions as an inverter, and enable signals (UPAGE0LEN) 470, (UPAGE0HEN) 471, (UPAGE1LEN) 472, and (UPAGE1HEN) 473 of each page are exclusive. Asserted. On the other hand, when BISTEN 140 is “H”, ENOR 480 functions as a buffer, and only when the address bits A21 and A15 are both “0” and UMEMEN is “1”, the enable signals 470 to 473 of each page are asserted in parallel. When the address is in any other condition, the operation is performed so that all the enable signals 470 to 473 are negated regardless of UMEMEN.
FIG. 8 illustrates an address map of the XY memory 108. This figure shows an example in which the XY memory 108 has 4 pages, 4 pages per page, and a total of 16 kbytes. In consideration of extensibility, a space of 128 kbytes from 0xA5000000 to 0xA501FFFF is allocated to the XY memory 108, and in this embodiment, an actual memory exists in 16 kbytes. Although not shown in the figure, the space of 0xA502000-0xA50FFFFF is treated as a shadow of the space of 0xA50000000-0xA501FFFF. In the case of this configuration, the address map when BISTEN 140 is “L” is as shown in FIG. The four pages are assigned to “X0: 0xA5007000-0xA5007FFF”, “X1: 0xA5000000-0xA5008FFF”, “Y0: 0xA5017000-0xA5017FFF”, “Y1: 0xA5018000-0xA5018FFF”, respectively. In this case, the shaded area 501 in FIG. 8 becomes a shadow, and the enable signals (XPAGE0EN, XPAGE1EN, YPAGE0EN, YPAGE1EN) of each page have values as shown on the right side of FIG. 8 (a). On the other hand, the address map when BISTEN 140 is “H” is as shown in FIG. In this case, all pages are allocated to “0xA50000000 to 0xA5000FFF”, and the enable signals (XPAGE0EN, XPAGE1EN, YPAGE0EN, YPAGE1EN) of each page are also asserted at the same address. Access to the area 502 indicated by “x” in FIG. 8B does not react to any page and becomes invalid. A difference from the case of the general-purpose memory 107 shown in FIG. 6 is that the shadow area 501 disappears when the BISTEN 140 is “H”. In this embodiment, since the memory size is smaller than the general-purpose memory 107, if a shadow is left when performing the simultaneous test, for example, in the L1 phase of the 13N test, the XY memory 107 is being executed while executing the L1 phase of the general-purpose memory. This is because the test in the L1 phase is performed a plurality of times and the state expected at the start of the next L2 phase is broken.
FIG. 9 illustrates the configuration of the enable control circuit 356 for realizing the address map. The upper address decoder 551 operates to assert XMEMENB 553 when the command 552 is read or write and the upper bits 31 to 20 of the address are 0xA50. The AMASK circuit 554 decodes the address bits A14, A13, A12, XMEMENB553, and BISTEN140 to generate XMEMEN555. When BISTEN is “0”, XMEMEN = XMEMENB regardless of the address bits A14, A13, A12, but when BISTEN140 is “1”, the address bits A14, A13, A12 are “000”. Only XMEMEN = XMEMENB, otherwise XMEMEN is “0”. The enable signal for each page is generated by decoding XMEMEN 555, BISTEN 140, and address bits A16 and A15 with decode circuits (X0DEC) 560, (X1DEC) 561, (Y0DEC) 562, and (Y1DEC) 563. When BISTEN 140 is “L”, ENOR 580 functions as an inverter, and enable signals (XPAGE0EN) 570, (XPAGE1EN) 571, (YPAGE0EN) 572, and (YPAGE1EN) 573 of each page are exclusively asserted. On the other hand, when BISTEN 140 is “H”, ENOR 580 functions as a buffer, and only when address bits A16 and A15 are both “0” and XYMEMEN 555 is “1”, enable signals 570 to 573 of each page are asserted at the same time. When the condition is other than XYMEMEN 555, the operation is performed so that all enable signals 570 to 573 are negated regardless of XYMEMEN 555.
FIG. 10 illustrates the details of the CPU 102 with the instruction fetch configuration as the main component. Reference numeral 610 denotes an arithmetic unit, which is not particularly shown, and includes a general-purpose register, an arithmetic logic unit, an address register, a data buffer register, a temporary register, a control register, and the like connected to the internal bus. The CPU address bus 202 is connected to the address register, and the CPU data bus 203 is connected to the data buffer register.
The instruction queue 103 includes, for example, an instruction buffer 103BF having a 12-stage buffer area, and a read pointer 103RP and a write pointer 103WP for causing the instruction buffer 103BF to perform a FIFO operation. The read pointer 103RP is a loop counter that designates a buffer area for performing a read operation, and the count value CNTR is set to # 0 to # 11. The write pointer 103WP is a loop counter for designating a buffer area in which a write operation is performed, and the count value CNTW is set to # 0 to # 11. The read pointer 103RP and the write pointer 103WP are based on the initial values, and the write pointer 103WP is incremented each time a write operation is performed, and the read pointer 103RP is incremented each time a read operation is performed. The state in which the count value CNTR of the read pointer 103RP has caught up with the count value CNTW of the write pointer 103WP is a state in which no significant storage information is held in all of the 12-stage buffer area, in other words, it is temporarily stored in the buffer area. The stored information means an empty (empty) state in which reading is complete. The state in which the count value CNTW of the write pointer 103WP has caught up with the count value CNTR of the read pointer 103RP is a state in which significant storage information is held in all the 12-stage buffer areas, in other words, all the buffer areas are still It means a full state filled with storage information that has not been read.
The instruction buffer 103B fetches an instruction from the CPU data bus 203. The instruction read from the buffer 103B or the instruction on the CPU data bus 203 is selected by the selector 603 and supplied to the instruction register (IR) 601. The instruction latched in the IR 601 is decoded by the instruction decoder 602, and the arithmetic operation by the arithmetic unit 610 is controlled according to the decoding result, and the instruction control unit 607 is controlled.
The instruction control unit 607 causes the selector 603 to select the instruction fetch path to the IR 601 by the selection signal SEL, and generates the increment signal INCR of the read pointer 103RP and the increment signal INCW of the write pointer 103WP. The instruction control unit 607 controls generation of a memory access cycle via the arithmetic unit 610 for instruction fetch or instruction prefetch, and controls instruction write (push) and read (pull) operations to the instruction queue 103. Further, control is performed such that the instruction queue 103 operates as a repeat queue or a loop queue.
An instruction prefetch control function by the instruction control unit 607 will be described. The instruction control unit 607 receives the count value CNTR of the read pointer 103RP and the count value CNTW of the write pointer 103WP, and detects the full empty state of the instruction buffer 103. If the instruction buffer 103B is not full, the instruction control unit 607 uses a free timing of the data bus 203 to prefetch instructions from the cache memory 106 or the external ROM 131 or RAM 132 to the instruction buffer 103B. Is generated by the arithmetic unit 610. The instruction address at this time is generated using a program counter or the like. The instruction supplied to the data bus 203 in this memory cycle is held in the instruction buffer 103B, and the value of the write pointer 103WP is incremented by the increment signal INCW.
An instruction fetch control function by the instruction control unit 607 will be described. If the instruction buffer 103B is not in an empty state at the instruction fetch timing to the IR 601, the instruction read from the instruction buffer 103B is latched in the IR 601 via the selector 603. After reading from the instruction buffer 103B, the read pointer 103RP is incremented. If the instruction buffer 103B is in an empty state at the instruction fetch timing to the IR 601, the arithmetic unit 610 generates a memory cycle for fetching an instruction from the cache memory 106 or the external ROM 131 or RAM 132. The instruction obtained on the bus 203 is latched in the IR 601 via the selector 603.
The repeat queue control function by the instruction control unit 607 will be described. The instruction set of the CPU 102 includes repeat instructions. This repeat instruction designates the first instruction address to be repeatedly executed, the last instruction address, and the number of repetitions. When the instruction decoder 602 decodes the repeat instruction, it controls the instruction address generation by the arithmetic unit 610 and instruction fetch to the instruction control unit 607 so that the instruction from the first instruction address to the last instruction address is repeatedly executed a specified number of times. Thus, a repeat loop is formed. At this time, the instruction decoder 602 gives an instruction to the instruction control unit 607 to operate the instruction queue 103 as a repeat queue. That is, the instruction decoder 602 sets a repeat queue mode flag 607F in the instruction control unit 607 by decoding a repeat instruction, and sets the number of repeat loop repetitions and the number of instructions to be executed in each repeat loop in the register 607R. After this operation is performed, the instruction control unit 607 resets the values of the read pointer 103RP and the write pointer 103WP to initial values before proceeding to the execution of the head instruction specified by the repeat instruction, and in the first repeat loop, The instruction is fetched from the cache memory 106 or the external ROM 131 or RAM 132 to the IR 603, and the fetched instruction is executed. In parallel with this, an operation of sequentially storing instructions of the first repeat loop in the instruction queue 103 is performed. From the second repeat loop, the instructions stored in the instruction buffer 103B are sequentially read and executed. At this time, every time the count value of the read pointer 103RP reaches the set value (number of instructions) of the register 607R, the instruction control unit 607 returns the count value CNTR to the initial value with the reset signal RES, and causes the ring counter operation. When the repeat loop execution count finishes the set value of the register 607R (repeat loop repeat count), the repeat queue mode flag 607F is reset, whereby the instruction control unit 607 ends control of the repeat queue operation for the instruction queue 103. To do.
As described above, when the repeat loop is used, the instruction control unit 607 determines the length of the repeat loop, and when the length is within the instruction queue (12 instructions or less in this example), the instruction queue 103 stores the repeat loop. Control is performed so that the instruction once stored and read is not immediately discharged but is reserved for the second and subsequent repeat loops. As a result, instruction fetch is required only for the first repeat loop, but instruction fetch is not required when executing the second and subsequent repeat loops, so that the CPU bus 105 can be used efficiently. . In addition, since the process of returning to the top in a repeat loop does not require a branch instruction, the program itself constituting the loop is shortened. By using such a repeat instruction in a test program for a memory test, the memory test can be speeded up.
FIG. 11 illustrates a test flow in the case where the general memory 107 is not relieved. First, in step 651, the BIST module 110 is initialized. Specifically, the C2 bit of the control register BISTCR1 is set to “0”, and the repair information signal 113 is generated from BISTFDR (303). Also, all bits “0”, which is set to “use no relief bit”, are written in BISTFDR. With the above settings, the relief bit is not used. Further, “0” is set to the C0 bit of BISTCR1, and when a mismatch occurs, the FAIL terminal 205 is asserted. Further, the expected values for pattern 0 and pattern 1 are set in BISTDR0 and BISTDR1 (301). Next, in step 652, "1" is written to the EN bit of BISTCR1, and the memory test mode is entered. As a result, BISTEN 140 becomes “1”.
Next, in step 653, the CPU 102 is caused to execute a repeat instruction for the memory test, and performs memory access for the memory test, update of the access address, and the like according to the repeat loop test program. Next, in step 645, the data read from the memory is compared with the expected value written in the register. This comparison is performed in parallel for each page in the BIST module 110. Next, in step 655, the comparison result is determined, and if there is a mismatch in any one page, the FAIL terminal, which is an external terminal, is asserted in step 656, and it is determined as a defective product, and the test ends. .
If no mismatch has occurred in the comparison result, the loop counter is decremented in step 657. Next, in step 658, it is determined whether or not the loop counter has become 0. If not 0, the process returns to step 653. This operation is repeated until the loop counter reaches 0, and if no mismatch occurs until then, it is determined as PASS. All processing in steps 654 to 658 is performed by hardware. When the entire test is configured for each of a plurality of phases, such as a 13N test, the above-described series of operations is repeated for the number of phases, and a non-defective product is determined as PASS when the final phase is completed.
In FIG. 11, steps 656 and 657 are processing by hardware, and the other steps are processing by software.
FIG. 12 illustrates a test flow in the case where the general memory 107 is relieved. First, in step 701, the BIST module 110 is initialized. Specifically, the C2 bit of the control register BISTCR1 (306) is set to “0”, and the repair information signal 113 is generated from the BISTFDR (303). Also, ALL0, which is set to “use no relief bit”, is written in BISTFDR. With the above settings, the relief bit is not used. Further, the C0 bit of BISTCR1 is set to “1” so that the FAIL terminal 205 is not asserted even when a mismatch occurs. Further, the expected values for pattern 0 and pattern 1 are set in BISTDR0 and BISTDR1 (301). Next, in step 702, “1” is written to the EN bit of BISTCR1, and the memory test mode is entered. As a result, BISTEN 140 becomes “1”.
Next, in step 703, the CPU 102 is caused to execute a repeat instruction for a memory test, and a memory access and an access address update for the memory test are performed according to a repeat loop test program. In step 704, the data read from the memory is compared with the expected value written in the register. This comparison is performed in parallel for each page in the BIST module 110. Next, in step 705, the comparison result is determined. If a mismatch has occurred in any one page, it is determined in step 706 whether the address in which the mismatch has occurred can be relieved. Here, it is possible to relieve up to one address for each page of the general-purpose memory 106. Accordingly, when a mismatch occurs at a plurality of locations on the same page or when a mismatch occurs in the XY memory 108 having no repair bit, it is determined that the repair is impossible. When it is determined that the repair is possible, information for generating the repair information signal 113 is written in the BISTFDR. If it is determined that the repair is not possible, the repair impossible terminal 207 is asserted in step 707, the product is determined to be defective, and the test ends. If there is no mismatch in the comparison result, or if it is determined that there is a mismatch but it can be remedied, the loop counter is decremented in step 708. Next, in step 709, it is determined whether or not the loop counter has become 0. If not 0, the process returns to step 703. This operation is repeated until the loop counter reaches zero. The processing in steps 704 to 709 is all performed by hardware.
When the loop counter reaches 0, the process proceeds to step 710. If no mismatch has occurred until then, it is determined as normal (PASS). If there is a mismatch, it can be remedied and the process proceeds to step 711. If there is a mismatch that can be repaired at the above-described test stage, data necessary for generating the repair information signal 113 is automatically written in the register (BISTFDR) under the control of the BIST module 110. Therefore, next, the relief bit is tested using this relief information. Although the test operation itself is the same as described above, in the initial setting of the BIST module in step 712, the C0 bit of BISTCR1 is set to “0” and the FAIL terminal (205) is asserted when a mismatch occurs. To be. Since the repair has already been used, the further occurrence of mismatch means that the repair bit is also defective. In this case, the FAIL terminal is asserted in step 717 and is determined to be defective. The operations in steps 713 to 719 are the same as those in steps 702 to 709, respectively. If no inconsistency occurs at the end of the test, the repair is successful. In step 720, the BISTFDR data is written in the fuse circuit 115 and the test is terminated.
In FIG. 13, steps 704, 707, 708, 711, 715, 717, and 718 are processing by hardware, step 720 is processing by a tester, and the other steps are processing by software.
FIG. 13 shows an instruction sequence in assembly language for performing a 13N test on the system LSI of FIG. The repeat instruction (REPEAT) is an instruction for designating a repeat loop start address, end address, and loop count, and has a syntax of “REPEAT start address, end address, loop count designation register”. The start address and end address can be specified by labels of assembly language programs. As shown in FIG. 16, the 13N test is composed of five phases L0 to L4. Each L0 is a one instruction repeat loop (750), and each L1 to L4 is a three instruction repeat loop (751, 752). 753, 754). The reason why two types of address pointer registers R2 and R3 are prepared for reading is to switch the expected values of the pattern 0 and the pattern 1 by the bit A18 of the address. As shown in FIGS. 6B and 8B, in this example, when BISTEN 140 is “1”, the general-purpose memory 107 and the XY memory 108 are mapped to 0xA5000000 to 0xA5007FFF. The initial value of the pointer is set to 0xA5000000. Since each page of the memory is accessed with a 32-bit width, the initial value of the loop counter is set to 0x2000.
FIG. 14 shows a timing chart of the CPU bus 105 and the BIST dedicated data buses 141 and 142 executing the phase L1 of the instruction sequence shown in FIG. R. L is a longword (32 bits) read command, W.L. L is a long word write command, RD0 is 13N test pattern 0 read data, RD1 is pattern 1 read data, and WD1 is pattern 1 write data. According to this, for example, it takes 3 cycles / loop to execute the phase L1 of the 13N test. Furthermore, a parallel test can be performed on 8 pages of the general-purpose memory 107 and the XY memory 108 together.
Here, as a comparative example, a case where the CPU tests an on-chip memory when it does not have a repeat loop function and does not have a dedicated circuit for comparison determination will be described. As a program according to the comparative example for performing the 13N test, a test program for executing the L1 phase can be described as shown in FIG. 17, for example. R0 to R7 are CPU registers, where R0 is a memory address, R1 is pattern 0 expected value data, R2 is pattern 1 write data and expected value data, R3 is pattern 0 read data storage destination, and R4 is pattern One read data storage destination, R7, is a loop counter. This program is composed of 9 instructions, each of which reads pattern 0 with instruction 901, writes pattern 1 with instruction 902, reads pattern 1 with instruction 903 and increments the address, determines whether pattern 0 data matches with instruction 904, Branch for performing error processing when pattern 0 does not match with instruction 905, decision to match pattern 1 data with instruction 906, branch for performing error processing when pattern 1 does not match with instruction 907, instruction 908 The loop counter is decremented and the loop end is determined, and the branch to the top of the loop when the loop is not ended with the instruction 909 is performed.
FIG. 18 shows a timing chart of the bus connecting the CPU and the built-in memory when the test program according to the comparative example is placed in the cache memory and the built-in memory test capable of one cycle access is executed. This shows the fourth loop when the memory to be tested is allocated from 0xA5000000. Eleven cycles are required per loop. Of these, only the pattern 0 read command 951, the pattern 1 write command 952, and the pattern 1 read command 953 are actually tested. Only 3 cycles are spent. The remaining 8 cycles are an instruction fetch cycle 954 of the program itself and a cycle 955 by a comparison instruction. In addition, since the data received and compared by the CPU is one data per cycle, even when there are a plurality of memories to be tested, a simultaneous parallel test cannot be performed and it is necessary to test sequentially.
In FIG. 18, JIF is a branch instruction fetch, NIF is a normal instruction fetch, R.I. L is longword read, W.L. L is long word write, NOP is non-operation, RD0 is read data 0, RD1 is read data 1, and WD1 is write data 1.
Comparing the case of the present invention of FIGS. 13 and 14 with the case of the comparative example of FIGS. 16 and 17, the latter is 11 cycles / loop to execute the phase L1 of the 13N test, In the case of the present invention, there are 3 cycles / loop. Further, in the case of the comparative example, only one page of the memory can be tested at the same time. However, according to the present invention, simultaneous parallel testing of 8 pages can be performed, and the memory test can be further speeded up. it can. That is, focusing on the L1 phase of the 13N test, in the comparative example, “11 cycles × 8k loops × 4 pages = 352 k” steps are required for the general-purpose memory test, and “11 cycles × 1k loop × 4” are required for the XY memory test. Page = 44k "steps are required, for a total of 396k steps. On the other hand, in the present invention, it is understood that all the memories need only “3 cycles × 8k loops = 24k” steps, and the speed is increased by 396/24 = 16.5 times.
FIG. 15 shows another example of the semiconductor integrated circuit according to the present invention. In the example of FIG. 1, the cache memory 106 is not a test target. However, in the example of FIG. 15, the cache memory 106 is also a test target. Specifically, the BISTEN 140 is also output to the cache memory 106, and the BIST dedicated data bus 143 is provided from the cache memory 106 to the BIST module 110. The BIST module 110 is connected to the general-purpose memory 107, the XY memory 108, and the cache memory 106. The parallel read / write processing can be performed on the read data. The bridge function between the CPU bus 105 and the system bus 118 included in the cache memory 106 can be used even in the memory test mode, so that a parallel test including the cache memory 106 can be performed. In short, in the memory test mode, the cache memory 106 is arranged in the memory space of the CPU 102, and can be read / written by designating an address.
Further, in the example shown in FIG. 15, the XY memory 108 and the cache memory 106 are also configured to be relieved, and the relieving information signals 144 and 145 are output from the BIST module 110 to each.
FIG. 19 illustrates the development and manufacturing procedures of a semiconductor integrated circuit having a self-test function as typified by FIG. Referring to FIG. 19, a desired semiconductor integrated circuit is planned and its specifications are determined. Based on this, logic design (S1), layout design (S2), photomask creation (S3), and manufacturing (S4) The function test (S5), the memory test (S6), and the shipping process (S7) are performed. Development and manufacture of a semiconductor integrated circuit can be performed by one semiconductor integrated circuit manufacturer. Nowadays, there are cases in which the division of labor is divided into a so-called foundry responsible only for manufacturing a semiconductor integrated circuit and a so-called fabless that specializes in designing a semiconductor integrated circuit and does not have a manufacturing department. For example, the fabless employs a business form in which logic design and, if necessary, layout design are performed, and subsequent processes are outsourced to the foundry, and the final product is received and shipped. For example, in FIG. 19, FB is positioned as fabless processing, and FD is positioned as foundry processing.
In the development design process such as the logical design (S1) and the layout design (S2), it is possible to use past design assets, and moreover, today, it is possible to use circuit design data distributed as IP module data. . The IP module data includes design data (also referred to as soft IP module data) in which circuit modules such as the CPU 102 and the DSP 104 are specified in a logic description language such as HDL (Hardware Description Language), or mask pattern data. (Also referred to as hard IP module data). Normally, IP module data is packaged with debugging information in addition to circuit design data.
In order to make it possible to easily apply the means for improving the efficiency of the on-chip memory test described with reference to FIG. Can be provided as simple design data.
For example, focusing on the CPU, the circuit data of the CPU 102 having the loop queue function described in FIG. 10 may be provided as the soft IP module data or the hard IP module data. In short, such circuit data may include the circuit data of the instruction queue 103, the bus 105, the instruction decoder 602 that decodes the instruction supplied via the instruction queue 103 or the bus 105, and the control unit 607. The instruction decoder 602 can repeat a fetch of the program to be repeated from the instruction queue after the program to be repeated is temporarily stored in the instruction queue 103 by decoding a predetermined repeat instruction and stored in the instruction queue 103. It is only necessary to realize a function for setting the operation mode to be performed. This function may be described by HDL or specified by a specific circuit mask pattern.
The design data of the CPU 102 may be provided together with a test program that can be executed by the CPU 102 realized by the design data. The test program is stored in the instruction queue 103 in the operation mode such as the loop queue mode, and causes the CPU 102 to repeatedly execute the memory access processing and the memory access address update processing via the bus 105. I just need it.
The design data and the test program may be provided by being stored in a computer-readable information recording medium (also simply referred to as a recording medium). For example, the recording medium includes a CD-ROM (Compact Disk-Read Only Memory), a CD-R (Compact Disk-Recordable), a CR-RW (Compact Disk-Rewriteable), and a DVD-ROM (Digital Video Disk Read-Ready-Ready-Ready-Ready-Ready-Ready-Ready-Ready-Ready-Ready-Ready-Ready-Ready-Ready-Ready-Ready-ReadyM)). Any computer-readable recording medium such as a DVD-RAM (Digital Video Disk-Random Access Memory) or FD (Floppy Disk) may be used.
FIG. 20 shows an example of a semiconductor integrated circuit development system. In the figure, reference numerals 1, 2, and 3 denote computer devices such as engineering workstations, which are connected to an information processing network. The information processing network is a system such as a LAN (Local Area Network), a WAN (Wide Area Network) such as the Internet, or a wireless communication network, and what is indicated by 4 is an optical fiber, ISDN line, or It means a transmission medium such as a wireless line. The transmission medium 4 is not particularly limited, but is connected to the computer devices 1, 2, and 3 representatively shown through a host computer device 5 and communication adapters 6, 7, 8 such as routers and terminal adapters. Yes.
The computer device 1 is not particularly limited, but has a processor (MPU) 9 to which a display controller (DISPC) 13, a network controller (NETC) 14, and a main memory (DRAM) 15 are connected. A floppy disk controller (FDC) 20, a keyboard controller (KEYC) 21, and an integrated device electronics controller (IDEC) 22 connected to the circuit are provided. The DISPC 13 performs drawing control on the video RAM (VRAM) 24 and controls display of the drawn display data on the display (DISP) 23. The NETC 14 is connected to the communication adapter 6 and performs buffering of transmission / reception information, communication protocol control, and the like. The DRAM 15 is used for a program area and a work area of the MPU 9. A floppy disk drive 16 is connected to the FDC 20 to read information from and write information to a floppy disk 25 which is an example of a recording medium. A keyboard 17 is connected to the KEYC 21. A hard disk drive (HDD) 18 and a CD-ROM drive (CDRD) 19 are connected to the IDEC 22. The HDD 18 has a magnetic disk which is another example of the recording medium. The CDRD 19 has a CD-ROM 26 which is still another example of the recording medium. Other computer apparatuses 2 and 3 are also configured in the same manner as described above.
When developing and designing a semiconductor integrated circuit using the computer apparatus 1, circuit design data such as a CPU provided by a floppy disk 25 or a CD-ROM 26 is read and temporarily stored in the hard disk drive device 18. At this time, the circuit data of the CPU described in FIG. 10 is stored in the floppy disk 25 and the CD-ROM 26, and the test program is stored. The test program may be provided not only via a recording medium such as the CD-ROM 26 but also via an information processing network. When designing a semiconductor integrated circuit using the computer device 1, by using the circuit data of the CPU 102 provided by the floppy disk 25 or the CD-ROM 26, an on-chip memory on the semiconductor integrated circuit can be efficiently used as described above. It is possible to shorten the development period of a semiconductor integrated circuit that can be tested quickly. That is, the design and development of a semiconductor integrated circuit using circuit data of the CPU 102 such as IP module data provided by the floppy disk 25 or the CD-ROM 26 can be facilitated. In the memory test for the on-chip memory of the semiconductor integrated circuit thus developed and manufactured, the test program provided on the floppy disk 25 or the CD-ROM 26 is loaded on the semiconductor integrated circuit, and the on-chip memory is loaded. The CPU may execute the test program. Since the on-chip CPU supports the repeat queue function of the instruction queue 103 as a memory test function and enables the branch instruction to be excluded from the test program, a memory test program optimized for the CPU hardware is provided. No need to develop from scratch. Thus, a user who develops a semiconductor integrated circuit using IP module data such as a CPU can improve the efficiency of the circuit design of the CPU and the test design for the on-chip memory, thereby improving the efficiency of the development and manufacturing of the semiconductor integrated circuit. it can.
Since the test program for the memory test is executed by an on-chip CPU, it can be described in an assembly language or the like used for CPU program development. Can be changed easily. Therefore, when providing the IP module data of the CPU, the user of the IP module data can easily cope with various memory tests only by providing a sample program or the like as a test program for the memory test. .
Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.
For example, the configurations of the instruction queue having the loop queue mode, the memory corresponding to the memory test mode, and the BIST module are not limited to the above example and can be changed as appropriate. For example, if the data bus is 32 bits and the instruction is 16 bits in fixed length, the instruction queue may prefetch the instructions in 16-bit units, but if the IR is 32 bits and latches two instructions together Accordingly, the instruction queue may prefetch instructions in units of 32 bits. Further, the operation control content in the loop queue mode of the instruction queue is not limited to the above. Furthermore, the on-chip module of the semiconductor integrated circuit is not limited to the above example and can be changed as appropriate. Further, the computer apparatus constituting the semiconductor integrated circuit development system is not limited to being connectable to a network, and may be used stand-alone.
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, since the instruction queue is operated as a loop queue, it is not necessary to use a branch instruction in order to repeatedly execute the same test program. The test program to be repeatedly executed may be repeatedly fetched from the instruction queue, and the memory read / write access for the memory test and the memory access for the instruction fetch do not compete on the bus. Therefore, branch instructions can be eliminated from the test program, and further, since it is not necessary to repeatedly fetch the same instruction from the bus connected to the CPU, it is possible to improve the test efficiency for the on-chip memory of the semiconductor integrated circuit. Become.
If CPU design data capable of setting the repeat queue mode is recorded and provided on a recording medium, the CPU can be designed using such design data, so that the on-chip memory can be efficiently tested. The development period of the semiconductor integrated circuit can be shortened.
By recording and providing a memory test program using a CPU developed with the design data together with the design data on a recording medium, the design and development of a semiconductor integrated circuit using the CPU can be facilitated. In the memory test for the on-chip memory of the semiconductor integrated circuit, the on-chip CPU only has to execute the test program. The circuit design of the CPU and the test design for the on-chip memory can be made efficient, and the development of the semiconductor integrated circuit is made efficient. be able to.
By having a comparison / determination circuit for memory testing as dedicated hardware separate from the CPU, comparison instructions for comparison / determination can be removed from the test program executed by the CPU. Test efficiency can be improved. If the read data to be compared and determined are guided to the comparison and determination circuit by the dedicated bus, it is possible to avoid a situation in which the write data for the memory test competes with the read data on the bus.
Industrial applicability
The present invention can be widely applied to a semiconductor integrated circuit such as a data processor, a microcomputer, or a single chip microcomputer incorporating a memory, and further to a test technique thereof.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a system LSI such as a microcomputer as an example of a semiconductor integrated circuit according to the present invention.
FIG. 2 is a block diagram illustrating in detail a connection state of circuit blocks related to the memory test.
FIG. 3 is a block diagram illustrating details of the BIST module.
FIG. 4 is an explanatory diagram of registers held by the register unit of the BIST module.
FIG. 5 is a block diagram illustrating the configuration of one page of the XY memory.
FIG. 6 is an explanatory diagram illustrating an address map of the general-purpose memory.
FIG. 7 is a logic circuit diagram illustrating the configuration of an enable control circuit for realizing the address map of FIG.
FIG. 8 is an explanatory diagram illustrating an address map of the XY memory.
FIG. 9 is a logic circuit diagram illustrating the configuration of an enable control circuit for realizing the address map of FIG.
FIG. 10 is a block diagram showing an example of a CPU.
FIG. 11 is a flowchart exemplifying a memory test procedure when the general-purpose memory is not relieved.
FIG. 12 is a flowchart exemplifying a memory test procedure when a general-purpose memory is relieved.
FIG. 13 is an explanatory diagram showing an instruction sequence for performing the 13N test in assembly language.
FIG. 14 is a timing chart of the CPU bus and the BIST dedicated data bus during execution of the phase L1 of the instruction sequence shown in FIG.
FIG. 15 is a block diagram illustrating a system LSI which is another example of the semiconductor integrated circuit according to the present invention.
FIG. 16 is an explanatory view showing a 13N test method which is one of the test sequences of the on-chip memory.
FIG. 17 is an explanatory diagram illustrating a test program for executing the L1 phase as a program according to a comparative example for performing the 13N test.
FIG. 18 is a timing chart of the bus connecting the CPU and the built-in memory when the test program according to the comparative example of FIG. 17 is arranged in the cache memory and the built-in memory test capable of one cycle access is executed.
FIG. 19 is a flow chart illustrating a procedure for developing and manufacturing a semiconductor integrated circuit having a self-test function as typified by FIG.
FIG. 20 is a block diagram showing an example of a semiconductor integrated circuit development system.

Claims (4)

A method for testing the memory of a semiconductor integrated circuit having a CPU having an instruction queue, a memory connected to the CPU via a bus, and a determination circuit connected to the memory and the bus,
The test program is stored in the instruction queue, the CPU executes the test program to perform memory write access and memory read access, the memory read access data is compared with the expected value by the determination circuit, and the test program is temporarily stored in the instruction queue. A memory test method, wherein fetching of a test program after being stored is repeatedly performed from an instruction queue instead of the bus. A semiconductor integrated circuit having a CPU, a memory, and a bus connecting the CPU and the memory in a semiconductor chip,
The CPU includes an instruction queue, an instruction queue, an instruction decoder that decodes an instruction supplied via the bus, and a control unit.
The instruction decoder decodes a predetermined repeat instruction and allows the control unit to repeat the fetch of the program to be repeated from the instruction queue after the program to be repeated is temporarily stored in the instruction queue. Can be set,
In the operation mode, the CPU further includes a determination circuit that inputs the data read from the memory when the CPU executes the program, and compares the logical value of the input data with an expected value. A semiconductor integrated circuit, characterized in that it can be output to the outside of a chip. 3. The semiconductor integrated circuit according to claim 2 , wherein a dedicated bus separated from the bus is provided as a path for supplying read data from the memory to the determination circuit. The memory has a plurality of memory blocks, and the memory blocks are mapped to the same address in response to the setting of the operation mode, and can be operated in parallel.
4. The semiconductor integrated circuit according to claim 3, wherein said determination circuit is capable of comparing and determining memory read data output in parallel from a plurality of memory blocks with an expected value in parallel.

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