JP2006287877A - Linearizer - Google Patents

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JP2006287877A
JP2006287877A JP2005108814A JP2005108814A JP2006287877A JP 2006287877 A JP2006287877 A JP 2006287877A JP 2005108814 A JP2005108814 A JP 2005108814A JP 2005108814 A JP2005108814 A JP 2005108814A JP 2006287877 A JP2006287877 A JP 2006287877A
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terminal
modulator
power
linearizer
baseband signal
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JP5049469B2 (en
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Tetsuya Kaneko
哲也 金子
Kunihiko Sakaihara
邦彦 酒井原
Yorihiro Kitamura
頼広 北村
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a linearizer capable of suppressing instantaneous spectrum spreading on a frequency axis by suppressing occurrence of an impulse-like DC voltage change in a baseband input of a modulator while maintaining power supply control due to burst operation of a circuit required for equipment even in a leading block or the like of burst transmission of a TDMA transmitter. <P>SOLUTION: Even in the leading block or the like of burst transmission of a TDMA transmitter, a switch 10 for electrically connecting or disconnecting a baseband signal input terminal 4 and a DC offset controllable terminal 7 is controlled in accordance with a burst timing, thereby suppressing the occurrence of an impulse-like DC voltage change in the baseband input of a modulator 28 and suppressing instantaneous spectrum spreading on a frequency axis. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、カーテシアンループ方式等のリニアライザに関する。   The present invention relates to a linearizer such as a Cartesian loop system.

従来、変調器や差動アンプで発生するDCオフセットによるスプリアスを抑えるために、変調器へ入力するベースバンド信号のDC値や、復調後の差動アンプの一方の素子のDC値を調整する方法が一般的に知られている。   Conventionally, in order to suppress spurious due to a DC offset generated in a modulator or a differential amplifier, a method of adjusting a DC value of a baseband signal input to the modulator or a DC value of one element of a differential amplifier after demodulation Is generally known.

図7は、従来の変調器でのDCオフセット調整を行うための回路構成例を示しており、この回路は、負荷抵抗1と、半導体素子2と、ローカル信号差動入力端子3と、ベースバンド信号入力端子4と、電流源5と、DCオフセット調整用可変電圧DC電源6と、DCオフセット調整用可変電圧DC電源接続端子7と、変調波差動出力端子8と、変調器28の主電源接続端子9とから構成されている。   FIG. 7 shows an example of a circuit configuration for performing DC offset adjustment in a conventional modulator. This circuit includes a load resistor 1, a semiconductor element 2, a local signal differential input terminal 3, and a baseband. Signal input terminal 4, current source 5, DC offset adjustment variable voltage DC power supply 6, DC offset adjustment variable voltage DC power supply connection terminal 7, modulated wave differential output terminal 8, and main power supply for modulator 28 The connection terminal 9 is comprised.

変調器出力に現れるスプリアスでDCオフセットに起因するものは、DCオフセット調整用可変電圧DC電源接続端子7に接続された、DCオフセット調整用可変電圧DC電源6のDC電圧を調整することで低減される。この時、ベースバンド信号入力端子4とDCオフセット調整用可変電圧DC電源6のDC電圧はほぼ等しくなる。また、通常想定されるDCオフセットの要因は、ベースバンド回路および変調器の半導体素子のベース・エミッタ間電位差や抵抗値の作成時のばらつき、それらの温度変化などである。   The spurious appearing in the modulator output and caused by the DC offset is reduced by adjusting the DC voltage of the DC offset adjusting variable voltage DC power source 6 connected to the DC offset adjusting variable voltage DC power source connection terminal 7. The At this time, the DC voltages of the baseband signal input terminal 4 and the DC offset adjusting variable voltage DC power source 6 are substantially equal. Also, the DC offset factor that is normally assumed is the base-emitter potential difference between the semiconductor elements of the baseband circuit and the modulator, variations in resistance value creation, temperature changes thereof, and the like.

負帰還ループにより送信系の非線形歪を補償するカーテシアンループ方式のリニアライザでは、ベースバンド信号入力端子4のDC電圧をローパスフィルタにより取り出し、それを基準電圧と比較して、その差分だけベースバンド信号入力端子4のDC電圧を補正するという適応DCオフセット補正が提案されている(例えば、特許文献1参照)。   In a Cartesian loop type linearizer that compensates for non-linear distortion of the transmission system by a negative feedback loop, a DC voltage at the baseband signal input terminal 4 is taken out by a low-pass filter, compared with a reference voltage, and a baseband signal input by the difference is obtained. An adaptive DC offset correction that corrects the DC voltage at the terminal 4 has been proposed (see, for example, Patent Document 1).

また、TDMA(Time Division Multiple Access)方式の無線機において、バースト送信時の送信オフ区間には低消費電力化や受信回路への送信機雑音低減のために、送信系の可変利得アンプやパワーアンプの電源を切ることが必要である。図8に示す、負帰還ループを作ってベースバンドにて歪補償を行うカーテシアン歪補償方式を用いた送信機の一例でも同様に、バースト送信時の送信オフ区間には可変利得アンプ34やパワーアンプ35を送信系主電源24から切り離すことが行われている。   Also, in a TDMA (Time Division Multiple Access) system radio, a variable gain amplifier or power amplifier of a transmission system is used in a transmission off section at the time of burst transmission in order to reduce power consumption and reduce transmitter noise to a receiving circuit. It is necessary to turn off the power. Similarly, in the example of the transmitter using the Cartesian distortion compensation method in which the negative feedback loop is formed and the distortion compensation is performed in the baseband shown in FIG. 8, the variable gain amplifier 34 and the power amplifier are used in the transmission off period at the time of burst transmission. 35 is disconnected from the transmission main power supply 24.

図8の送信機の基本的な動作を次に述べる。ベースバンド信号発生器21から出力された無歪の信号は、変調器28でローカル信号とミキシングされ、高周波の変調信号となり、可変利得アンプ34とパワーアンプ35を通る。この時、パワーアンプ35が非線形歪を発生してしまう。この歪を含んだ高周波信号の一部を方向性結合器36で抜き出し、可変減衰器33でレベル調整をした後、復調器32でベースバンド信号に変換する。この歪を含んだベースバンド信号を、減算器31にてベースバンド信号発生器21の無歪のベースバンド信号から減算することで、逆位相の歪成分だけを抽出する。エラーアンプ30で増幅されたエラー(逆位相の歪)は、加算器29にて、ベースバンド信号発生器21の無歪のベースバンド信号と加算される。すなわち、この信号はパワーアンプ35が発生する歪の逆特性を含んでおり、この信号で変調し、パワーアンプ35に通すことで、パワーアンプ35の非線形歪を補償している。   The basic operation of the transmitter of FIG. The undistorted signal output from the baseband signal generator 21 is mixed with the local signal by the modulator 28 to become a high-frequency modulated signal, and passes through the variable gain amplifier 34 and the power amplifier 35. At this time, the power amplifier 35 generates nonlinear distortion. A part of the high-frequency signal including the distortion is extracted by the directional coupler 36, the level is adjusted by the variable attenuator 33, and then converted to a baseband signal by the demodulator 32. By subtracting the baseband signal including the distortion from the undistorted baseband signal of the baseband signal generator 21 by the subtractor 31, only the distortion component having the opposite phase is extracted. The error (antiphase distortion) amplified by the error amplifier 30 is added to the undistorted baseband signal of the baseband signal generator 21 by the adder 29. That is, this signal includes an inverse characteristic of distortion generated by the power amplifier 35, and is modulated by this signal and passed through the power amplifier 35 to compensate for nonlinear distortion of the power amplifier 35.

しかし、カーテシアン歪補償方式において、可変利得アンプ34やパワーアンプ35の電源をオフにして帰還系40に入力される高周波電力を切ってしまった場合、閉ループとしては動作せず、回路は単純な帰還信号の反転増幅回路となる。この時、復調器32などを構成する半導体素子のインピーダンス変化により、安定した送信状態(DCオフセットが調整されている状態)から、帰還系の信号入力端子のDC値が僅かにずれてしまう。そして、この僅かなDC値のズレが、エラーアンプ30により増幅され、変調器28に入力される時には、安定した送信状態(DCオフセットが調整されている状態)から、大きくずれたDC値になってしまう。ここで、再び、可変利得アンプ34やパワーアンプ35の電源をオンにし送信状態に入った場合、再び閉ループが構成され帰還系には、安定した送信状態(DCオフセットが調整されている状態)にあるべき高周波電力が入力され、増幅された誤差(大きくずれた)DC値がループの応答速度に応じて極短時間に、安定した送信状態の時のDC値に遷移する(引き戻される)。   However, in the Cartesian distortion compensation method, when the high-frequency power input to the feedback system 40 is turned off by turning off the power of the variable gain amplifier 34 or the power amplifier 35, the circuit does not operate as a closed loop, and the circuit is simply fed back. It becomes a signal inverting amplifier circuit. At this time, the DC value of the signal input terminal of the feedback system slightly shifts from a stable transmission state (a state in which the DC offset is adjusted) due to a change in impedance of the semiconductor elements constituting the demodulator 32 and the like. When this slight DC value deviation is amplified by the error amplifier 30 and input to the modulator 28, the DC value greatly deviates from the stable transmission state (the state in which the DC offset is adjusted). End up. Here, when the variable gain amplifier 34 and the power amplifier 35 are turned on again to enter the transmission state, a closed loop is formed again, and the feedback system is in a stable transmission state (a state where the DC offset is adjusted). The desired high-frequency power is input, and the amplified error (shifted greatly) DC value is changed (returned) to the DC value in the stable transmission state in a very short time according to the response speed of the loop.

なお、送信系主電源24とパワーアンプ35との間には、送信機制御装置20より出力されるパワーアンプ電源用制御信号22によってオン/オフされるパワーアンプ電源用スイッチ26が設けられており、送信系主電源24と可変利得アンプ34との間には、送信機制御装置20より出力される可変利得アンプ電源用制御信号23によってオン/オフされる可変利得アンプ電源用スイッチ27が設けられている。また、方向性結合器36は、アイソレータ37及び送受切替用高周波スイッチ38を介してアンテナ39に接続されている。   A power amplifier power switch 26 that is turned on / off by a power amplifier power control signal 22 output from the transmitter controller 20 is provided between the transmission main power supply 24 and the power amplifier 35. Between the transmission main power supply 24 and the variable gain amplifier 34, there is provided a variable gain amplifier power switch 27 which is turned on / off by a variable gain amplifier power control signal 23 output from the transmitter control device 20. ing. The directional coupler 36 is connected to an antenna 39 through an isolator 37 and a transmission / reception switching high-frequency switch 38.

この時の、変調器のベースバンド入力の時間的な変化を図9に示す。DC値が大きく変化する動きは、変調器のベースバンド入力に、インパルスを入れた時と同じ現象であり、その遷移過程での波形は本来の通信用の信号としての帯域制限を全く受けず、その瞬間、周波数軸上に図10のようにスペクトラムの拡がりを発生させてしまう。このような変化に対応するために、可変利得アンプ34の立ち上がりやベースバンド信号の立ち上がりをなまらせる方法(ランピング)も考えられる。   FIG. 9 shows a temporal change in the baseband input of the modulator at this time. The movement in which the DC value greatly changes is the same phenomenon as when an impulse is input to the baseband input of the modulator, and the waveform in the transition process is not subject to any band limitation as an original communication signal, At that moment, spectrum spread occurs on the frequency axis as shown in FIG. In order to cope with such a change, a method (ramping) for smoothing the rising of the variable gain amplifier 34 or the rising of the baseband signal is also conceivable.

特開2001−333124号公報JP 2001-333124 A

しかし、前述のカーテシアンループ方式のリニアライザにおいては、適応的にDC値のズレを押さえ込もうとするが、差動アンプなどの付加回路が多いために追従速度が遅く、温度変化や経時変化によるゆっくりとしたオフセット変動には追従できても、TDMA送信機のバースト送信の先頭区間などでは、極短期間で、かつ大きなDCオフセットのズレを補正することができず、その期間にスプリアスを輻射してしまうという欠点があった。また、ローパスフィルタや比較器などの制御手段も必要となるため、装置が大きくなると言う欠点があった。   However, the above-mentioned Cartesian loop type linearizer adaptively tries to suppress the deviation of the DC value, but the follow-up speed is slow because there are many additional circuits such as a differential amplifier, and it is slow due to temperature changes and changes over time. Even if the offset fluctuation can be followed, in the first section of burst transmission of the TDMA transmitter, etc., it is not possible to correct the deviation of a large DC offset in a very short period, and spurious is radiated during that period. There was a drawback of end. Further, since control means such as a low-pass filter and a comparator are required, there is a drawback that the apparatus becomes large.

また、可変利得アンプ34の立ち上がりやベースバンド信号の立ち上がりをなまらせる方法(ランピング)の場合、信号処理側で変調信号帯域幅に合わせた波形の最適化制御など条件分けした制御(余計な制御)が必要になり、負帰還ループ設計の帯域以下の信号であれば同一の制御での閉ループ動作ができるという方式の特質を損ねてしまう。また、閉ループ時の収束精度であり、歪み改善量そのものであるエラーアンプ34の利得が大きいほど、ズレ量は大きくなり、スペクトラムの拡がりが大きくなる。それを抑えるためにベースバンド信号もしくはアンプの利得や電源の立ち上がりをなまらせてしまうと、必要な信号の先頭部分の情報が欠けてしまう可能性が出てくる。すなわち、極短時間で大きなDC電圧変動をランピングなど既存の手法で吸収するには無理がある。   In the case of a method (ramping) in which the rise of the variable gain amplifier 34 and the rise of the baseband signal are smoothed (ramping), control according to conditions (extra control) such as waveform optimization control in accordance with the modulation signal bandwidth on the signal processing side. Therefore, if the signal is within the band of the negative feedback loop design, the characteristic of the system that the closed loop operation with the same control can be performed is impaired. Further, as the gain of the error amplifier 34, which is the convergence accuracy in the closed loop and is the distortion improvement amount itself, increases, the amount of deviation increases and the spread of the spectrum increases. If the baseband signal or the gain of the amplifier or the rise of the power supply is slowed down in order to suppress it, there is a possibility that the information at the beginning of the necessary signal is lost. In other words, it is impossible to absorb a large DC voltage fluctuation in an extremely short time using an existing method such as ramping.

本発明は、係る事情に鑑みてなされたものであり、TDMA送信機のバースト送信の先頭区間などでも、機器に必要な回路のバースト動作による前述の電源制御を維持しつつ、変調器のベースバンド入力での、インパルス的なDC電圧変化の発生を抑制し、瞬間的な周波数軸上のスペクトラムの拡がりを抑圧することができるリニアライザを提供することを目的とする。   The present invention has been made in view of such circumstances, and the baseband of the modulator is maintained while maintaining the above-described power control by the burst operation of the circuit necessary for the device even in the head section of the burst transmission of the TDMA transmitter. An object of the present invention is to provide a linearizer that can suppress the occurrence of an impulse DC voltage change at the input and suppress the spread of the spectrum on the instantaneous frequency axis.

上記目的は下記構成により達成される。
(1) リニアライザであって、ベースバンド信号入力端子とDCオフセット調整可能な端子とを有する変調手段と、前記ベースバンド信号入力端子と前記DCオフセット調整可能な端子とを電気的に接続または切断する端子接続切断手段と、前記端子接続切断手段を制御する制御手段と、を具備する。
The above object is achieved by the following configuration.
(1) A linearizer that electrically connects or disconnects a modulation means having a baseband signal input terminal and a DC offset adjustable terminal, and the baseband signal input terminal and the DC offset adjustable terminal. Terminal connection cutting means, and control means for controlling the terminal connection cutting means.

(2) 上記(1)に記載のリニアライザにおいて、カーテシアンループの電源回路を制御する電源制御手段を具備し、前記電源制御手段と前記端子接続切断手段を制御する制御手段とを同期または所定の時間差にて制御する。 (2) The linearizer according to (1), further comprising power control means for controlling the power circuit of the Cartesian loop, wherein the power control means and the control means for controlling the terminal connection disconnecting means are synchronized or have a predetermined time difference. Control with.

上記(1)に記載のリニアライザでは、TDMA送信機のバースト送信の先頭区間などでも、バーストタイミングに合わせて、ベースバンド信号入力端子とDCオフセット調整可能な端子とを電気的に接続または切断する端子接続切断手段を制御することで、変調器のベースバンド入力での、インパルス的なDC電圧変化の発生を抑制し、瞬間的な周波数軸上のスペクトラムの拡がりを抑圧することができる。   In the linearizer described in (1) above, a terminal for electrically connecting or disconnecting a baseband signal input terminal and a terminal capable of adjusting a DC offset in accordance with the burst timing even in the first section of burst transmission of a TDMA transmitter By controlling the connection disconnection means, it is possible to suppress the occurrence of an impulse DC voltage change at the baseband input of the modulator, and to suppress the spread of the spectrum on the instantaneous frequency axis.

上記(2)に記載のリニアライザでは、カーテシアンループの電源回路を、ベースバンド信号入力端子とDCオフセット調整可能な端子とを電気的に接続または切断する端子接続切断手段を制御する制御手段を同期または所定の時間差にて制御することで、瞬間的な周波数軸上のスペクトラムの拡がりを抑圧するだけではなく、非送信時の低消費電力化を実現することができる。   In the linearizer described in the above (2), the power supply circuit of the Cartesian loop is synchronized with the control means for controlling the terminal connection cutting means for electrically connecting or disconnecting the baseband signal input terminal and the DC offset adjustable terminal. By controlling at a predetermined time difference, not only the instantaneous spread of the spectrum on the frequency axis can be suppressed, but also a reduction in power consumption during non-transmission can be realized.

以下、本発明を実施するための好適な実施の形態について、図面を参照して詳細に説明する。   DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments for carrying out the invention will be described in detail with reference to the drawings.

(実施の形態1)
図1は、本発明の実施の形態1に係るカーテシアンループ方式のリニアライザの構成を示す回路図である。この図において、本実施の形態のカーテシアンループ方式のリニアライザは、負荷抵抗1と、半導体素子2と、ローカル信号差動入力端子3と、ベースバンド信号入力端子4と、電流源5と、DCオフセット調整用可変電圧DC電源6と、DCオフセット調整用可変電圧DC電源接続端子7と、変調波差動出力端子8と、変調器(変調手段)28の主電源接続端子9と、スイッチ(端子接続切断手段)10と、送信機制御装置(制御手段)20と、スイッチ10の制御信号25から構成されている。
(Embodiment 1)
FIG. 1 is a circuit diagram showing a configuration of a Cartesian loop type linearizer according to Embodiment 1 of the present invention. In this figure, the Cartesian loop type linearizer of the present embodiment includes a load resistor 1, a semiconductor element 2, a local signal differential input terminal 3, a baseband signal input terminal 4, a current source 5, and a DC offset. Adjustable variable voltage DC power supply 6, DC offset adjusting variable voltage DC power supply connection terminal 7, modulated wave differential output terminal 8, main power supply connection terminal 9 of modulator (modulation means) 28, and switch (terminal connection) (Cutting means) 10, a transmitter control device (control means) 20, and a control signal 25 of the switch 10.

従来では、カーテシアンループ方式のリニアライザで送信系の可変利得アンプやパワーアンプの電源を切ると、図9の送信オフ区間のようにDC電圧が大きくずれ、次の送信オン時に、図10のようなスプリアスを出していたが、本実施の形態では、スイッチ10を送信オフ区間に強制的にショート(電気的接続状態)にすることで、ベースバンド信号入力端子4は、調整後のDC値に切り替えられてしまうため、図3のように送信オフ区間と送信オン区間のDC電圧のズレは発生しない。すなわち、スペクトラムの拡がりは図4のように抑制される。   Conventionally, when the transmission variable gain amplifier or power amplifier is turned off with a Cartesian loop type linearizer, the DC voltage is greatly shifted as shown in the transmission off section of FIG. In this embodiment, the spurious signal is output. In this embodiment, the baseband signal input terminal 4 is switched to the adjusted DC value by forcibly shorting the switch 10 to the transmission-off interval (electrical connection state). Therefore, the DC voltage difference between the transmission off period and the transmission on period does not occur as shown in FIG. That is, the spread of the spectrum is suppressed as shown in FIG.

図2は、図1のカーテシアンループ方式のリニアライザを用いたカーテシアン歪補償送信機の構成例を示すブロック図である。なお、図2において、前述した図8と共通する構成部分には同一符号を付してその説明を省略する。また、図2に示したカーテシアン歪補償送信機の構成例は、送信機制御装置20より出力されるスイッチ10の制御信号25が変調器28(スイッチ10)に供給されるという点で図8のものとは異なっている。   FIG. 2 is a block diagram showing a configuration example of a Cartesian distortion compensating transmitter using the Cartesian loop type linearizer of FIG. In FIG. 2, the same components as those in FIG. 8 described above are denoted by the same reference numerals, and description thereof is omitted. The configuration example of the Cartesian distortion compensation transmitter shown in FIG. 2 is that the control signal 25 of the switch 10 output from the transmitter controller 20 is supplied to the modulator 28 (switch 10). It is different from the thing.

このような本実施の形態のカーテシアンループ方式のリニアライザによれば、TDMA送信機のバースト送信の先頭区間などでも、バーストタイミングに合わせて、ベースバンド信号入力端子4とDCオフセット調整可能な端子7とを電気的に接続または切断するスイッチ10を送信機制御装置20で制御することで、変調器28のベースバンド入力での、インパルス的なDC電圧変化の発生を抑制し、瞬間的な周波数軸上のスペクトラムの拡がりを抑圧することができる。   According to the Cartesian loop type linearizer of this embodiment, the baseband signal input terminal 4 and the DC offset adjustable terminal 7 can be adjusted in accordance with the burst timing even in the first section of burst transmission of the TDMA transmitter. By controlling the switch 10 that electrically connects or disconnects the transmitter 10 with the transmitter control device 20, the occurrence of an impulsive DC voltage change at the baseband input of the modulator 28 is suppressed, and the instantaneous frequency axis is changed. The spread of the spectrum can be suppressed.

(実施の形態2)
図5は、本発明の実施の形態2に係るカーテシアンループ方式のリニアライザの構成を示す回路図である。基本的な回路構成は図1と同じであるが、スイッチ10を制御する制御信号に送信機制御装置20より出力される可変利得アンプ電源用制御信号23を使用しているところに違いがある。送信オフ区間にスイッチ10が接続(オン)されるのに同期して、可変利得アンプの電源を切ることで、スペクトラムの拡がりを抑えつつ、送信時の消費電力を下げようとするものである。
(Embodiment 2)
FIG. 5 is a circuit diagram showing a configuration of a Cartesian loop type linearizer according to Embodiment 2 of the present invention. The basic circuit configuration is the same as in FIG. 1 except that a variable gain amplifier power control signal 23 output from the transmitter controller 20 is used as a control signal for controlling the switch 10. In synchronization with the switch 10 being connected (turned on) during the transmission off period, the power of the variable gain amplifier is turned off to reduce the power consumption during transmission while suppressing the spread of the spectrum.

図6は、図5のカーテシアンループ方式のリニアライザを用いたカーテシアン歪補償送信機の構成例を示すブロック図である。なお、図6において、前述した図8と共通する構成部分には同一符号を付してその説明を省略する。また、図6に示したカーテシアン歪補償送信機の構成例は、送信機制御装置20より出力される可変利得アンプ電源用制御信号23が変調器28(スイッチ10)に供給されるという点で図8のものとは異なっている。   FIG. 6 is a block diagram showing a configuration example of a Cartesian distortion compensating transmitter using the Cartesian loop type linearizer of FIG. In FIG. 6, the same components as those in FIG. 8 described above are denoted by the same reference numerals, and description thereof is omitted. Further, the configuration example of the Cartesian distortion compensation transmitter shown in FIG. 6 is illustrated in that the variable gain amplifier power control signal 23 output from the transmitter controller 20 is supplied to the modulator 28 (switch 10). It is different from eight.

このような本実施の形態のカーテシアンループ方式のリニアライザによれば、カーテシアンループの全てもしくは一部の電源回路を、ベースバンド信号入力端子4とDCオフセット調整可能な端子7とを電気的に接続または切断する手段を制御する電源制御手段と同期または所定の時間差にて制御することで、瞬間的な周波数軸上のスペクトラムの拡がりを抑圧するだけではなく、非送信時の低消費電力化を実現することができる。   According to the Cartesian loop type linearizer of this embodiment, all or a part of the power circuit of the Cartesian loop is electrically connected to the baseband signal input terminal 4 and the DC offset adjustable terminal 7 or By controlling in synchronization with the power supply control means that controls the means for cutting or with a predetermined time difference, not only suppresses the spread of the spectrum on the frequency axis instantaneously, but also realizes low power consumption during non-transmission. be able to.

本発明は、TDMA送信機のバースト送信の先頭区間などでも、バーストタイミングに合わせて、ベースバンド信号入力端子とDCオフセット調整可能な端子とを電気的に接続または切断する端子接続切断手段を制御することで、変調器のベースバンド入力での、インパルス的なDC電圧変化の発生を抑制し、瞬間的な周波数軸上のスペクトラムの拡がりを抑圧することができるという効果を有し、カーテシアン歪補償送信機などに用いて有用である。   The present invention controls terminal connection / cutting means for electrically connecting or disconnecting a baseband signal input terminal and a terminal capable of adjusting a DC offset in accordance with the burst timing even in a burst transmission head section of a TDMA transmitter. Thus, it is possible to suppress the occurrence of an impulse DC voltage change at the baseband input of the modulator, and to suppress the spread of the spectrum on the instantaneous frequency axis. Useful for machine etc.

本発明の実施の形態1に係るカーテシアンループ方式のリニアライザの構成を示す回路図1 is a circuit diagram showing a configuration of a Cartesian loop type linearizer according to Embodiment 1 of the present invention; 図1のカーテシアンループ方式のリニアライザを用いたカーテシアン歪補償送信機の構成例を示すブロック図1 is a block diagram showing a configuration example of a Cartesian distortion compensation transmitter using the Cartesian loop linearizer of FIG. 本発明を用いた場合の変調器入力信号の時間変化を示す図The figure which shows the time change of the modulator input signal at the time of using this invention 本発明を用いた場合の送信機出力(DC急変なし)を示す図The figure which shows the transmitter output (no DC sudden change) at the time of using this invention 本発明の実施の形態2に係るカーテシアンループ方式のリニアライザの構成を示す回路図A circuit diagram showing composition of a Cartesian loop type linearizer concerning Embodiment 2 of the present invention 図5のカーテシアンループ方式のリニアライザを用いたカーテシアン歪補償送信機の構成例を示すブロック図FIG. 5 is a block diagram showing a configuration example of a Cartesian distortion compensation transmitter using the Cartesian loop linearizer of FIG. 従来のカーテシアンループ方式のリニアライザの構成を示す回路図Circuit diagram showing the configuration of a conventional Cartesian loop linearizer 図7のカーテシアンループ方式のリニアライザを用いたカーテシアン歪補償送信機の構成例を示すブロック図FIG. 7 is a block diagram showing a configuration example of a Cartesian distortion compensation transmitter using the Cartesian loop linearizer of FIG. 本発明を用いない場合の変調器入力信号の時間変化を示す図The figure which shows the time change of the modulator input signal when not using this invention 本発明を用いない場合の送信機出力(DC急変あり)を示す図The figure which shows the transmitter output (with DC sudden change) when not using this invention

符号の説明Explanation of symbols

1 負荷抵抗
2 半導体素子
3 ローカル信号差動入力端子
4 ベースバンド信号入力端子
5 電流源
6 DCオフセット調整用可変電圧DC電源
7 DCオフセット調整用可変電圧DC電源接続端子
8 変調波差動出力端子
9 変調器の主電源接続端子
10 スイッチ
20 送信機制御装置
21 ベースバンド信号発生器
22 パワーアンプ電源用制御信号
23 可変利得アンプ電源用制御信号
24 送信系主電源
25 スイッチ10の制御信号
26 パワーアンプ電源用スイッチ
27 可変利得アンプ電源用スイッチ
28 変調器
29 加算器
30 エラーアンプ
31 減算器
32 復調器
33 可変減衰器
34 可変利得アンプ
35 パワーアンプ
36 方向性結合器
37 アイソレータ
38 送受切替用高周波スイッチ
39 アンテナ
40 帰還系
DESCRIPTION OF SYMBOLS 1 Load resistance 2 Semiconductor element 3 Local signal differential input terminal 4 Baseband signal input terminal 5 Current source 6 DC offset adjustment variable voltage DC power supply 7 DC offset adjustment variable voltage DC power supply connection terminal 8 Modulation wave differential output terminal 9 Modulator main power supply connection terminal 10 Switch 20 Transmitter control device 21 Baseband signal generator 22 Power amplifier power supply control signal 23 Variable gain amplifier power supply control signal 24 Transmission system main power supply 25 Switch 10 control signal 26 Power amplifier power supply Switch 27 variable gain amplifier power switch 28 modulator 29 adder 30 error amplifier 31 subtractor 32 demodulator 33 variable attenuator 34 variable gain amplifier 35 power amplifier 36 directional coupler 37 isolator 38 transmission / reception switching high-frequency switch 39 antenna 40 Return system

Claims (2)

ベースバンド信号入力端子とDCオフセット調整可能な端子とを有する変調手段と、
前記ベースバンド信号入力端子と前記DCオフセット調整可能な端子とを電気的に接続または切断する端子接続切断手段と、
前記端子接続切断手段を制御する制御手段と、
を具備するリニアライザ。
Modulation means having a baseband signal input terminal and a DC offset adjustable terminal;
A terminal connection cutting means for electrically connecting or disconnecting the baseband signal input terminal and the DC offset adjustable terminal;
Control means for controlling the terminal connection cutting means;
A linearizer comprising:
カーテシアンループの電源回路を制御する電源制御手段を具備し、前記電源制御手段と前記端子接続切断手段を制御する制御手段とを同期または所定の時間差にて制御する請求項1に記載のリニアライザ。   2. The linearizer according to claim 1, further comprising a power control unit that controls a power circuit of a Cartesian loop, wherein the power control unit and the control unit that controls the terminal connection cutting unit are controlled synchronously or at a predetermined time difference.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010045629A (en) * 2008-08-13 2010-02-25 Fujitsu Ltd Digital distortion compensation device
CN108449096A (en) * 2018-03-26 2018-08-24 华南理工大学 A kind of pre-distortion method and system based on parallel-connection structure

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07162466A (en) * 1993-10-14 1995-06-23 Kyocera Corp Tdma quadrature modulating method
JPH07202961A (en) * 1993-12-29 1995-08-04 Toshiba Corp Transmitter
JP2001016283A (en) * 1999-07-01 2001-01-19 Fujitsu General Ltd Digital radio equipment
JP2001024728A (en) * 1999-07-02 2001-01-26 Nec Corp Quadrature modulator, mobile communication machine provided with the same, and communication system
JP2002319989A (en) * 2001-04-19 2002-10-31 Matsushita Electric Ind Co Ltd Dc offset and phase correcting device and radio communication device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07162466A (en) * 1993-10-14 1995-06-23 Kyocera Corp Tdma quadrature modulating method
JPH07202961A (en) * 1993-12-29 1995-08-04 Toshiba Corp Transmitter
JP2001016283A (en) * 1999-07-01 2001-01-19 Fujitsu General Ltd Digital radio equipment
JP2001024728A (en) * 1999-07-02 2001-01-26 Nec Corp Quadrature modulator, mobile communication machine provided with the same, and communication system
JP2002319989A (en) * 2001-04-19 2002-10-31 Matsushita Electric Ind Co Ltd Dc offset and phase correcting device and radio communication device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010045629A (en) * 2008-08-13 2010-02-25 Fujitsu Ltd Digital distortion compensation device
CN108449096A (en) * 2018-03-26 2018-08-24 华南理工大学 A kind of pre-distortion method and system based on parallel-connection structure
CN108449096B (en) * 2018-03-26 2020-02-18 华南理工大学 Pre-distortion processing method and system based on parallel structure

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