JP2006287240A - Process for fabricating semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for obtaining a TFT in which variation in characteristics of the element is suppressed. <P>SOLUTION: A crystalline semiconductor film is formed using a metal element for accelerating crystallization of a semiconductor film, a mask is formed on the crystalline semiconductor film which is then doped selectively with an impurity element, and the region doped with the metal element is subjected to gettering by first heat treatment. After the region doped by using the same mask is removed, the crystalline semiconductor film is processed to form an insular semiconductor film which is then subjected to side etching by using the same mask as it is. Subsequently, a gate insulating film and a gate electrode are formed on the insular semiconductor film which is then doped with the impurity element through the gate insulating film by using the gate electrode, and the region doped with metal element is subjected to gettering by second heat treatment. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The invention disclosed in this specification relates to a thin film transistor and a manufacturing method thereof. Alternatively, the present invention relates to a circuit or a device formed using a thin film transistor.

  A thin film transistor (hereinafter referred to as TFT) using a thin film semiconductor is known. This is a structure in which a thin film semiconductor, particularly a silicon semiconductor film, is formed on a substrate, and this thin film semiconductor is used.

  TFTs are used in various integrated circuits, but are particularly used in active matrix liquid crystal display devices.

  An active matrix liquid crystal display device has a structure in which TFTs are arranged as switching elements on each of pixel electrodes arranged in a matrix.

  In addition to the matrix circuit, a peripheral drive circuit including TFTs (called a peripheral drive circuit integrated type) is also known.

  Other applications of the TFT include various integrated circuits and multilayer structure integrated circuits (stereoscopic ICs).

  As a silicon film used for the TFT, it is easy to use an amorphous silicon film formed by a vapor phase method such as a plasma CVD method. It can be said that this technology is almost established.

  However, a TFT using an amorphous silicon film has a much lower electrical characteristic than that using a single crystal semiconductor used in a general semiconductor integrated circuit. For this reason, it can be used only for limited applications such as switching elements of active matrix circuits.

  As a future technical trend, there is a demand for a configuration in which an active matrix circuit and a peripheral drive circuit, a circuit for performing image processing, an oscillation circuit, and the like are integrated on the same substrate.

  In order to improve the characteristics of a TFT using an amorphous silicon film, a crystalline silicon film may be used instead of an amorphous silicon film.

  A silicon film having crystallinity other than single crystal silicon is called polycrystalline silicon, polysilicon, microcrystalline silicon, or the like.

  In order to obtain a silicon film having such crystallinity, an amorphous silicon film is first formed and then crystallized by heating (thermal annealing). This method is called a solid phase growth method because the amorphous state changes to a crystalline state while maintaining a solid state.

  However, the solid phase growth of silicon requires a heating temperature of 600 ° C. or more and a time of 20 hours or more, and there is a problem that it is difficult to use an inexpensive glass substrate as the substrate.

  For example, Corning 7059 glass used in an active liquid crystal display device has a glass strain point of 593 ° C., and considering the increase in area of the substrate, there is a problem in performing thermal annealing at 600 ° C. or higher for a long time.

  In addition, the fact that the heat treatment time for performing crystallization takes 20 hours or more is problematic in terms of productivity.

  In response to such a problem, the present inventors have developed the following technology. This means that a small amount of a certain metal element such as nickel or palladium is deposited on the surface of the amorphous silicon film, and then heated, so that crystallization can be performed in a processing time of about 550 ° C. for about 4 hours. Is. (Japanese Patent Laid-Open No. 6-244103)

  Of course, if annealing is performed at 600 ° C. for 4 hours, a silicon film with better crystallinity can be obtained.

  According to this technique, it is possible to obtain a crystalline silicon film having a large area on an inexpensive glass substrate with high productivity.

  In order to introduce such a trace amount of metal element (metal element that promotes crystallization), a method of depositing a film of the metal element or a compound thereof by sputtering (JP-A-6-244104), spin coating, etc. A method of forming a film of a metal element or a compound thereof by means (Japanese Patent Laid-Open No. 7-130552), and a method of forming a film by decomposing a gas containing a metal element by means of thermal decomposition, plasma decomposition, etc. -335548).

  In addition, by selectively introducing a metal element into a specific portion and then heating, the crystal growth is expanded from the portion where the metal element is introduced to the surroundings (lateral growth method or lateral growth method). You can also. Crystalline silicon obtained by such a method has directionality in the crystal structure, and exhibits extremely excellent characteristics depending on the directionality.

  As described above, the method for manufacturing a crystalline silicon film using a certain metal element (for example, nickel) is very excellent. However, it has been found that when a TFT is manufactured using the crystalline silicon film, there are problems such as variations in element characteristics and low reliability.

  An object of the invention disclosed in this specification is to provide a technique for obtaining a TFT with little variation in element characteristics when a TFT is obtained using a crystalline silicon film obtained using a metal element.

  By using the invention disclosed in this specification, it is possible to provide a technique for obtaining a TFT with little variation in element characteristics when a TFT is obtained using a crystalline silicon film obtained using a metal element. it can.

One of the inventions disclosed in this specification is:
As shown in FIG. 1 and FIG.
Forming a crystalline silicon film 107 on the insulating surface using a metal element that promotes crystallization of silicon (FIGS. 1A and 1B);
Forming a mask 109 on the crystalline silicon film (FIG. 1C);
Using the mask to getter the metal element to specific regions 111 and 112 of the crystalline silicon film (FIG. 2E);
A step of forming an active layer 116 of the device using the mask 109 (side etching is performed to 115) (FIG. 2H);
It is characterized by having.

Other aspects of the invention are:
Forming a crystalline silicon film on the insulating surface using a metal element that promotes crystallization of silicon;
Forming a mask on the crystalline silicon film;
Selectively doping the crystalline silicon film with an element selected from nitrogen, phosphorus, arsenic, antimony, and bismuth using the mask;
Applying heat treatment to getter the metal element into the doped region;
Removing the doped region using the mask;
It is characterized by having.

  In the above configuration, the most effective dopant is phosphorus.

Other aspects of the invention are:
Forming a crystalline silicon film on the insulating surface using a metal element that promotes crystallization of silicon;
Forming a mask on the crystalline silicon film;
Selectively doping the crystalline silicon film with an element selected from nitrogen, phosphorus, arsenic, antimony, and bismuth using the mask;
Applying heat treatment to getter the metal element into the doped region;
Forming an active layer of the device using the gettered region using the mask;
It is characterized by having.

The structure of another invention is as shown in FIG. 1 and FIG.
Forming a crystalline silicon film 107 on the insulating surface using a metal element that promotes crystallization of silicon (FIGS. 1A and 1B);
A step of forming a mask 109 on the crystalline silicon film 107 (FIG. 1C), and using the mask 109 for the crystalline silicon film, selected from nitrogen, phosphorus, arsenic, antimony, and bismuth. A step of selectively doping the element (in this case phosphorus) (FIG. 1D);
Performing a heat treatment to getter the metal element to the doped regions 111 and 112 (FIG. 2E);
A step (FIG. 2H) of etching a region adjacent to the doped region of the gettered region using the mask 113 in a self-aligning manner (FIG. 2H).

  The above process is characterized in that phosphorus is doped using the mask 109 and a pattern indicated by 116 is obtained using a side-etched mask 109 (indicated by 115).

  By doing so, the region adjacent to 111 and 112 of 113 can be removed, and the influence of nickel element on the region of 116 can be suppressed.

  In the invention disclosed in this specification, it is most preferable to use Ni (nickel) as a metal element that promotes crystallization of silicon.

  As the metal element for promoting the crystallization of silicon, one or more kinds selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au can be used.

Further, a compound film represented by Si _x Ge _1-X (0 <x <1) can be used instead of the crystalline silicon film.

In this case, the amorphous silicon film as a starting film may be a compound film represented by Si _x Ge _1-X (0 <x <1).

  1 to 3 show a manufacturing process of this embodiment. First, as shown in FIG. 1A, a silicon oxide film is formed as a base film on a glass substrate 101 to a thickness of 300 nm by plasma CVD or sputtering.

  Next, an amorphous silicon film 103 is formed to a thickness of 50 nm by low pressure thermal CVD. The film thickness of the amorphous silicon film may be selected from a range of about 20 to 100 nm.

In addition to the amorphous silicon film, a silicon-containing compound represented by Si _x Ge _1-x (0 <x <1) can be used.

  Further, a silicon oxide film (not shown) is formed to a thickness of 120 nm by plasma CVD. Then, a mask indicated by 104 is formed by patterning this silicon oxide film.

  In this mask, a slit-like opening 105 is formed. The opening 105 has an elongated shape having a longitudinal shape in the depth direction from the front side of the drawing. (Fig. 1 (A))

  Next, a nickel acetate solution containing nickel at a concentration of 10 ppm (weight conversion) is applied, and the excess solution is removed by a spinner.

  In this way, a state is obtained in which the nickel element is held in contact with the surface of the sample as indicated by 106 in FIG.

  In the state of FIG. 1A, the nickel element is selectively held in contact with the surface of the amorphous silicon film 103 in the region of the opening 105.

  As a method for introducing nickel, there are a plasma CVD method, a sputtering method, a plasma treatment by discharge from an electrode containing nickel, a gas adsorption method, an ion implantation method, and the like.

  Next, this sample is heat-treated in a nitrogen atmosphere at 600 ° C. for 4 hours. In this step, nickel element diffuses into the amorphous silicon film from the region where the opening 105 is provided, and crystallization proceeds as indicated by the arrow 106 accordingly.

  This crystallization is observed as a peculiar thing progressing along a direction parallel to the substrate. (Fig. 1 (B))

  In this way, a crystalline silicon film 107 having crystal growth in a direction parallel to the substrate as indicated by 106 is obtained.

  What is necessary is just to select the heating conditions for said crystallization from the range of about 550 degreeC-700 degreeC. When nickel element is used, the effect of increasing the heating temperature is not so high.

  When crystallization is completed, the mask 104 made of a silicon oxide film is removed. Next, the silicon film is annealed by irradiation with infrared light. In this step, defects in a region where crystallization has progressed are reduced and crystallinity is increased.

  Further, an excimer laser in the ultraviolet region may be irradiated instead of infrared light. The laser light irradiation promotes a non-equilibrium state in the film and has an effect of making the nickel element move easily. Of course, it also has the effect of promoting crystallization.

  Next, a silicon oxide film and a silicon nitride film (not shown) are formed by plasma CVD. Each film thickness is 200 nm.

  Then, as shown in FIG. 1C, a resist mask 108 is formed, and the silicon oxide film and the silicon nitride film previously formed are patterned by a dry etching method.

  Thus, a state in which the silicon oxide film pattern 109 and the silicon nitride film pattern 110 are laminated is obtained. This stacked pattern is formed on a region where the growth indicated by 107 is performed. (Figure 1 (C))

  Next, as shown in FIG. 1D, phosphorus is doped on the surface of the exposed silicon film. Here, phosphorus ions are acceleratedly implanted into the regions 111 and 112 by plasma doping.

Here, an example in which doping is performed by a method of accelerated implantation of phosphorus ions is shown, but the following methods can be adopted as other doping methods.
(1) A film containing phosphorus is formed, and laser annealing or heat treatment is performed.
(2) A film containing phosphorus is formed by applying a solution such as a PSG film, and laser annealing or heat treatment is performed.
(3) Laser annealing is performed in an atmosphere containing phosphorus.

  Next, heat treatment is performed. This heat treatment is performed in a nitrogen atmosphere at 600 ° C. for 2 hours. This heat treatment can be selected from the range of 400 ° C. to the strain point of the substrate. Generally, it may be selected from a range of about 400 ° C to 650 ° C.

  In this heat treatment, nickel element moves from the region 113 to the regions 111 and 112 as indicated by 114 in FIG. That is, the nickel element existing in 113 is gettered into the regions 111 and 112.

This phenomenon is observed
(1) Phosphorus selectively doped in the regions 111 and 112 is likely to be combined with nickel.
(2) The regions 111 and 112 are damaged during doping, and defects for trapping nickel are formed at a high density. Therefore, the nickel element easily moves to this region.
For reasons such as

Phosphorus and nickel have various bonding states represented by Ni ₃ P, Ni ₅ P ₂ , Ni ₂ P, Ni ₃ P ₂ , Ni ₂ P ₃ , NiP ₂ , and NiP ₃ , and these The bonding state is very stable (stable in a temperature atmosphere of at least about 700 ° C. or less). Therefore, the movement of nickel from the region 113 to the regions 111 and 112 is unilateral.

  By passing through the process shown in FIG. 2E, the concentration of nickel element in the region 113 and the regions 111 and 112 differ by several times.

  FIG. 3 shows a sample treated under the same conditions as in this example, a region doped with phosphorus (corresponding to region 111 in FIG. 2E) and a region not so (FIG. 2E ) (Corresponding to the region 113)) and the result of measuring the residual concentration of nickel element by SIMS (secondary ion analysis method).

  The measurement curve shown in FIG. 3A shows the concentration of nickel element in a region where phosphorus ions are accelerated and implanted. The measurement curve shown in FIG. 3B shows the concentration of nickel element in a region where phosphorus ions are not acceleratedly implanted.

  Note that it is confirmed that no difference in concentration is particularly observed in the two regions when phosphorus ion implantation and subsequent heat treatment are not performed.

  When the process shown in FIG. 2E is completed, isotropic etching is performed on the silicon oxide film pattern 109 using the silicon nitride film pattern 110 as a mask, as shown in FIG. 2F. That is, the silicon oxide film 109 is side-etched.

  In this way, a silicon oxide film pattern 115 whose side is side-etched is obtained. (Fig. 2 (F))

  Next, the silicon nitride film pattern 110 is removed. (Fig. 2 (G))

  Next, as shown in FIG. 2H, the exposed silicon film is removed using the silicon oxide film pattern 115 as a mask. Thus, a crystalline silicon film pattern 116 constituted by the region where the crystal growth as shown by 106 in FIG. 1B is performed is obtained.

  The silicon film pattern 116 is formed using the region 113 where nickel gettering has been performed. This silicon film pattern 116 will later become the active layer of the TFT.

  In the formation of this pattern 116, by adopting the steps shown in FIGS. 2F to 2G, the nickel element present at a high concentration in the regions 111 and 112 finally wraps around the 116 pattern. That is restrained.

  That is, the etching region of the silicon oxide film 115 side-etched in the process shown in FIG. 2F serves as a margin, and nickel elements existing in the regions 111 and 112 are prevented from entering the 116 pattern.

  When the process shown in FIG. 2H is completed, the silicon oxide film pattern 115 is then removed. Then, a silicon oxide film 117 is formed to a thickness of 100 nm by plasma CVD so as to cover the silicon film pattern 116. (Fig. 2 (I))

  Next, an aluminum film (not shown) is formed, and a pattern 118 made of an aluminum film is formed using a resist mask 119. (Fig. 2 (I))

  Next, a porous anodic oxide film 120 (aluminum oxide film) is formed to a thickness of 500 nm by anodic oxidation. At this time, the porous anodic oxide film 120 is formed on the side surface of the pattern due to the presence of the resist mask 119. (Fig. 3 (J))

  In order to form a porous anodic oxide film, an aqueous solution containing 3% oxalic acid is used as the electrolytic solution.

  Next, the resist mask 119 is removed, and anodic oxidation is performed again. In this step, an electrolytic solution obtained by neutralizing an ethylene glycol solution containing 3% tartaric acid with aqueous ammonia is used.

  In this step, an anodized film having a dense film quality indicated by 121 is formed. The film thickness of this anodic oxide film having a dense film quality is 80 nm.

  In this step, the anodic oxide film 121 is formed on the peripheral surface of the aluminum pattern 122 because the electrolytic solution penetrates into the porous anodic oxide film 120. (Fig. 3 (J))

  Further, the remaining aluminum pattern 122 becomes a gate electrode.

  In this way, the state shown in FIG. Next, the exposed silicon oxide film 117 is removed by a dry etching method.

  Through this process, the remaining silicon oxide film 123 is obtained. In this way, the state shown in FIG.

  Next, the porous anodic oxide film 120 is removed.

  Then, phosphorus doping is performed. Here, phosphorus is doped in order to manufacture an NTFT (N-channel TFT). (Fig. 3 (L))

  Here, plasma doping is used as a phosphorus doping method.

  Note that if a PTFT (P-channel TFT) is manufactured, boron may be doped.

  By performing phosphorous doping, phosphorous doping is selectively performed on the pattern 116 of the active layer.

  In this step, the source region 11, the low concentration impurity region 12, the channel region 13, the low concentration impurity region 14, and the drain region 15 are formed in a self-aligned manner. (Fig. 3 (L))

  Here, the reason why the regions 12 and 14 are low-concentration impurity regions is as follows. (Low concentration means that the concentration of impurities that determine the channel type is lower than that of the source and drain regions)

  On the regions 12 and 14, the silicon oxide film 123 remains. Accordingly, some of the phosphorus ions acceleratedly implanted in the regions 12 and 14 are shielded by the silicon oxide film 123. As a result, the regions 12 and 14 are doped with phosphorus at a lower concentration than the regions 11 and 15.

  Further, the 13 region becomes a channel region. This is because the gate electrode 122 and the surrounding anodic oxide film 121 serve as a mask, so that phosphorus is not doped.

  If the wraparound of ions and the diffusion of electric field are ignored, the offset gate region (functions as a high resistance region in the same manner as the low concentration impurity region) adjacent to the channel region by the thickness of the anodic oxide film 121. Will be formed.

  However, in this embodiment, the thickness of the anodic oxide film 121 is as thin as 80 nm, and its presence can be ignored when considering the wraparound of phosphorus ions during doping.

  Next, a silicon oxide film 16 is formed as an interlayer insulating film by a plasma CVD method, and a silicon nitride film 17 is further formed by a plasma CVD method. (Figure 3 (M))

  Next, a polyimide resin film 124 is formed. When a resin film is used, the surface can be flattened. Other than polyimide, polyamide, polyimide amide, polyamide, acrylic, epoxy, or the like can be used.

  Next, an opening for contact is formed, and a source electrode 125 and a drain electrode 126 are formed.

  Thus, the thin film transistor shown in FIG.

  This embodiment relates to an improvement of the manufacturing process shown in FIGS.

  FIG. 5 shows part of the manufacturing process of this example.

  First, a crystalline silicon film 503 that is at least partially crystallized is obtained over a glass substrate 501 in accordance with the manufacturing steps shown in FIGS. Here, reference numeral 502 denotes an underlying silicon oxide film. (Fig. 5 (A))

  Next, a silicon oxide film (not shown) is formed. Then, as shown in FIG. 5B, this silicon oxide film is patterned using a resist mask 504 to obtain a pattern indicated by 505. (Fig. 5 (A))

  Further, phosphorus ions are accelerated and implanted by plasma doping. In this manner, phosphorus ions are accelerated and implanted into the regions indicated by 506 and 507 in FIG. Further, phosphorus ions are not acceleratedly implanted into the region 500.

  Next, using the resist mask 504 as shown in FIG. 5C, the side surface of the silicon oxide film pattern 505 is etched (side-etched) as indicated by 508.

  Thereafter, the resist mask 504 is removed.

  Then, heat treatment is performed as shown in FIG. This heat treatment is performed in a nitrogen atmosphere at 600 ° C. for 2 hours.

  In this step, nickel element moves from the region 500 to the regions 506 and 507. That is, the nickel element contained in the 500 region is gettered into the 506 and 507 regions.

    When the heat treatment step shown in FIG. 5D is completed, the silicon film is patterned using the silicon oxide film pattern 509 as a mask as shown in FIG.

  In this step, the regions 506 and 507 are completely removed, and the region adjacent to the regions 506 and 507 in the 500 region (corresponding to the region that was previously side-etched in step (C)) is also removed. Is done.

  The reason for this is to prevent the nickel element from entering the region finally used as the active layer of the element.

  When the state shown in FIG. 5E is obtained, the silicon oxide film pattern 509 is removed, and a silicon film pattern 510 is obtained. Then, a TFT is produced using the silicon film pattern 510 as an active layer.

  This example shows an example in which crystallization is performed by a method different from crystal growth in a direction parallel to the substrate as shown in Example 1. In this embodiment, a method for obtaining a crystalline silicon film using nickel will also be described.

  This embodiment shows not a method of selectively introducing nickel element as shown in Embodiment 1 to cause crystal growth in a direction parallel to the substrate, but nickel over the entire surface of amorphous silicon. The present invention relates to a method for uniformly crystallizing the entire surface by introducing an element.

  FIG. 6 shows a manufacturing process of this example. First, a silicon oxide film 602 is formed over the glass substrate 601 as a base film. Next, an amorphous silicon film 603 is formed by a low pressure thermal CVD method or a plasma CVD method. In this way, the state shown in FIG.

  Next, a nickel acetate solution is applied to the entire surface of the amorphous silicon film. At this time, the excess solution is blown off using a spinner.

  It is desirable to form an extremely thin oxide film on the surface of the amorphous silicon film before applying the solution. By doing so, the wettability (hydrophilicity) of the surface of the silicon film can be improved and the solution can be prevented from being repelled. The oxide film can be formed by irradiation with UV light in an oxygen atmosphere, treatment with ozone water, or the like.

  Thus, as shown at 604 in FIG. 6B, a state is obtained in which the nickel element is held in contact with the surface of the amorphous silicon film 603.

  Next, a crystalline silicon film 604 is obtained by performing heat treatment. (Fig. 6 (C))

  This heat treatment may be performed in a nitrogen atmosphere at 600 ° C. for 4 hours.

  In this heat treatment step, not the crystal growth in a specific direction as shown in FIG. 1, but a state where the entire film is uniformly grown is obtained.

  This manufacturing process has a feature that it is simpler than the manufacturing process shown in FIG. However, when a TFT is fabricated, higher performance can be obtained by using the lateral growth method shown in FIG.

  In this embodiment, a process of manufacturing PTFT and NTFT at the same time is shown. In addition to the gettering of nickel element from the active layer, the structure in which gettering of nickel element from the channel and the low-concentration impurity region to the source and drain regions is further performed is shown.

  7 to 9 show a manufacturing process of this example.

  First, as shown in FIG. 7A, a base film 702 is formed on a glass substrate 701, and further a crystalline silicon film (or partially crystallized silicon) is formed by the method shown in FIGS. Membrane) 703 is obtained.

  Next, a silicon oxide film and a silicon nitride film (not shown) are stacked and patterned by resist masks 707 and 709.

  Thus, a laminated film pattern composed of the silicon oxide film pattern 704 and the silicon nitride film pattern 706 is obtained. Similarly, a laminated film pattern including a silicon oxide film pattern 705 and a silicon nitride film pattern 708 is obtained.

  In this way, the state shown in FIG.

  Next, the resist masks 707 and 708 are removed, and phosphorus ions are doped by plasma doping as shown in FIG.

  In this step, phosphorus is doped in the regions 710, 711, and 712.

  Thereafter, by performing heat treatment, nickel elements are gettered in the regions 710, 711, and 712.

  Next, as shown in FIG. 7C, the side surface of the silicon oxide film pattern 704 is side-etched using the silicon nitride film pattern 706. In this way, a silicon oxide film pattern 713 having side etching as indicated by 715 is obtained.

  Similarly, a silicon oxide film pattern 714 that has been side-etched is obtained.

  Next, the silicon film in the exposed region is removed using the silicon oxide film patterns 713 and 714. (Fig. 7 (D))

  The silicon film patterns 716 and 717 obtained here are formed by regions where nickel elements are gettered in the regions 710, 711, and 712 and the concentration of nickel elements is reduced.

  Next, a silicon oxide film 718 functioning as a gate insulating film is formed by a plasma CVD method. Further, an aluminum film is formed and patterned using the resist masks 71 and 72 to obtain aluminum patterns 719 and 720.

  In this way, the state shown in FIG.

  Next, as shown in FIG. 8F, porous anodic oxide films 721 and 724 are formed by anodic oxidation.

  Next, the resist masks 71 and 72 are removed, and anodic oxide films 723 and 726 having a dense film quality are formed. In this state, gate electrodes 722 and 725 are defined.

  After obtaining the state shown in FIG. 8 (F), phosphorus is doped as shown in FIG. 8 (G). This doping is performed in order to cause gettering in the doped region again.

  Thereafter, heat treatment is performed at 400 ° C. for 1 hour. In this step, the nickel element remaining in the region 731 is gettered to the regions 727 and 728. The nickel element remaining in the region 732 is gettered in the regions 729 and 730.

  Thus, the regions 731 and 732 are thoroughly gettered again. That is, the nickel element is thoroughly removed from the regions 731 and 732. (Fig. 8 (H))

  Note that it is important that this heat treatment step be performed under conditions that the gate electrode can withstand (mainly the upper limit of temperature).

  When silicon or silicide is used as the gate electrode, this treatment may be performed at a temperature that the glass substrate can withstand. In this case, a higher gettering effect can be obtained.

  Regions 727, 728, 729, and 730 are regions that finally become a source and a drain, and even if the concentration of nickel element is somewhat high, the operation of the TFT is not significantly affected.

  On the other hand, the regions 731 and 732 are sensitive to the presence of nickel elements in the regions where channels and low-concentration impurity regions are formed.

  That is, the channel region is a region where the carrier density is changed by an electric field applied from the gate electrode, and the presence of a metal element that becomes a trap adversely affects its operation.

  The low-concentration impurity region, particularly the low-concentration impurity region on the drain side, has a function of relaxing a high electric field applied between the channel region and the drain region, and a relatively strong electric field is applied.

  The nickel element in the semiconductor functions as a carrier trap level.

In addition, if a trap level exists in a region where a relatively high electric field is applied, the carrier moves through the level and changes in semiconductor characteristics occur.
Therefore, the nickel element remaining in the low-concentration impurity region causes a problem such as generation of a leakage current and a decrease in breakdown voltage.

  When the step of gettering by heating shown in FIG. 8H is completed, the exposed silicon oxide film 718 is etched. (Fig. 8 (I))

  In this state, remaining silicon oxide films indicated by 733 and 734 are obtained.

  Further, the porous anodic oxide films 721 and 724 are removed. (Fig. 8 (I))

  In the state shown in FIG. 8I, phosphorus doping is performed again.

  In this step, the region 735 is doped at a high concentration, the region 736 is doped at a low concentration, the region 737 is not doped, and the region 738 is doped at a low concentration. , 739 is doped at a high concentration.

  At the same time, a drain region 740, a low concentration impurity region 741, a channel region 742, a low concentration impurity region 743, and a source region 744 of the NTFT are formed in a self-aligned manner.

  Next, a resist mask 745 is formed on the NTFT and this time boron is doped by a plasma doping method.

  By performing this doping, the conductivity type of the region previously doped with phosphorus is inverted and becomes P-type.

  Thus, as shown in FIG. 8J, the PTFT source region 745, low-concentration impurity region 746, channel region 747, low-concentration impurity region 748, and drain region 749 are formed in a self-aligned manner.

  Next, as shown in FIG. 9K, a silicon oxide film 750, a silicon nitride film 751, and a resin film 752 are formed as interlayer insulating films.

  Next, contact holes are formed, and a source electrode 753 and a drain electrode 754 of the PTFT are formed. Further, a source electrode 756 and a drain electrode 755 of the NTFT are formed.

  Thus, as shown in FIG. 9M, NTFT and PTFT can be manufactured on the same substrate in the same process.

  In this embodiment, nickel gettering from the active layer constituting the TFT (step in FIG. 7C) and nickel gettering from the channel region and the low-concentration impurity region (in FIG. 8H). Step), the fact that the nickel element affects the characteristics of the TFT element is thoroughly eliminated.

  By doing so, an element having high characteristics and high reliability can be obtained. This is important in configuring an integrated circuit.

  This embodiment relates to a structure for obtaining a crystalline silicon film by a method different from the manufacturing process as shown in FIG.

  The configuration shown in the present embodiment uses the technique described in Japanese Patent Application No. 8-335152 already filed by the present applicant.

  An outline of the manufacturing process will be described with reference to FIG. Here, a quartz substrate is used as the substrate 101 instead of a glass substrate. This is because a heat treatment at a high temperature that cannot be tolerated later by a glass substrate such as 900 ° C. or higher is required.

  First, a silicon oxide film 102 is formed on a quartz substrate 101 as a base film. In addition, since a quartz substrate with good flatness can be obtained, in this case, the base film may not be formed.

  Next, an amorphous silicon film is formed to a thickness of 50 nm by low pressure thermal CVD. Further, a mask 104 made of a silicon oxide film is formed. (Fig. 1 (A))

  Then, a nickel acetate solution is applied to obtain a state in which nickel element is held in contact with the surface. (Fig. 1 (A))

  Then, heat treatment is performed at 600 ° C. for 4 hours in a nitrogen atmosphere to perform crystallization as shown in FIG.

  Next, the mask 104 is removed, and heat treatment is performed again. This heat treatment is performed for 30 minutes at a temperature of 950 ° C. in an oxygen atmosphere containing 3% by volume of HCl. As a result of this step, a thermal oxide film is formed to a thickness of 30 nm, and the thickness of the silicon film is reduced from 50 nm to 35 nm.

  This process is a feature of this embodiment. In this step, nickel element is removed from the entire film in the form of nickel chloride in the atmosphere.

  In addition, the crystallinity of the film is drastically improved as interstitial silicon atoms or unstablely bonded silicon atoms in the film are consumed to form the thermal oxide film. That is, the defect density in the film is dramatically reduced.

  After the heat treatment is completed, the formed thermal oxide film is removed. After that, a TFT may be manufactured according to the steps shown in FIG.

  In this embodiment, since the effect cannot be obtained unless the effect of the thermal oxide film forming step is at least 900 ° C. or higher, it is necessary to use a quartz substrate as the substrate. However, an element with very high characteristics can be obtained.

  In this embodiment, a device having more stable element characteristics can be obtained by a synergistic effect of the effect of applying the thermal oxide film forming step and the nickel gettering effect as shown in the first embodiment. .

  The manufacturing process shown in this embodiment can also be used for the manufacturing process shown in FIG.

  In this example, a bottom gate type (in this case, an inverted stagger type) TFT is manufactured.

  First, as shown in FIG. 10A, a silicon oxide film 1002 is formed over a glass substrate 1001 as a base film. Then, a gate electrode 1003 is formed using a silicide material.

  Further, a silicon oxide film 1000 functioning as a gate insulating film is formed so as to cover the gate electrode.

  Next, a crystalline silicon film 1004 is obtained by a method as shown in FIGS. In this way, the state shown in FIG.

  Next, a resist mask 1007 is used to obtain a silicon oxide film pattern 1005 and a silicon nitride film pattern 1006. (Fig. 10 (B))

  Then, phosphorus doping is performed. As a result, phosphorus ions are accelerated and implanted into the regions 1008 and 1009. Also, phosphorus ions are not implanted into the region 1010.

  Next, heat treatment is performed as shown in FIG. In this step, nickel element existing in the region 1010 is gettered to the regions 1008 and 1009.

  Next, the silicon oxide film pattern 1005 is side-etched using the silicon nitride film pattern 1006 to form a pattern 1011. (Figure 10 (D))

  Next, the silicon nitride film 1006 is removed, and the region 1010 of the silicon film is patterned using the silicon oxide film pattern 1011. Thus, a pattern 1012 made of a crystalline silicon film is obtained as shown in FIG.

  Next, as shown in FIG. 11F, a mask 1013 made of a silicon nitride film is provided, and phosphorus is doped by a plasma doping method.

  After the doping is completed, laser beam irradiation is performed to activate the dopant and anneal the doped region.

  In this step, a source region 1014, a channel region 1015, and a drain region 1016 are formed.

  Next, as shown in FIG. 11G, a silicon oxide film 1017 and a resin film 1018 are formed.

  Then, contact holes are formed, and a source electrode 1019 and a drain electrode 1020 are formed. Thus, a bottom gate type TFT is obtained.

  This embodiment is an example in which doped silicon or silicide is used as the gate electrode in the TFT manufacturing process shown in FIGS.

  In this case, since a temperature such as 600 ° C. can be applied in the step shown in FIG. 8C, the gettering effect can be further enhanced.

  In this embodiment, an outline of an apparatus using the invention disclosed in this specification is shown. FIG. 12 shows an outline of each device.

  FIG. 12A shows a portable information processing terminal, which has a communication function using a telephone line.

  This electronic device includes an integrated circuit 2006 using a thin film transistor inside a main body 2001. An active matrix liquid crystal display 2005, a camera unit 2002 for capturing an image, and an operation switch 2004 are provided.

  FIG. 12B illustrates an electronic device called a head mounted display. This apparatus has a function of displaying an image in front of the eyes by wearing a main body 21201 on the head with a band 2103. The image is created by the liquid crystal display device 2102 corresponding to the left and right eyes.

  Such an electronic device uses a circuit using a thin film transistor in order to be small and light.

  FIG. 12C has a function of displaying map information and various information based on a signal from an artificial satellite. Information from the satellite captured by the antenna 2204 is processed by an electronic circuit provided inside the main body 2201, and necessary information is displayed on the liquid crystal display device 2202.

  The operation of the apparatus is performed by an operation switch 2203. Even in such an apparatus, a circuit using a thin film transistor is used in order to reduce the overall configuration.

  FIG. 12D illustrates a mobile phone. This electronic device includes a main body 2301 that includes an antenna 2306, an audio output unit 2302, a liquid crystal display device 2304, operation switches 2305, and an audio input unit 2303.

  An electronic device illustrated in FIG. 12E is a portable imaging device called a video camera. The electronic apparatus includes a liquid crystal display 2402 attached to an opening / closing member and an operation switch 2404 attached to the opening / closing member.

  Further, the main body 2401 includes an image receiving unit 2406, an integrated circuit 2407, an audio input unit 2403, operation switches 2404, and a battery 2405.

  An electronic device illustrated in FIG. 12F is a projection liquid crystal display device. This device includes a light source 2502, a liquid crystal display device 2503, and an optical system 2504 in a main body 2501, and has a function of projecting an image onto a screen 2505.

  Further, as the liquid crystal display device in the electronic device described above, either a transmission type or a reflection type can be used. The transmissive type is advantageous in terms of display characteristics, and the reflective type is advantageous when pursuing low power consumption and reduction in size and weight.

  As a display device, a flat panel display such as an active matrix EL display or a plasma display can be used.

  This embodiment shows another process for obtaining a pattern in which a metal element is gettered (removed) using a crystalline silicon film obtained using the metal element.

  FIG. 13 shows a manufacturing process of this example. First, as shown in FIG. 13A, a base film 1302 is formed over a glass substrate 1301, and a crystalline silicon film 1303 is formed using nickel.

  Next, a mask made of the silicon oxide film 1302 is formed. Then, phosphorus doping is performed. In this step, phosphorus is doped in regions 1303 and 1305. Further, the region 1304 is not doped. (Fig. 13B)

  Heat treatment is performed in the state shown in FIG. 13B, and the nickel element existing in the region 1304 is gettered to the regions 1303 and 1305.

  Next, regions 1303 and 1305 are removed using a mask 1302 made of a silicon oxide film. (Fig. 13 (C))

  Next, the region 1306 is side-etched using a mask 1302 made of a silicon oxide film. In this way, a pattern 1307 made of a crystalline silicon film is obtained. (Fig. 13D)

  Next, the mask 1302 made of a silicon oxide film is removed to obtain the state shown in FIG. Thereafter, a TFT is manufactured using a pattern 1307 made of a crystalline silicon film.

  In this embodiment, in the step shown in FIG. 2, before performing the side etching of the pattern 109 of the silicon oxide film, the regions 111 and 112 are removed using the pattern, and then the side etching of the pattern 109 is performed. Further, the peripheral portion of the exposed region 113 is etched.

  In this case, although the process becomes complicated, it is possible to thoroughly prevent the nickel scattered when the regions 111 and 112 are etched from entering the region 116 that finally remains.

FIG. 6 shows a manufacturing process of a TFT. FIG. 6 shows a manufacturing process of a TFT. FIG. 6 shows a manufacturing process of a TFT. The figure which shows the density | concentration of the nickel element in the area | region where phosphorus was doped, and the area | region which is not so. 10A and 10B show a manufacturing process of a TFT. The figure which shows the process of obtaining a crystalline silicon film. The figure which shows the process of producing PTFT and NTFT on the same board | substrate. The figure which shows the process of producing PTFT and NTFT on the same board | substrate. The figure which shows the process of producing PTFT and NTFT on the same board | substrate. 10A and 10B illustrate a manufacturing process of a bottom gate type TFT. 10A and 10B illustrate a manufacturing process of a bottom gate type TFT. 1 shows a schematic configuration of an apparatus using the invention. 10A and 10B show part of a manufacturing process of a TFT.

Explanation of symbols

101 Glass substrate (or quartz substrate)
102 Base film (silicon oxide film)
103 Amorphous silicon film 104 Mask made of silicon oxide film 105 Slit-like opening 106 Nickel element 107 held in contact 107 Crystalline silicon film 108 Resist mask 109 Pattern of silicon oxide film 110 Pattern of silicon nitride film 111, 112 Phosphorus Doped region 113 Nickel gettering region 114 Nickel moving direction 115 Silicon oxide film pattern after side etching 116 Patterned silicon film 117 Gate insulating film (silicon oxide film)
118 Aluminum pattern 119 Resist mask 120 Porous anodic oxide film 121 Anodic oxide film having dense film quality 122 Gate electrode 123 Remaining gate electrode (silicon oxide film)
11 Source electrode 12 Low concentration impurity region 13 Channel region 14 Low concentration impurity region 15 Drain region 16 Silicon oxide film 17 Silicon nitride film 124 Polyimide resin film 125 Source electrode 126 Drain electrode

Claims (17)

A crystalline semiconductor film is formed using a metal element that promotes crystallization of the semiconductor film,
Forming a mask on the crystalline semiconductor film;
Selectively doping the crystalline semiconductor film with an element selected from nitrogen, phosphorus, arsenic, antimony, and bismuth using the mask;
Applying a first heat treatment, gettering the metal element into the doped region,
The doped region is removed using the mask to form an island-shaped semiconductor film,
Side etching the island-shaped semiconductor film using the mask,
Forming a gate insulating film on the island-shaped semiconductor film;
Forming a gate electrode on the island-shaped semiconductor film through the gate insulating film;
After doping the island-shaped semiconductor film with an element selected from nitrogen, phosphorus, arsenic, antimony, and bismuth through the gate insulating film using the gate electrode, a second heat treatment is performed, and the metal A method for manufacturing a semiconductor device, characterized in that an element is gettered into the doped region. A crystalline semiconductor film is formed using a metal element that promotes crystallization of the semiconductor film,
Forming a mask on the crystalline semiconductor film;
Selectively doping the crystalline semiconductor film with an element selected from nitrogen, phosphorus, arsenic, antimony, and bismuth using the mask;
Applying a first heat treatment, gettering the metal element into the doped region,
Removing the doped region using the mask to form an island-shaped semiconductor film;
Side etching the island-shaped semiconductor film using the mask,
Forming a gate insulating film on the island-shaped semiconductor film;
Forming a gate electrode on the island-shaped semiconductor film through the gate insulating film;
After doping the island-shaped semiconductor film with an element selected from nitrogen, phosphorus, arsenic, antimony, and bismuth through the gate insulating film using the gate electrode, a second heat treatment is performed, and the metal Gettering elements into the doped region;
By removing the gate insulating film, the doped region of the island-shaped semiconductor film is exposed,
A method of manufacturing a semiconductor device, wherein a source region and a drain region are formed in the island-shaped semiconductor film by doping impurities into the exposed island-shaped semiconductor film using the gate electrode. A crystalline semiconductor film is formed using a metal element that promotes crystallization of the semiconductor film,
Forming a mask on the crystalline semiconductor film;
Selectively doping the crystalline semiconductor film with an element selected from nitrogen, phosphorus, arsenic, antimony, and bismuth using the mask;
Applying a first heat treatment, gettering the metal element into the doped region,
Removing the doped region using the mask to form a first island-shaped semiconductor film and a second island-shaped semiconductor film;
Side etching the first island-shaped semiconductor film and the second island-shaped semiconductor film using the mask,
Forming a gate insulating film on the first island-shaped semiconductor film and the second island-shaped semiconductor film;
Forming a gate electrode on the first island-shaped semiconductor film and the second island-shaped semiconductor film via the gate insulating film;
Doping the first island-shaped semiconductor film and the second island-shaped semiconductor film with an element selected from nitrogen, phosphorus, arsenic, antimony, and bismuth through the gate insulating film using the gate electrode Then, a second heat treatment is performed, the metal element is gettered to the doped region,
By removing the gate insulating film, the doped regions of the first island-shaped semiconductor film and the second island-shaped semiconductor film are exposed,
A source region and a drain region are formed in the first island-shaped semiconductor film by doping the first island-shaped semiconductor film and the second island-shaped semiconductor film using the gate electrode. ,
Forming a mask on the first island-shaped semiconductor film, and doping the second island-shaped semiconductor film with boron to form a source region and a drain region in the second island-shaped semiconductor film; A method for manufacturing a semiconductor device. In any one of Claims 1 thru | or 3,
By performing the first heat treatment and the second heat treatment, the metal element is gettered to the doped region to form a region where the concentration of the metal element is reduced. A method for manufacturing a semiconductor device. In any one of Claims 1 thru | or 4,
A method for manufacturing a semiconductor device, comprising: forming an active layer of an element in a region of the crystalline semiconductor film that has not been removed using the mask. In any one of Claims 1 thru | or 5,
As the metal element for promoting the crystallization of the semiconductor film, one or more kinds selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au are used. A method for manufacturing a semiconductor device. In any one of Claims 1 thru | or 5,
A method for manufacturing a semiconductor device, wherein Ni is used as a metal element that promotes crystallization of the semiconductor film. In any one of Claims 1 thru | or 7,
A method for manufacturing a semiconductor device, wherein the semiconductor film is a silicon film. In any one of Claims 1 thru | or 7,
The method for manufacturing a semiconductor device, wherein the semiconductor film is a compound film represented by Si _X Ge _1-X (0 <X <1). In any one of Claims 1 thru | or 9,
A method for manufacturing a semiconductor device, wherein phosphorus is selected as the element to be doped. In claim 10,
A method for manufacturing a semiconductor device, wherein a phosphorus-containing film is formed and laser irradiation or third heat treatment is performed to perform doping of the phosphorus. In claim 10,
A method for manufacturing a semiconductor device, wherein a phosphorus-containing solution is applied to form a PSG film, and laser irradiation or third heat treatment is performed to perform doping of the phosphorus. In claim 10,
A method for manufacturing a semiconductor device, wherein the phosphorous doping is performed by laser irradiation in an atmosphere containing phosphorus. In any one of Claims 1 thru / or Claim 13,
The method for manufacturing a semiconductor device, wherein the gate insulating film is a silicon oxide film. In any one of Claims 1 thru | or 14,
A method for manufacturing a semiconductor device, wherein the crystalline semiconductor film is irradiated with infrared light. In any one of Claims 1 to 15,
A method for manufacturing a semiconductor device, wherein the crystalline semiconductor film is irradiated with a laser. In any one of Claims 1 thru | or 16,
The method for manufacturing a semiconductor device is characterized in that the first heat treatment is performed at 400 ° C. to 650 ° C. in a nitrogen atmosphere.

Images