JP3998899B2 - THIN FILM TRANSISTOR AND SEMICONDUCTOR DEVICE USING THIN FILM TRANSISTOR - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The invention disclosed in this specification relates to a structure of a thin film transistor (hereinafter referred to as a TFT in this specification). Further, the present invention relates to a manufacturing method thereof.
[0002]
[Prior art]
A TFT manufactured using a silicon thin film formed on a glass substrate or a quartz substrate is known.
[0003]
Most TFTs currently in practical use use an amorphous silicon film (amorphous silicon film) as an active layer.
[0004]
The amorphous silicon film can be formed relatively easily using a plasma CVD method.
[0005]
Future technology trends for active matrix liquid crystal display devices include an active matrix circuit, a circuit that drives the circuit, and various circuits that handle image information and various information on a single glass or quartz substrate. The system-on-panel configuration is considered to be pursued.
[0006]
In order to realize such a configuration, the characteristics of a TFT using an amorphous silicon film are too low.
[0007]
A TFT using an amorphous silicon film has low characteristics and can only be used in an active matrix circuit of an active matrix liquid crystal display device.
[0008]
Specifically, a TFT using an amorphous silicon film has a mobility of 1 cm. ² / Vs or less. Moreover, only the N channel type can be put into practical use, and the P channel type has a problem that its characteristics are too low to be put into practical use.
[0009]
The mobility of a MOS transistor using a single crystal silicon wafer is 1000 cm. ² Usually, it is at least / Vs.
[0010]
In order to solve this problem, TFTs using a crystalline silicon film are partly put into practical use.
[0011]
As a method for obtaining a crystalline silicon film, a method of crystallizing an amorphous silicon film by heating is common.
[0012]
For example, an amorphous silicon film is formed by a plasma CVD method or a low pressure thermal CVD method, and the film is heated at a temperature of about 800 ° C. to 1000 ° C. for several hours to obtain a crystalline silicon film having a polycrystalline state. Can be obtained.
[0013]
This method is referred to as a high temperature process because the high temperatures required for normal IC fabrication are utilized.
[0014]
A TFT using a crystalline silicon film obtained by this method is an N-channel type and has a mobility of 100 cm. ² / Vs, P channel type with mobility of 60cm ² / Vs is obtained.
[0015]
With such a characteristic, a CMOS circuit required for constituting an integrated circuit can be produced. In addition, a circuit that is configured with an IC using a conventional single crystal silicon wafer can be configured with TFTs, although it does not reach the characteristics.
[0016]
However, in order to manufacture a TFT using a crystalline silicon film, it is necessary to use a substrate having heat resistance (currently limited to quartz), which increases costs. (Quartz substrates are expensive)
[0017]
Therefore, what is considered is a method of devising a crystallization method using an inexpensive glass substrate as the substrate.
[0018]
This method is referred to as a low-temperature process because it is produced by a process at a temperature that the glass substrate can withstand.
[0019]
A first example of this method is a technique for crystallizing an amorphous silicon film by setting the heating temperature to a level that a glass substrate can withstand.
[0020]
For example, a crystalline silicon film can be obtained by forming an amorphous silicon film on a glass substrate and heating it at 600 ° C. for about 48 hours.
[0021]
However, a TFT using a crystalline silicon film obtained by this method does not exhibit satisfactory characteristics.
[0022]
In addition, since the heating time becomes long, there is a problem that the manufacturing cost is not so low.
[0023]
As another method of the low temperature process, there is a technique of transforming an amorphous silicon film into a crystalline silicon film by irradiating laser light.
[0024]
This method has an advantage that the glass substrate is hardly heated.
[0025]
A TFT obtained by this method (referred to as a laser process) can obtain characteristics comparable to those obtained by a high temperature process.
[0026]
[Problems to be solved by the invention]
In order to realize the system-on-panel as described above, it has been found that the TFT obtained by the above-described low-temperature process still has low characteristics.
[0027]
The technology required here includes
(1) A low temperature process.
(2) A characteristic higher than that obtained by a laser process can be obtained.
Is required.
[0028]
As a technique that satisfies this requirement, the present applicants have developed a technique for crystallizing by introducing a trace amount of a metal element of an amorphous silicon film and then performing a heat treatment. This technique is described in JP-A-7-321337.
[0029]
A TFT using a crystalline silicon film obtained by the method has extremely high performance. However, in the crystalline silicon film obtained by this method, the metal element used for crystallization remains without being exhausted, and there is a concern that the influence may affect the characteristics of the TFT.
[0030]
In fact, it has been confirmed that items such as reliability and uniformity of characteristics for each element are inferior to conventional TFTs having low characteristics.
[0031]
According to the studies by the present inventors, it has been found that the low reliability and uniformity of the device characteristics are due to the influence of metal elements remaining in the crystalline silicon film.
[0032]
In the invention disclosed in this specification, in a TFT manufactured using a crystalline silicon film crystallized using the above-described certain metal element, the influence of the metal element adversely affects the device characteristics of the TFT. It is an object of the present invention to provide a technique for suppressing the problem.
[0033]
[Means for Solving the Problems]
One of the inventions disclosed in this specification is:
A high resistance region disposed adjacent to the channel region;
A source or drain region disposed adjacent to the high resistance region;
Have
The source or drain region contains a high concentration of a metal element that promotes crystallization of silicon,
The high resistance region includes the metal element at a low concentration.
[0034]
Other aspects of the invention are:
A high resistance region disposed adjacent to the channel region;
A source or drain region disposed adjacent to the high resistance region;
Have
The source or drain region contains 1 × 10 5 of a metal element that promotes crystallization of silicon. ¹⁹ Atom / cm ^Three It is contained in the above concentration,
The metal element is 1 × 10 5 in the channel region and the high resistance region. ¹⁷ Atom / cm ^Three It is contained in the following concentrations.
[0035]
In the source or drain region, the metal element is 1 × 10 ¹⁹ Atom / cm ^Three Even if it is contained in the above concentration, there is no particular problem. However, in a high resistance region (an offset region or a low concentration impurity region in this specification), the concentration of the metal element is 1 × 10 6. ¹⁷ Atom / cm ^Three It is important that: This is because the presence of the metal element in the high resistance region greatly contributes to the formation of unnecessary levels. Further, the concentration of the metal element in the source and drain regions may be larger than the defect density in the region. However, in the high resistance region, the concentration of the metal element needs to be smaller than the defect density in the region.
[0036]
In another aspect of the invention, the source or drain region is doped with phosphorus, and the concentration of phosphorus is higher than the concentration of the metal element. By doing so, it is possible to obtain a higher effect of gettering the nickel element in the source or drain region.
[0037]
In another aspect of the invention, the source or drain region is P-type and the source and drain regions are doped with phosphorus.
[0038]
As a metal element that promotes crystallization of silicon, nickel (Ni) is most preferably used in terms of reproducibility and effects.
[0039]
As the metal element, one or more kinds selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au can be used.
[0040]
DETAILED DESCRIPTION OF THE INVENTION
In a structure in which a high-resistance region such as a low-concentration impurity region or an offset region is arranged adjacent to the channel region, the nickel concentration in the high-resistance region is obtained by using the source and drain regions (at least one region) as gettering sites. Reduce.
[0041]
In order to use the source / drain regions as gettering sites, phosphorus is doped in these regions, and the metal element is gettered into phosphorus. This gettering effect is particularly remarkable when nickel is selected as the metal element.
[0042]
The presence of a metal element that promotes crystallization of silicon typified by nickel poses a problem in the following regions.
(1) Channel region
(2) Interface between channel region and adjacent region and its vicinity
When the metal element is present in the channel region, the electric field applied from the gate electrode, which is the original function of the channel, changes the conductivity type of the surface on the gate insulating film side, thereby inhibiting the function of forming a so-called inversion layer. .
[0043]
This is because when the metal element exists, many unnecessary levels are formed in the forbidden body in the channel region.
[0044]
In general, a junction of different conductivity types such as an IN junction and a PN junction is formed at the interface between the channel region and a region adjacent to the channel region.
[0045]
For example, in the most basic TFT structure, the source / drain regions are disposed adjacent to the channel region. In this structure, a PN junction is formed at the interface between the channel region and the source / drain region when the TFT is turned off.
[0046]
Further, in a structure in which a low concentration impurity region typified by an LDD region is disposed adjacent to the channel region, a PN junction is formed at the interface between the channel region and the low concentration impurity region during the OFF operation.
[0047]
In the structure in which the offset region is disposed adjacent to the channel region, a PI or NI junction is formed at the interface between the channel region and the low concentration impurity region during the OFF operation.
[0048]
In general, when the metal element is present in a junction portion of a different conductivity type, the function and function of the original semiconductor junction at the heterojunction portion is impaired. This is because many levels are formed in the forbidden body due to the presence of the metal element.
[0049]
For example, an unnecessary level due to the presence of the metal element is formed in the heterogeneous junction, and the carrier moves through the level.
[0050]
This causes a decrease in breakdown voltage and an increase in leakage current. In addition, since the state does not occur stably, problems such as a decrease in reliability and variations in characteristics among elements occur.
[0051]
When the invention disclosed in this specification is employed, first, the concentration of the metal element in the channel region can be greatly reduced. In addition, the concentration of the metal element in the high resistance region adjacent to the channel region can be greatly reduced. 1 × 10 which cannot be detected by SIMS in the experiment ¹⁶ Atom / cm ^Three It can also be reduced to the level. The metal concentration in the high resistance region is 1 × 10 ¹⁷ Atom / cm ^Three If it can be reduced to a level or less, a predetermined effect can be obtained.
[0052]
FIG. 12 shows the relative distribution of Ni concentration in each part of the active layer of the TFT obtained when the invention is used. (A) shows the schematic configuration of the TFT, and (B) shows the distribution of relative density in each part.
[0053]
The arrow shown in (B) indicates the direction of Ni concentration change (whether the concentration increases or decreases) in the gettering step. The length of the arrow indicates the magnitude relationship of the rate of density change.
[0054]
The HRD means a high resistance region, which is a low concentration impurity region shown in the embodiment.
[0055]
As shown in FIG. 12, by using the invention disclosed in this specification, the concentration of a metal element in a high-resistance region such as a low-concentration impurity region or an offset region is reduced, whereby a heteroconductive junction is formed. The concentration of the metal element in the portion can be greatly reduced.
[0056]
Then, problems such as a decrease in breakdown voltage and an increase factor of leakage current can be solved, and problems such as a decrease in reliability and variation in characteristics of each element can be solved.
[0057]
【Example】
[Example 1]
In this embodiment, an example of manufacturing an N-channel thin film transistor is described. 1 and 2 show a manufacturing process of this embodiment.
[0058]
First, as shown in FIG. 1A, a silicon oxide film 102 is formed to a thickness of 300 nm as a base film over a glass substrate 101. Here, a Corning 1737 glass substrate is used as the glass substrate.
[0059]
Next, an amorphous silicon film 103 is formed to a thickness of 50 nm by low pressure thermal CVD using disilane as a source gas.
[0060]
Next, a mask 104 made of a silicon oxide film is formed. This mask 104 is made of a silicon oxide film having a thickness of 120 nm, and an opening 105 is formed.
[0061]
The opening 105 has a longitudinal shape extending in the depth direction from the front side of the drawing.
[0062]
When the mask 104 is formed, a nickel acetate solution adjusted to a predetermined nickel concentration is applied to obtain a state where the nickel element is held in contact with the surface as indicated by 106.
[0063]
In this state, the nickel element is held in contact with the surface of the amorphous silicon film 103 in the region where the opening 105 is formed. In this way, as shown in FIG. 1A, a state in which the nickel element is selectively held in contact with part of the surface of the amorphous silicon film 103 is obtained.
[0064]
Although an example in which nickel element is introduced using a solution is shown here, an ion implantation method may be used instead. In this case, the amount of the metal element introduced can be precisely controlled.
[0065]
Next, heat treatment is performed on a sample having the state illustrated in FIG. 1A in a nitrogen atmosphere at 570 ° C. for 12 hours.
[0066]
In this step, nickel element diffuses from the region where the opening 105 is formed into the amorphous silicon film, and crystal growth as indicated by 107 proceeds.
[0067]
This crystal growth proceeds in a direction parallel to the film surface. This crystal growth direction coincides with a direction perpendicular to the direction in which the opening 105 extends. In addition, the growth direction is aligned. (The crystal growth direction is radial at the end of the opening 105)
[0068]
The crystal growth as indicated by 107 can be performed over 100 μm or more. This crystal growth is called lateral growth for convenience.
[0069]
When this crystal growth is completed, nickel element remains in the film at a relatively high concentration.
[0070]
When the crystallization is completed, the silicon film is patterned to obtain a pattern indicated by 108 in FIG. This pattern will later constitute the active layer of the TFT.
[0071]
Here, the pattern 108 of the silicon film is configured using a region where the lateral growth indicated by 107 is performed.
[0072]
Note that the film thickness of the pattern 108 is 100 nm or less, preferably 50 nm or less.
[0073]
Next, a silicon oxide film 109 functioning as a gate insulating film is formed to a thickness of 100 nm by plasma CVD. In this way, the state shown in FIG.
[0074]
Next, an aluminum pattern 110 is formed. Here, an aluminum film is first formed to a thickness of 400 nm by sputtering. Further, by patterning it using the resist mask 100, a pattern indicated by 110 is obtained. In this way, the state shown in FIG.
[0075]
Next, anodic oxidation using the aluminum pattern 110 as an anode is performed with the resist mask 100 remaining. In this step, an anodic oxide film 111 is formed to a thickness of 400 nm.
[0076]
Here, because the anodic oxidation is performed with the resist mask 100 remaining, the anodic oxidation selectively proceeds in the side surface direction of the pattern, and an anodic oxide film is formed in a shape as indicated by 111.
[0077]
Here, anodic oxidation is performed using platinum as a cathode and an aqueous solution containing 3% by volume of oxalic acid as an electrolytic solution. Moreover, this anodic oxide film is obtained as having a porous shape (porous shape).
[0078]
Next, the resist mask 100 is removed, and anodic oxidation is performed again. Here, the anodic oxide film 112 is formed to a thickness of 70 nm.
[0079]
Here, an electrolytic solution obtained by neutralizing an ethylene glycol solution containing 3% tartaric acid with aqueous ammonia is used. The anodized film formed in this step has a dense barrier type film quality.
[0080]
In this step, an anodic oxide film is formed around the aluminum pattern 113 as indicated by 112 because the electrolytic solution penetrates into the porous anodic oxide film 111. In this way, the state shown in FIG.
[0081]
Here, the pattern indicated by 112 is the pattern of the gate electrode and the gate wiring extending therefrom.
[0082]
An offset region can be formed adjacent to the channel region later by the thickness of the anodic oxide film 112.
[0083]
However, in this embodiment, since the thickness of the anodic oxide film 112 is as thin as 70 nm, an offset region that functions effectively is not formed. Therefore, the existence of the offset area is ignored here.
[0084]
If the thickness of the anodic oxide film 112 is 150 nm or more, an offset region whose function cannot be ignored is formed.
[0085]
After the anodic oxide film 112 is formed, phosphorus is doped by plasma doping. The phosphorus dose is determined under the condition that the doped region is a source region and a drain region. Further, this doping is preferably performed under the condition that the concentration of phosphorus finally present is higher than the concentration of nickel after gettering. By doing so, gettering of nickel element can be performed more effectively in a later step.
[0086]
In this step, as shown in FIG. 2A, phosphorus is doped in the regions 114 and 116 in a self-aligning manner. In addition, the region 115 is not doped.
[0087]
Note that an ion implantation method may be used for doping. In any case, this doping step preferably uses a method of ionizing an impurity element and electrically accelerating it.
[0088]
Further, the exposed silicon oxide film 109 may be removed before doping. In this case, the silicon oxide film formed on the surfaces 114 and 116 in FIG. 2A is removed.
[0089]
After the doping shown in FIG. 2A, the porous anodic oxide film 111 is removed. Again, phosphorus is doped by plasma doping.
[0090]
In this step, doping is performed with a low dose amount as compared with the dose amount in the step of FIG.
[0091]
In this step, regions 117 and 119 are formed as low concentration impurity regions. The low-concentration impurity region means that the concentration of contained phosphorus is low compared to the regions 114 and 116.
[0092]
Further, as a result of this step, a region where the doping indicated by 118 is not performed becomes a channel region of the TFT. In this way, the state shown in FIG.
[0093]
Next, heat treatment is performed at 450 ° C. for 2 hours in a nitrogen atmosphere. In this process, the nickel element is gettered by phosphorus in the process of diffusing. As a result, the nickel concentrations in the regions 114 and 116, the regions 117 and 119, and then the region 115 are lowered.
[0094]
Here, phosphorus is also doped in the regions 117 and 119 with a low dose, but according to experiments, gettering of nickel is mainly performed in the regions 114 and 116.
[0095]
Phosphorus and nickel are NiP, NiP ₂ , Ni ₂ Forms of various compounds such as P ... Moreover, the bonding state is extremely stable, and exists in a stable state at a heating temperature of about 450 ° C.
[0096]
That is, once nickel and phosphorus are bonded, they are not decomposed again from that state. (At least not the temperature in the process of this embodiment)
[0097]
Further, phosphorus in silicon does not diffuse unless it is about 800 ° C. or higher.
[0098]
Therefore, as a result, nickel elements are concentrated in the regions 114 and 116 where phosphorus is present in high concentration.
[0099]
In this way, as shown in FIG. 2C, a state in which the nickel element has moved to the regions 114 and 116 as indicated by the arrows 120 and 121 is obtained.
[0100]
The nickel element moves to the low concentration impurity regions 117 and 119, but the nickel element moves to the regions 114 and 116 doped with phosphorus at a higher concentration. Is done.
[0101]
FIG. 3 shows a distribution state of nickel element and phosphorus element after the heat treatment. Further, in this heat treatment stage, the crystallinity of the regions 114, 116, 117, and 119 where the crystallinity is destroyed by accelerated implantation of impurity ions progresses.
[0102]
This is largely related to the concentration of nickel element in those regions (particularly regions 114 and 116).
[0103]
That is, in the region where the nickel element is concentrated, crystallization due to the action of the nickel element is strongly promoted, and the damage to the crystal structure caused during the doping of phosphorus ions is recovered.
[0104]
In particular, in the structure shown in this embodiment, since phosphorus ions are concentrated at a higher concentration in a region where phosphorus is doped at a high concentration (that is, a region where the crystallinity is further destroyed), the crystallinity in this step is reduced. Improvement proceeds effectively.
[0105]
Next, laser light irradiation is performed to activate the doped phosphorus. Annealing of the crystalline damage caused during doping can be performed by heat treatment as described above.
[0106]
However, since the temperature is as low as 450 ° C., the activation rate of the dopant (phosphorus) is low. Therefore, in this embodiment, the dopant is activated by irradiating laser light in addition to heating.
[0107]
By performing this step, the regions 114 and 116 can function as source and drain regions.
[0108]
When the laser light irradiation is completed, a silicon nitride film 122 is formed to a thickness of 200 nm by plasma CVD as shown in FIG.
[0109]
Further, a silicon oxide film 123 is formed to a thickness of 400 nm by plasma CVD.
[0110]
Further, an acrylic resin film 124 is formed. The thickness of the acrylic resin film is set to 700 nm at the minimum portion.
[0111]
As materials other than acrylic, materials such as polyimide, polyamide, polyimide amide, and epoxy can be used.
[0112]
When the structure shown in this embodiment is employed, the obtained N-channel TFT includes phosphorus and nickel in high concentration in the source and drain regions. The low concentration impurity regions 114 and 116 contain phosphorus at a lower concentration.
[0113]
In addition, the channel region 118 and the low-concentration impurity regions 117 and 119 hardly contain nickel.
[0114]
This density distribution state is shown in FIG. Thus, a TFT having a special concentration distribution with respect to nickel and phosphorus can be obtained.
[0115]
The TFT shown in this embodiment has a process temperature of about 600 ° C. or less that can be withstood by a glass substrate, and can be made into an active layer having high crystallinity by utilizing nickel element. Obtainable.
[0116]
The characteristics of the TFT obtained in this example are superior to those of the high-temperature polycrystalline polysilicon TFT.
[0117]
In addition, since the nickel element is fixed in the source / drain regions that do not affect the operation, high characteristics can be stably obtained. Further, even when a large number of TFTs are manufactured at the same time, variation in characteristics can be reduced.
[0118]
[Example 2]
In this example, the manufacturing process shown in Example 1 is further improved. 4 and 5 show a manufacturing process of this embodiment.
[0119]
1 having the same reference numerals as those in FIG. 1 have the same manufacturing process and function as those shown in FIG.
[0120]
First, as shown in FIG. 4A, a silicon oxide film 102 is formed over a glass substrate 101, and an amorphous silicon film 103 is further formed.
[0121]
Next, a mask 104 made of a silicon oxide film is formed, and a nickel acetate solution is applied to obtain a state where the nickel element is held in contact with the surface as indicated by 106.
[0122]
Next, heat treatment is performed, and lateral growth as indicated by 107 is performed. (Fig. 4 (B))
[0123]
When the lateral growth shown in FIG. 4B is completed, the mask 104 made of a silicon oxide film is removed, and a mask 401 made of a silicon oxide film is placed again.
[0124]
Then, phosphorus ions are doped by a plasma doping method using the mask 401.
[0125]
In this step, phosphorus is doped in the region 403. Next, heat treatment is performed. This heat treatment is performed in a nitrogen atmosphere at 600 ° C. for 2 hours.
[0126]
At this time, the nickel element is gettered to the region 403. In the region 402 where phosphorus is not doped, the concentration of nickel element is greatly reduced.
[0127]
When the gettering step is completed, the mask 401 made of a silicon oxide film is removed, and a resist mask is further arranged for patterning to obtain a pattern 108 shown in FIG. This pattern is a pattern that later becomes the active layer of the TFT.
[0128]
The pattern 108 is formed as a pattern that is smaller than the area 402 covered with the mask 401.
[0129]
This is because the influence of nickel is more positively eliminated by forming the active layer pattern 108 of the TFT using the region where the gettering has been performed (region 402).
[0130]
After the pattern 108 of the active layer is formed, a silicon oxide film 109 that functions as a gate insulating film is formed by plasma CVD. In this way, the state shown in FIG.
[0131]
Next, an aluminum pattern 110 shown in FIG. 4E is formed using the resist mask 100.
[0132]
Next, as shown in FIG. 5A, a porous anodic oxide film 111 and an anodic oxide film 112 having a dense film quality are formed.
[0133]
Next, in this state, phosphorus is doped by plasma doping. In addition to the plasma doping method, a plasma doping method can be used.
[0134]
Since this doping is performed at a higher concentration than doping performed later, it will be referred to as heavy doping for convenience.
[0135]
In this doping, heavy doping is performed in the regions 114 and 116. In addition, the region 115 is not doped.
[0136]
Next, the porous anodic oxide film 111 is removed. Then, doping of phosphorus is performed again. This doping is performed with a low dose compared to the previous doping.
[0137]
As a result of this step, low-concentration impurity regions 117 and 119 are formed. In addition, a channel region 118 is formed. (Fig. 5 (C))
[0138]
In the present embodiment, these regions are formed in a self-aligned manner.
[0139]
Next, heat treatment is performed to concentrate the nickel element remaining in the active layer pattern in the regions 114 and 116. That is, the nickel element remaining in the active layer pattern is gettered to the regions 114 and 116. (Fig. 5 (D))
[0140]
In this way, it is possible to more thoroughly eliminate the presence of nickel in the vicinity of the channel region and the boundary between the channel region and the low-concentration impurity region, which are problematic for the operation of the TFT.
[0141]
At this time, annealing of crystal structure damage caused during doping is simultaneously performed.
[0142]
Next, laser light irradiation is performed to activate the dopant.
[0143]
Next, as shown in FIG. 6A, a silicon nitride film 122 and a silicon oxide film 123 are formed by a plasma CVD method. Then, an acrylic resin film 124 is formed.
[0144]
Next, contact holes are formed, and a source electrode 125 and a drain electrode 126 are formed. In this way, an N-channel TFT in which nickel element is more thoroughly removed from the channel region and the region having a different conductivity type junction can be obtained.
[0145]
Example 3
In this embodiment, an example in which an offset region is arranged instead of the low-concentration impurity regions 117 and 119 (see FIG. 2) in the structure shown in Embodiment 1 is shown.
[0146]
In this embodiment, phosphorus ions are not implanted at a low dose in the step shown in FIG. That is, the doping in FIG. 2B is not performed.
[0147]
In such a case, the regions 117 and 119 are not doped with phosphorus. The conductivity type of this portion is basically the same as that of the channel region 118.
[0148]
However, in the regions 117 and 119, unlike the channel, no inversion layer is formed by application of an electric field from the gate electrode. (The electric field from the gate electrode is broad and not strictly speaking, but I think so here to simplify the discussion.)
[0149]
The regions 117 and 119 function as high resistance regions during the operation of the TFT as in the low concentration impurity region. In other words, it has a function of relaxing the electric field strength formed between the channel region and the drain region, and improving the breakdown voltage and leakage characteristics.
[0150]
In this embodiment, the areas 117 and 119 are offset areas.
[0151]
Even in the case of the TFT shown in this embodiment, the concentration of the metal element can be reduced in the channel region, the boundary between the channel and the region adjacent to the channel, and the vicinity thereof.
[0152]
And
・ Improved breakdown voltage and leakage current characteristics
・ Improved reliability
・ Reduction of variation in characteristics among elements
Such effects can be obtained.
[0153]
Example 4
The present embodiment relates to a technique of forming the offset region with the thickness of the dense anodic oxide film 112 in FIG.
[0154]
In the case of this embodiment, the offset region is formed between the channel region 118 and the low concentration impurity region 117 and between the channel region 118 and the low concentration impurity region 119 shown in FIG.
[0155]
In the case of this embodiment as well, since the process shown in FIG. 2C is performed, the nickel concentration in the channel region and the nickel concentration at the interface between the channel region and the offset region can be reduced.
[0156]
Example 5
This embodiment is an example where the channel region is doped with an impurity imparting conductivity type in the structure shown in Embodiment 1 or other embodiments.
[0157]
In general, in the case of a thin film transistor, an intrinsic or substantially intrinsic semiconductor that does not perform artificial doping is used for a channel region.
[0158]
However, there is also known a technique for finely controlling the conductivity type of the channel region in order to control characteristics as represented by threshold control. This technique is called channel doping technique.
[0159]
The following two methods are mainly adopted as a method for performing channel doping.
(1) An ion implantation method or a plasma doping method is used.
(2) A dopant is doped in the starting film constituting the active layer.
[0160]
In this embodiment, the method is used in (2). Here, an example in which boron is doped in a channel is shown on the premise that an N-channel TFT is manufactured.
[0161]
In this embodiment, the amorphous silicon film 103 in the stage shown in FIG. 1A is formed by a low pressure thermal CVD method using disilane and diborane as source gases.
[0162]
At this time, the doping amount of the channel dope can be changed by changing the addition amount of diborane.
[0163]
Here, an example of manufacturing a channel type TFT is shown. However, if a P channel type TFT is manufactured, phosphine is used as a doping gas.
[0164]
Example 6
In this example, an example in which a p-channel TFT is manufactured using the invention disclosed in this specification will be described.
[0165]
Nickel gettering cannot be performed with boron. At least a remarkable gettering effect as in the case of using phosphorus cannot be obtained.
[0166]
Therefore, when a P-channel TFT is manufactured using the invention disclosed in this specification, phosphorus doping for use in nickel gettering and dopant for forming source and drain regions (this In this case, boron doping must be performed separately.
[0167]
A manufacturing process of this embodiment will be described with reference to FIGS. First, according to the manufacturing process shown in Example 1, the state shown in FIG.
[0168]
In this state, phosphorus is doped by plasma doping (or ion implantation). In this state, phosphorus is doped in regions 701 and 703 in FIG. 7A. Further, the region 702 is not doped with phosphorus.
[0169]
Here, the reason why the regions 701 and 703 are doped with phosphorus is to remove nickel elements existing in the region 702 by using these regions as gettering sites.
[0170]
After the doping shown in FIG. 7A is completed, heat treatment is performed at 450 ° C. for 2 hours in a nitrogen atmosphere. In this step, the nickel element is moved from the region 702 to the regions 701 and 703 as indicated by arrows 704.
[0171]
That is, the nickel element in the region 702 is gettered to the regions 701 and 703.
[0172]
Here, the heating temperature is set to 450 ° C. because aluminum is used for the gate electrode. In the case where a silicon material, a silicide material, or a metal material is used for the gate electrode, it is preferable that the heat resistance is higher in view of the heat resistance of the substrate.
[0173]
Next, as shown in FIG. 7C, boron is doped by plasma doping. The doping method may be an ion implantation method.
[0174]
The doping in this step is for making the regions 705 and 707 the source and drain regions. Therefore, a doping condition is required in which boron is doped at a higher concentration than phosphorus doped in the step shown in FIG. 7A and the N-type regions 701 and 703 are inverted to P-type.
[0175]
After the doping shown in FIG. 7C is completed, the porous anodic oxide film 111 is removed.
[0176]
Then, boron doping is performed again as shown in FIG. Since this step is for forming a low-concentration impurity region, it is performed under such a condition that the conductivity type is weaker than the regions 705 and 707 doped in the step (C).
[0177]
Since the regions 708 and 710 are not doped with phosphorous in the process of FIG. 7A, the region 708 and 710 do not need to have a doping condition that inverts the conductivity type as in the regions 711 and 712.
[0178]
After the doping is completed, laser light irradiation is performed to repair damage caused during doping in the doped region and activate the dopant. This step may be performed by heating.
[0179]
In this manner, the source region 711, the drain region 712, the channel region 709, and the low concentration impurity regions 708 and 710 are formed.
[0180]
Here, nickel is gettered in the source region 711 and the drain region 712.
[0181]
Also in this configuration, the nickel element is reduced in the vicinity of the junction existing at the boundary between the channel and the region adjacent to the channel.
[0182]
As a result, in a P-channel TFT, it is possible to obtain effects such as an increase in breakdown voltage, a reduction in OFF current, an improvement in reliability, and a reduction in variation in characteristics of each element.
[0183]
A feature of the TFT shown in this embodiment is that the source and drain regions are doped with phosphorus and boron, and the concentration of boron is higher than that of phosphorus.
[0184]
In addition, the nickel concentration in the source and drain regions is higher than that in the channel region and the low concentration impurity region.
[0185]
Example 7
In this embodiment, a configuration obtained by improving the configuration shown in the sixth embodiment is shown. In the configuration shown in the sixth embodiment, an example in which a low-concentration impurity region is disposed adjacent to the channel region is shown. (Ignore the existence of the offset region due to the thickness of the anodized film)
[0186]
Here, an example in which the region that has been the low-concentration impurity region is used as an offset region is shown.
[0187]
In this example, light doping of boron is not performed at the stage shown in FIG. In this case, boron is not doped in the regions 708 and 710, and these regions become offset regions.
[0188]
Even if the structure shown in this embodiment is not adopted, if the thickness of the dense anodic oxide film formed around the gate electrode is increased, an offset region can be formed adjacent to the channel region. it can.
[0189]
Example 8
This embodiment is an example in which tantalum (Ta) is used as the gate electrode instead of aluminum in the other embodiments.
[0190]
Anodization technology can also be used when tantalum is used. Then, the formation of the low concentration impurity region and the offset region using the anodic oxide film can be performed in the same manner as when aluminum is used.
[0191]
Since tantalum has higher heat resistance than aluminum, the heating temperature in the heat treatment step shown in FIG. 2C can be set to 600 ° C. for 2 hours, for example.
[0192]
Since the melting point of tantalum is 2000 ° C. or higher, it is not necessary to pay particular attention to the heat treatment temperature.
[0193]
Example 9
This embodiment is an example in which silicon having a conductivity type is used instead of aluminum as a gate electrode in another embodiment.
[0194]
Here, the gate electrode is formed using a silicon film doped with phosphorus or boron. Even when a silicon material is used for the gate electrode, the heating temperature in the heat treatment step shown in FIG.
[0195]
As the gate electrode, various silicide materials and metal materials can be used.
[0196]
In the case where a silicon material or a silicide material is used as the gate electrode material, it is necessary to use a material that is replaced with an anodic oxidation technique as a means for forming the low concentration impurity region.
[0197]
FIG. 8 shows an example of a TFT manufacturing process when a silicon material is used as the gate electrode.
[0198]
First, according to the manufacturing steps shown in FIGS. 1A to 1C shown in Example 1, a silicon oxide film 102 is formed as a base film on a glass substrate 101 as shown in FIG. Further, an active layer 108 made of a crystalline silicon film is formed.
[0199]
In this state, the active layer 108 contains nickel element at a relatively high concentration. Further, the distribution state of the nickel element is not particularly biased and is uniform.
[0200]
At the stage of forming the gate insulating film 109, a silicon film doped with phosphorus at a high concentration is formed by using a low pressure thermal CVD method and patterned using a resist mask 802. In this way, a pattern indicated by 801 is obtained. A gate electrode is formed later based on the pattern 801 made of the silicon film. In this way, the state shown in FIG.
[0201]
Next, the pattern 801 made of a silicon film is etched by using isotropic dry etching or wet etching. At this time, the etching is side etching as shown in FIG. 8B due to the presence of the resist mask 802.
[0202]
When the side etching is completed, phosphorus doping is performed, and phosphorus is doped in the regions 803 and 805. This doping is performed to form source and drain regions and to form a gettering site.
[0203]
This doping is referred to as heavy doping for convenience because it is performed at a higher dose than the doping performed later.
[0204]
After the doping shown in FIG. 8C is completed, the resist mask 802 is removed. Next, phosphorus is doped again. Doping at this time is performed with a lower dose than in the step (C). The doping in this step is referred to as light doping for convenience.
[0205]
In this step, low concentration impurity regions 807 and 808 are formed. Then, heat treatment is performed at 600 ° C. for 2 hours in a nitrogen atmosphere. This heat treatment is performed under conditions where phosphorus does not diffuse, at a temperature as high as possible, and at a temperature below the strain point of the glass substrate 101.
[0206]
In this step, the nickel element existing in the active layer pattern 108 is concentrated in the regions 803 and 805. This state can also be regarded as nickel elements in the regions 807, 808, and 809 gettered in the regions 803 and 805.
[0207]
Thus, the region indicated by reference numeral 804 in FIG. 8C has a reduced nickel element.
[0208]
Next, the resist mask 802 is removed, and phosphorus is doped in the state shown in FIG. This step is performed with a lower dose than the doping in the step (C). The doping in this step is referred to as light doping for convenience.
[0209]
In this step, low-concentration impurity regions 807 and 808 are formed in a self-aligned manner. A channel formation region 809 is also formed in a self-aligned manner.
[0210]
Thereafter, a TFT may be manufactured according to the same process as shown in the first embodiment.
[0211]
In the manufacturing process shown in this embodiment, the regions 807 and 808 can be formed as offset regions if light doping in the step shown in (D) is not performed.
[0212]
As shown in this embodiment, if a structure in which a low concentration impurity region or an offset region is formed by a method that does not use an anodic oxidation technique, the invention disclosed in this specification is based on aluminum or tantalum as a material of a gate electrode. It is not limited only to the case where such a material is used.
[0213]
However, in order to use the invention disclosed in this specification, the structure needs to have a low-concentration impurity region and / or an offset region.
[0214]
Example 10
This embodiment is an example in which the invention disclosed in this specification is applied to an inverted stagger type TFT.
[0215]
9 and 10 show a manufacturing process of this example. First, the gate electrode 902 is formed on the glass substrate 901. Here, the gate electrode 902 is formed using tangten silicide.
[0216]
Next, a silicon oxide film 903 that functions as a gate insulating film is formed. Further, an amorphous silicon film 904 is formed as a starting film constituting the active layer. In this way, the state shown in FIG.
[0217]
When the state shown in FIG. 9A is obtained, crystallization using nickel is performed to obtain a crystalline silicon film 900. (Fig. 9 (B))
[0218]
Next, a resist mask 905 is disposed. Then, phosphorus is doped so that the region 906 is selectively doped with phosphorus. (Fig. 9 (B))
[0219]
Next, the resist mask 905 is removed. Then, heat treatment is performed at 600 times for 2 hours in a nitrogen atmosphere. The heating temperature at this time is almost governed by the heat resistance of the glass substrate.
[0220]
During this heat treatment, the nickel element in the film moves toward the region 906 along the path indicated by 907. That is, the nickel element in the silicon film is gettered to the region 906. (Fig. 9 (C))
[0221]
Next, the silicon film is patterned to obtain a pattern indicated by 908. This pattern constitutes the active layer of the TFT. (Figure 9 (D))
[0222]
It is important for this pattern 908 to avoid a region 906 that serves as a gettering site.
[0223]
This is because the gettering site contains nickel element at a high concentration.
[0224]
That is, it is important that the nickel gettering sites indicated by 906 are completely removed.
[0225]
Next, a resist mask 909 is arranged as shown in FIG.
[0226]
Then, using the resist mask 909, phosphorus is doped in the regions 910 and 911. This doping is performed under heavy doping conditions. (Fig. 10 (B))
[0227]
Next, the resist mask 909 is retracted by isotropic ashing to form a resist mask pattern as indicated by 912 in FIG.
[0228]
In this state, light doping of phosphorus is performed. In this step, phosphorous light doping is performed in the regions 914 and 915.
[0229]
Next, heat treatment is performed at 600 ° C. for 2 hours in a nitrogen atmosphere. In this way, nickel elements still remaining in the active layer mainly in the regions 910 and 911 are gettered.
[0230]
Next, the resist mask 912 is removed, and laser light irradiation and / or heat treatment is performed to activate the doped region.
[0231]
Thus, a source region 910, a drain region 911, low-concentration impurity regions 914 and 915, and a channel region 913 are formed.
[0232]
Next, a silicon oxide film 916 is formed as an interlayer insulating film, and a resin film 917 is further formed. (Figure 10 (D))
[0233]
Further, contact holes are formed, and a source electrode 918 and a drain electrode 919 are formed. Thus, a bottom gate type TFT is completed.
[0234]
Example 11
In this embodiment, a method different from the crystallization method using nickel shown in the other embodiments is used.
[0235]
The crystal growth method shown in FIG. 1 is called lateral growth. By aligning the crystal growth direction axis with the nickel gettering direction axis and the carrier movement direction axis during operation, High electrical characteristics can be obtained.
[0236]
However, this method has a problem that the method of introducing nickel element (which is the same even when other metal elements are used) used for crystallization is complicated, and the number of steps increases accordingly.
[0237]
In the method shown in this embodiment, after an amorphous silicon film is formed, nickel element is introduced into the entire surface. (The same applies when other metal elements are used.)
[0238]
For example, in the process shown in FIG. 1, a nickel acetate solution is applied to the entire surface in a stage where the entire surface of the amorphous silicon film 103 is exposed without disposing the mask 104 made of a silicon oxide film.
[0239]
In this way, the trouble of arranging the mask can be saved. However, since crystallization proceeds on the entire surface, characteristics as high as those in the case of lateral growth cannot be obtained.
[0240]
In other words, the characteristics of the resulting TFT are not as great as when lateral growth is used. However, it is possible to obtain characteristics higher than those of a conventional TFT using a crystalline silicon film obtained without using the metal element.
[0241]
Example 12
In this embodiment, an example of a semiconductor device using the invention disclosed in this specification will be described. That is, an example of a semiconductor device using a TFT using the invention disclosed in this specification is shown.
[0242]
FIG. 11 shows examples of various semiconductor devices. These semiconductor devices use TFTs at least in part.
[0243]
FIG. 11A illustrates a portable information processing terminal. This information processing terminal includes an active matrix type liquid crystal display or an active matrix type EL display in a main body 2001, and further includes a camera unit 2002 for capturing information from the outside.
[0244]
In the camera unit 2002, an image receiving unit 2003 and an operation switch 2004 are arranged.
[0245]
Information processing terminals are considered to become thinner and lighter in order to improve their portability.
[0246]
In such a configuration, it is preferable that the on-substrate peripheral driving circuit, the arithmetic circuit, and the memory circuit on which the active matrix display 2005 is formed are integrated with TFTs.
[0247]
FIG. 11B shows a head mounted display. This apparatus includes an active matrix liquid crystal display or an EL display 2102 in a main body 2101. The main body 2101 can be attached to the head with a band 2103.
[0248]
FIG. 11C shows a projection type liquid crystal display device, which is called a front projection type device.
[0249]
This apparatus has a function of optically modulating light from a light source source 2202 provided in a main body 2201 with a reflective liquid crystal display device 2203, expanding it with an optical system 2204, and projecting an image onto a screen 2205. .
[0250]
In such a configuration, the optical system 2204 is required to be miniaturized as much as possible due to cost. Correspondingly, the display device 2203 is also required to be downsized.
[0251]
When an active matrix type flat panel display is miniaturized, it is required to integrate a peripheral driving circuit for driving the active matrix circuit on the same substrate as the active matrix circuit.
[0252]
This is because when the active matrix circuit is downsized, it is difficult to mount the peripheral drive circuit even if the circuit constituting the peripheral drive circuit is configured with an external IC.
[0253]
Therefore, the display device 2203 employs a structure in which an active matrix circuit and a peripheral driver circuit are integrated with TFTs over the same substrate.
[0254]
Here, an example in which a reflective type is used as the liquid crystal display device 2503 is shown. However, a transmissive liquid crystal display device may be used here. In this case, the optical system is different.
[0255]
A mobile phone is illustrated in FIG. This device includes an active matrix liquid crystal display device 2304, an operation switch 2305, an audio input unit 2303, an audio output unit 2302, and an antenna 2306 in a main body 2301.
[0256]
Recently, a configuration in which the portable information processing terminal shown in (A) and the mobile phone shown in (D) are combined has been commercialized.
[0257]
FIG. 11E illustrates a portable video camera. The main body 2401 includes an image receiving unit 2406, an audio input unit 2403, operation switches 2404, an active matrix liquid crystal display 2402, and a battery 2405.
[0258]
FIG. 11F illustrates a rear projection type liquid crystal display device. In this configuration, the main body 2501 includes a projection screen. In the display, the light from the light source 2502 is separated by the polarization beam splitter 2504, the separated light is optically modulated by the reflective liquid crystal display device 2503, and the optically modulated image is reflected and reflected by the reflectors 2505 and 2506. It is reflected and projected onto the screen 2507.
[0259]
Here, an example in which a reflective type is used as the liquid crystal display device 2503 is shown. However, a transmissive liquid crystal display device may be used here. In this case, the optical system may be changed.
[0260]
【The invention's effect】
By using the invention disclosed in this specification, in a TFT manufactured using a crystalline silicon film crystallized using a specific metal element, the influence of the metal element adversely affects the device characteristics of the TFT. This can be suppressed.
[Brief description of the drawings]
FIGS. 1A and 1B illustrate a manufacturing process of a TFT. FIGS.
FIGS. 2A and 2B are diagrams illustrating a manufacturing process of a TFT. FIGS.
FIG. 3 is a diagram showing a concentration distribution of nickel and phosphorus in an active layer of a TFT.
4A and 4B are diagrams showing a manufacturing process of a TFT.
FIGS. 5A and 5B are diagrams illustrating a manufacturing process of a TFT. FIGS.
6A and 6B illustrate a manufacturing process of a TFT.
FIGS. 7A and 7B are diagrams illustrating a manufacturing process of a TFT. FIGS.
FIGS. 8A and 8B are diagrams illustrating a manufacturing process of a TFT. FIGS.
FIGS. 9A and 9B illustrate a manufacturing process of a TFT. FIGS.
10A and 10B illustrate a manufacturing process of a TFT.
FIG 11 illustrates an example of a semiconductor device.
FIG. 12 is a diagram showing a Ni concentration distribution in an active layer of a TFT.
[Explanation of symbols]
101 glass substrate
102 Base film (silicon oxide film)
103 Amorphous silicon film
104 Made of silicon oxide film
105 opening
106 Elemental nickel held in contact with the surface
107 Crystal growth direction
108 Active layer pattern
109 Gate insulating film (silicon oxide film)
110 Aluminum pattern
100 resist mask
111 Porous anodic oxide film
112 Anodized film with dense film quality
113 Gate electrode
114 High-concentration impurity region to be a source region
115 Undoped region
116 High-concentration impurity region to be a drain region
117 Low concentration impurity region
118 channel region
119 Low concentration impurity region
120 Movement direction of nickel element
121 Movement direction of nickel element
122 Silicon nitride film
123 Silicon oxide film
124 Acrylic resin film
125 source electrode
126 Drain electrode

Claims (12)

A crystalline silicon film crystallized using a metal element that promotes crystallization of silicon;
The crystalline silicon film includes a low-concentration impurity region containing boron adjacent to the channel region;
A source region or a drain region containing phosphorus and boron adjacent to the low concentration impurity region;
Have
The concentration of the boron contained in the source region or the drain region is higher than the concentration of phosphorus,
The concentration of the metal element in the source region or the drain region is a 1 × 10 ¹⁹ atoms / cm ³ or more, the concentration of the metal element in the channel region and the low concentration impurity region is 1 × 10 ¹⁷ atoms / A thin film transistor having a size of cm ³ or less. A crystalline silicon film crystallized using a metal element that promotes crystallization of silicon;
The crystalline silicon film includes a low-concentration impurity region containing boron adjacent to the channel region;
A source region or a drain region containing phosphorus and boron adjacent to the low concentration impurity region;
Have
The concentration of the boron contained in the source region or the drain region is higher than the concentration of phosphorus,
The source region or the drain region contains boron at a higher concentration than the low concentration impurity region,
The concentration of the metal element in the source region or the drain region is a 1 × 10 ¹⁹ atoms / cm ³ or more, the concentration of the metal element in the channel region and the low concentration impurity region is 1 × 10 ¹⁷ atoms / A thin film transistor having a size of cm ³ or less.   An active matrix liquid crystal display using the thin film transistor according to claim 1.   An active matrix EL display using the thin film transistor according to claim 1.   A portable information processing terminal comprising the active matrix type liquid crystal display according to claim 3.   A portable information processing terminal comprising the active matrix EL display according to claim 4.   A head-mounted display comprising the active matrix liquid crystal display according to claim 3.   A head mounted display comprising the active matrix EL display according to claim 4.   A mobile phone comprising the active matrix liquid crystal display according to claim 3.   A portable video camera comprising the active matrix type liquid crystal display according to claim 3.   A front projection type liquid crystal display device comprising the active matrix type liquid crystal display according to claim 3.   A rear projection type liquid crystal display device comprising the active matrix type liquid crystal display according to claim 3.

Images