JP4317105B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The invention disclosed in this specification relates to a method for manufacturing a semiconductor device using a silicon film formed over a substrate such as glass. For example, the present invention relates to a method for manufacturing a thin film transistor over a glass substrate.

Conventionally, a technique for manufacturing a thin film transistor on a glass substrate or a quartz substrate is known.

As the thin film transistor, a thin film transistor using an amorphous silicon film is mainstream, but recently, a thin film transistor using a crystalline silicon film has also been produced.

A thin film transistor using a crystalline silicon film is characterized in that high performance can be obtained.

However, it is also a fact that it is difficult to form a silicon film having high crystallinity uniformly over a large area.

Further, when considering using an inexpensive glass substrate as the substrate, a technique for obtaining a crystalline silicon film at a process temperature or lower that the glass substrate can withstand is required. This is an important technical issue in terms of cost.

One of the process temperatures that the glass substrate can withstand is a laser annealing process. The laser annealing process has an advantage that there is almost no thermal shock to the substrate.

But,
(1) It is difficult to perform uniform laser annealing over a large area.
(2) The oscillation intensity of the laser beam is unstable.
There is a problem.

As means for solving such a problem, a technique described in Japanese Patent Application Laid-Open No. 07-321339 is known.

This technique is a technique for obtaining a crystalline silicon film by heat treatment at a temperature that a glass substrate can withstand by introducing a metal element that promotes crystallization of silicon, such as nickel, into the amorphous silicon film.

Utilizing the technique described in the above-mentioned Japanese Patent Application Laid-Open No. 07-321339, a high-quality and good crystalline silicon film that has not been obtained so far (not simply means that the crystallinity is good, but has good characteristics) Meaning that a TFT having the same can be obtained) over a large area.

However, on the other hand, there are problems such as variation in characteristics and instability that are considered to be caused by residual metal elements.

An object of the invention disclosed in this specification is to provide means for solving this problem.

  One of the inventions disclosed in this specification includes a step of selectively introducing a metal element that promotes crystallization of silicon into an amorphous silicon film formed over a substrate having an insulating surface, and a heat treatment. Crystal growth is performed in a direction parallel to the substrate from a region where the metal element is selectively introduced, and a crystalline silicon film is obtained, and a part of the crystalline silicon film is masked, and an impurity element is provided in the other part. The step of accelerating the implantation of ions, the step of moving the metal element that promotes the crystallization of silicon present in the masked crystalline silicon film by heat treatment in an oxygen-containing atmosphere, Forming an active layer of the semiconductor device using the masked region.

A step of selectively introducing a metal element for promoting crystallization of silicon into an amorphous silicon film formed over a substrate having an insulating surface; and a region where the metal element is selectively introduced by performing heat treatment. Crystal growth in a direction parallel to the substrate, obtaining a crystalline silicon film, irradiating the crystalline silicon film with laser light, masking part of the crystalline silicon film, Impurity ion implantation of impurity elements is performed in a step of accelerating ion implantation of impurity elements in other portions, and a metal element that promotes crystallization of silicon existing in the crystalline silicon film by heat treatment in an oxygen-containing atmosphere. A step of moving to a region, and a step of forming an active layer of a semiconductor device using the masked region.

A step of selectively introducing a metal element for promoting crystallization of silicon into an amorphous silicon film formed over a substrate having an insulating surface; and a region where the metal element is selectively introduced by performing heat treatment. A step of crystal growth in a direction parallel to the substrate to obtain a crystalline silicon film; a step of masking a part of the crystalline silicon film; A step of moving the metal element from the masked region to a region doped with the impurity element by heat treatment in an atmosphere, and an active layer of a semiconductor device using the masked region. And a step of forming.

In the above structure, it is preferable to use Ni (nickel) as a metal element that promotes crystallization of silicon.

In addition, one or more elements selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au can be used as a metal element that promotes crystallization of silicon. .

Furthermore, it is preferable to use P (phosphorus) as the impurity element to be accelerated. In addition to P, a material selected from N, As, Sb, and Bi of the same group as P can be used.

In addition, it is important to select a region to be masked while avoiding a region where a metal element is selectively introduced.

 By utilizing the invention disclosed in this specification, the concentration of a metal element remaining in an active layer can be reduced even when a thin film transistor is manufactured using a crystallization method using a metal element that promotes crystallization of silicon. It can be reduced. Then, problems such as variation in characteristics and instability can be improved.

 As shown in FIG. 1A, by selectively introducing nickel, which is a metal element that promotes crystallization of silicon, and then performing heat treatment, the substrate 101 is subjected to heat treatment as shown at 17 in FIG. Crystal growth is performed in parallel directions.

Then, a part of the obtained crystalline silicon film 105 is masked with a resist mask 106, and P (phosphorus) ions are acceleratedly implanted into an unmasked region.

As a result, the regions 107 and 109 are doped with P ions. At this time, these regions are damaged by ion bombardment and become amorphous. Since the P element has a smaller atomic radius than the Si element, it can easily enter between Si atoms and effectively form defects. This defect later becomes a factor that positively moves the nickel element.

Then, as shown in FIG. 2A, by performing heat treatment in an atmosphere containing oxygen and chlorine, nickel element is transferred from the masked region 108 to the regions 107 and 109 where P is acceleratedly implanted. Can be moved.

At this time, an oxide film is formed on the surfaces of the regions 107 and 109, and nickel elements are gettered therein by the action of the halogen element.

Then, the areas 107 and 109 are removed. Thus, the nickel element is removed from the region 108. Then, an active layer of the thin film transistor is formed using this region.

Thus, a thin film transistor can be manufactured without the influence of nickel element.

1 and 2 show an outline of the manufacturing process of this example.

First, as shown in FIG. 1A, a silicon oxide film 102 is formed as a base film on a glass substrate 101 to a thickness of 300 nm by a plasma CVD method.

Next, an amorphous silicon film 103 is formed to a thickness of 40 nm by low pressure thermal CVD (or plasma CVD).

When the amorphous silicon film is formed, an extremely thin oxide film (not shown) is formed on the surface. Here, a very thin oxide film is formed by irradiating UV light in an oxygen atmosphere. This oxide film has a function of improving the wettability of a solution to be applied later.

Next, a mask 15 made of a silicon oxide film is formed. This mask is obtained by forming a silicon oxide film having a thickness of 100 nm by the plasma CVD method and patterning it.

The mask 15 has a slit-like opening 16. The amorphous silicon film 103 is exposed in the region of the slit 16.

Next, a nickel acetate solution containing 10 ppm (in terms of weight) of nickel is applied. Then, the excess solution is blown off by a spin coater.

As a result, a state in which the nickel element is held in contact as indicated by 104 is obtained. Here, the nickel element is held in contact with the surface of the amorphous silicon film 103 only in the region of the opening 16. (Fig. 1 (A))

When the state shown in FIG. 1A is obtained, heat treatment is performed at 600 ° C. for 6 hours. In this step, as indicated by 17, crystal growth proceeds in a direction parallel to the substrate 101 from a region where nickel element is selectively introduced (region of the opening 16). A crystalline silicon film 105 is thus obtained. (Fig. 1 (B))

This heat treatment can be performed at a temperature of 550 ° C to 700 ° C, preferably 600 ° C to 650 ° C. Note that the upper limit of the heating temperature needs to be lower than the strain point of the glass substrate.

Next, laser light is irradiated on the crystalline silicon film obtained as shown in FIG. Here, a KrF excimer laser (wavelength 248 nm) is used.

The excimer laser is a pulse oscillation type laser, and when this laser beam is irradiated, the irradiated region is repeatedly melted and solidified instantaneously.

By irradiating excimer laser light, a kind of non-equilibrium state is formed. Specifically, convex portions called ridges are formed on the surface, or nickel elements are partially segregated.

In such a non-equilibrium state, the nickel element is easy to move when some energy is given from the outside.

When the laser light irradiation is completed, a mask 106 made of a silicon oxide film is formed as shown in FIG.

It is important that the region covered with the mask 106 is provided so as to avoid the region where the nickel element is selectively introduced.

This is because the region that was not covered by the mask 106 later is removed, but at this time, the nickel element is introduced and the region where the crystal growth is started (the nickel element is contained in a relatively high concentration). It is because it is preferable to remove at the same time.

Next, P (phosphorus) element is doped by plasma doping (or ion implantation).

In this doping, conditions are set so that the concentration of P element is higher by one digit or more than the concentration of nickel element finally remaining in the film.

According to the measurement by the present inventors, the maximum value of the concentration of nickel element remaining in the silicon film at the time when the process of FIG. 1C is completed is about 1 × 10 ¹⁹ atoms cm ⁻³ .

Therefore, in this case, doping conditions are set so that doping of the P element remains at least about 1 × 10 ²⁰ atoms cm ⁻³ or more in the film.

This doping of P ions is performed on the regions 107 and 109 in FIG. As a result of this doping, the regions 107 and 109 contain P in a high concentration. In addition, these regions are made amorphous by the impact of implanted ions.

The region indicated by 108 is not doped with the P element because the mask 106 made of a silicon oxide film exists. In this state, the region 108 maintains crystallinity.

After the doping with P element, the sample is heated. Here, the sample is placed in a heating furnace having a mixed gas atmosphere of nitrogen (partial pressure ratio 88%), oxygen (partial pressure ratio 10%) and hydrogen chloride (partial pressure ratio 2%), and subjected to heat treatment at 400 ° C. for 30 minutes. Do.

In this step, nickel element in the region 108 moves to the regions 107 and 108 by the action of P (phosphorus). (Fig. 2 (A))

This movement of the nickel element is facilitated by the fact that the nickel element is easily moved by the laser beam irradiation earlier and that the regions 107 and 109 are made amorphous.

In particular, the fact that the regions 107 and 109 are amorphized and a large number of defects and strains are formed plays a major role in the movement of nickel element to those regions.

In this step, the regions 107 and 109 are locally etched excessively and become full of holes. (This area is not very useful for device formation)

In addition, when not irradiating a laser beam, it is necessary to raise this heating temperature to 600 degreeC or more. This is because the nickel element is not so easy to move.

When the heat treatment is finished, the mask 106 made of a silicon oxide film is removed. Then, a resist mask 110 is formed as shown in FIG. It is assumed that this resist mask is provided with some allowance so as to cover a smaller area than the region covered with the mask 106.

By using this resist mask 110, the silicon film is patterned. As a result, the region where the nickel element is segregated is removed. (The above process is called lateral gettering.)

Thus, a crystalline silicon film pattern indicated by 111 is obtained. This pattern will later become the active layer of the thin film transistor. (Fig. 2 (C))

This crystalline silicon film is one in which the nickel element in the film has been removed to the outside.

When the pattern indicated by 111 is obtained, the resist mask 110 is removed. A gate insulating film in which films 100 and 11 are laminated is provided so as to cover the silicon film pattern 111.

Here, a silicon oxide film 11 having a thickness of 100 nm is first formed by a plasma CVD method, and an oxide film 100 having a thickness of about 5 nm is further formed by a thermal oxidation method to form a gate insulating film.

In this case, a thermal oxide film 100 to be formed later is formed inside the silicon oxide film 11 formed by the CVD method. (Fig. 2 (D))

When the gate insulating film is formed, a gate electrode 113 mainly composed of aluminum is formed. An anodic oxide film 10 is formed on the gate electrode 12 by anodic oxidation after the pattern is formed. This anodized film has a function of electrically and mechanically protecting the surface of the aluminum film having low heat resistance.

Next, doping of impurities is performed to form source and drain regions. Here, P (phosphorus) ions are doped by a plasma doping method in order to manufacture an N-channel thin film transistor.

In this step, P elements are doped in the regions 112 and 114. 112 is a source region and 114 is a drain region. Further, the region 113 becomes a channel region.

Further, after the completion of doping, laser light irradiation is performed to anneal the damage caused during the doping and activate the doped dopant.

Next, as shown in FIG. 2E, a silicon nitride film 115 is formed as an interlayer insulating film to a thickness of 200 nm by plasma CVD.

Further, a polyimide resin film 116 is formed by spin coating. When a resin film is used for the interlayer insulating film, it is significant that the surface can be planarized.

As the material of the resin film, materials such as polyamide, polyimide amide, epoxy, and acrylic can be used.

Further, contact holes are formed, and a source electrode 117 and a drain electrode 118 are formed. Thus, the thin film transistor is completed. (Figure 2 (E))

In this embodiment, in the nickel gettering step shown in FIG. 2A, instead of heat treatment in an atmosphere containing a halogen element, treatment is performed with a mixed solution of hydrofluoric acid and perwater. At this time, nickel and nickel silicide are selectively etched.

The present embodiment relates to a method for controlling the threshold value of the TFT in the configuration shown in the first embodiment.

Here, a small amount of B (boron) is doped when the amorphous silicon film 103 shown in FIG. In order to perform this doping, a very small amount of B ₂ H ₆ is mixed in the film forming gas during film formation.

This is done because the threshold value of the TFT is controlled by making the channel region a weak P-type.

As a doping method, B (boron) may be doped by a plasma doping method or an ion implantation method after the amorphous silicon film is formed.

Note that if a P-channel TFT is manufactured, P (phosphorus) doping may be performed.

In this embodiment, a silicon material is used as the gate electrode in the configuration shown in the first embodiment.

This embodiment is an example in which an ion implantation method is used as a method for introducing a metal element that promotes crystallization of silicon in the process shown in Embodiment 1. That is, this is an example in which nickel elements are introduced into an amorphous silicon film by a method in which nickel ions are accelerated by an electric field and implanted into the amorphous silicon film.

When the ion implantation method is used, there is an advantage that the amount of nickel element introduced can be precisely controlled.

Further, when an ion implantation method is used for introducing nickel element, the mask 15 can be made of a resist.

In this case, the heat treatment for crystallization is performed with the resist removed.

This embodiment shows a process of manufacturing a complementary thin film transistor circuit by using the metal element removal method disclosed in this specification.

First, as shown in FIG. 3A, a base film 202 made of a silicon oxide film is formed over a glass substrate 201. Next, an amorphous silicon film 202 is formed.

Next, a mask 200 made of a silicon oxide film is formed. In this mask, an elongated opening 20 having a longitudinal shape in the depth direction and the near side in the drawing is formed.

Then, a nickel acetate salt solution is used to obtain a state in which nickel element is held in contact with the entire surface of the amorphous silicon film as indicated by 204. In this state, the nickel element is in contact with the amorphous silicon film 203 in the opening 20. (Fig. 3 (A))

Next, heat treatment is performed to crystallize the amorphous silicon film 203. At this time, crystal growth as indicated by an arrow 21 proceeds. (Fig. 3 (B))

Further, laser light irradiation is performed as shown in FIG.

Next, masks 206 and 207 made of a silicon oxide film are formed. (Fig. 3 (D))

Next, as shown in FIG. 3E, heavy doping of P (phosphorus) ions is performed.

In this step, P ions are acceleratedly implanted into the regions 208, 210, and 212. Further, P ions are not acceleratedly implanted into the regions 209 and 211.

Next, as shown in FIG. 4A, heat treatment is performed in a mixed atmosphere of HCl, oxygen, and nitrogen to perform gettering of nickel element.

Thereafter, the masks 206 and 207 made of a silicon oxide film are removed. Then, resist masks 213 and 214 are formed as shown in FIG.

Next, the silicon film is patterned using the resist masks 213 and 214. Thus, a pattern made of a crystalline silicon film indicated by 215 and 216 is obtained. One of the patterns becomes an active layer of a P-channel TFT. The other becomes an active layer of an N-channel TFT. (Fig. 4 (C))

Next, a gate insulating film composed of a thermal oxide film 218 and a silicon oxide film 219 formed by plasma CVD is formed.

Further, gate electrodes 211 and 223 made of aluminum are formed, and anodic oxide films 220 and 222 are formed on the surfaces thereof.

Next, the source region 224 and the drain region 226 of the P-channel type thin film transistor are formed by selectively doping P and B using a resist mask (not shown). In addition, a source region 229 and a drain region 227 of an N-channel thin film transistor are formed. (Fig. 4 (D))

Then, laser light irradiation is performed to activate the source and drain regions.

Next, a silicon nitride film 230 is formed as an interlayer insulating film, and a polyimide resin film 231 is further formed. Then, a contact hole is formed, and a source electrode 232 of a P-channel TFT, a source electrode 234 of an N-channel TFT, and a drain electrode 233 common to both TFTs are formed.

In this way, as shown in FIG. 4E, a P-channel TFT and an N-channel TFT are configured in a complementary manner.

In this embodiment, a manufacturing process of an inverted staggered thin film transistor is described. First, as shown in FIG. 5A, a silicon oxide film 402 is formed over a glass substrate 401 as a base film.

Then, a gate electrode 403 made of metal silicide is formed. Further, a gate insulating film 404 is formed.

Then, an amorphous silicon film 405 is formed. Next, a mask 400 made of a silicon oxide film is formed. An opening 40 is provided in this mask.

Next, a state in which nickel element is held in contact with the surface as indicated by 406 is obtained using a nickel acetate salt solution. (Fig. 5 (A))

Next, the amorphous silicon film 405 is crystallized by heating. At this time, crystal growth proceeds in the direction indicated by the arrow 41.

In this way, a crystalline silicon film 407 is obtained. (Fig. 5 (B))

Next, laser light irradiation is performed. (Fig. 5 (C))

Next, a mask 408 made of a silicon oxide film is formed. (Fig. 5 (D))

Next, heavy doping of P (phosphorus) element is performed. In this step, heavy doping of P element is performed in the regions 409 and 411. In addition, the region 410 is not doped. (Fig. 5 (E))

Next, heat treatment is performed in a mixed atmosphere of HCl, oxygen, and nitrogen, and nickel element is gettered as shown in FIG.

Thereafter, the mask 408 made of a silicon oxide film is removed, and a resist mask 408 is newly formed. (Fig. 6 (B))

Then, the silicon film is patterned using the resist mask 412. Thus, the silicon film pattern 413 is left. (Fig. 6 (C))

Next, a gate electrode 414 is provided, and further an impurity imparting one conductivity type is doped using the gate electrode as a mask. Thus, the source region 415 and the drain region 417 are formed. (Fig. 6 (D))

Then, laser light irradiation is performed to activate the source and drain regions.

Next, a silicon nitride film 418 and a polyimide resin film 419 are formed as an interlayer insulating film.

Further, contact holes are formed, and a source electrode 420 and a drain electrode 421 are formed. Thus, an inverted staggered thin film transistor is completed as shown in FIG.

In this embodiment, an outline of an apparatus using the invention disclosed in this specification is shown. FIG. 7 shows an outline of each device.

FIG. 7A shows a portable information processing terminal having a communication function using a telephone line.

This electronic device includes an integrated circuit 2006 using a thin film transistor inside a main body 2001. An active matrix liquid crystal display 2005, a camera unit 2002 for capturing an image, and an operation switch 2004 are provided.

FIG. 7B illustrates an electronic device called a head mounted display. This apparatus has a function of displaying an image in front of the eyes by wearing a main body 21201 on the head with a band 2103. The image is created by the liquid crystal display device 2102 corresponding to the left and right eyes.

Such an electronic device uses a circuit using a thin film transistor in order to be small and light.

FIG. 7C has a function of displaying map information and various information based on a signal from an artificial satellite. Information from the satellite captured by the antenna 2204 is processed by an electronic circuit provided inside the main body 2201, and necessary information is displayed on the liquid crystal display device 2202.

The operation of the apparatus is performed by an operation switch 2203. Even in such an apparatus, a circuit using a thin film transistor is used in order to reduce the overall configuration.

FIG. 7D illustrates a mobile phone. This electronic device includes a main body 2301 that includes an antenna 2306, an audio output unit 2302, a liquid crystal display device 2304, operation switches 2305, and an audio input unit 2303.

An electronic device illustrated in FIG. 7E is a portable imaging device called a video camera. The electronic apparatus includes a liquid crystal display 2402 attached to an opening / closing member and an operation switch 2404 attached to the opening / closing member.

Further, the main body 2401 includes an image receiving unit 2406, an integrated circuit 2407, an audio input unit 2403, operation switches 2404, and a battery 2405.

An electronic device illustrated in FIG. 7F is a projection liquid crystal display device. This device includes a light source 2502, a liquid crystal display device 2503, and an optical system 2504 in a main body 2501, and has a function of projecting an image onto a screen 2505.

Further, as the liquid crystal display device in the electronic device described above, either a transmission type or a reflection type can be used. The transmissive type is advantageous in terms of display characteristics, and the reflective type is advantageous when pursuing low power consumption and reduction in size and weight.

As a display device, a flat panel display such as an active matrix EL display or a plasma display can be used.

In this example, the manufacturing process of Example 1 shown in FIGS. 1 and 2 is modified. FIG. 8 shows a manufacturing process of this example.

First, a base film 102 and a crystalline silicon film 105 are formed on a glass substrate 101 according to the steps shown in FIG. Then, a mask 802 made of a silicon oxide film (or silicon nitride film) is formed using the resist mask 801. (Fig. 8 (A))

Next, heavy doping of P (phosphorus) is performed on the regions 107 and 109. (Fig. 8 (B))

Next, isotropic ashing is performed, and the resist mask 801 is isotropically retracted to a state as indicated by 803. (Fig. 8 (C))

Then, the mask 802 made of a silicon oxide film is patterned again using the receded resist mask 803, and a pattern made of a silicon oxide film indicated by 803 is formed. Then, the resist mask 803 is removed. (Fig. 8 (D))

In the state of FIG. 8D, heat treatment is performed to move the nickel element from the region 108 to the regions 107 and 109.

Then, the region of the silicon film indicated by 108 is patterned using the mask 804 to form a region 805 to be an active layer of the thin film transistor afterwards. After that, a thin film transistor is manufactured according to the steps described in Example 1 and other examples.

When the configuration shown in this embodiment is adopted, a silicon film pattern indicated by 805 can be formed in a self-aligning manner using a mask for implanting P ions.

The present embodiment relates to a structure obtained by improving the manufacturing process shown in the first embodiment. FIG. 9 shows a manufacturing process of this example.

First, the base film 102 is formed over the glass substrate 101 in accordance with the manufacturing process shown in Example 1. Further, a crystalline silicon film 105 is formed.

Next, a mask 901 made of a silicon oxide film (or silicon nitride film) is formed using the resist mask 902. (Fig. 9 (A))

Next, heavy doping of P (phosphorus) ions is performed. In this process, heavy doping of P is performed in the regions 107 and 109. (Fig. 9 (B))

Thereafter, the resist mask 902 is removed. Then, as shown in FIG. 9C, the nickel element is moved from the region 108 to the regions 107 and 109 by performing heat treatment.

Next, a region 108 of the silicon film is patterned using a mask 901 made of a silicon oxide film to obtain a region 902.

Next, isotropic etching is performed using a mask 901 made of a silicon oxide film, whereby the side surface of the pattern 902 of the silicon film is etched to obtain a pattern indicated by 903. (Figure 9 (D))

Next, the mask 901 is removed, and an active layer of the thin film transistor is formed using the silicon film pattern indicated by 903.

When the configuration shown in this embodiment is adopted, the mask 901 can be used twice, and the active layer pattern 903 can be obtained in a self-aligning manner.

Further, it is important that the region 107 or 109 containing nickel element at a high concentration does not exist in the patterning of the silicon film shown in FIG.

When etching is performed, it is feared that the nickel element is scattered and enters the region that will eventually become the active layer. For example, in the etching process for forming the pattern 805 as shown in FIG. 8E, there is a concern that nickel element enters the region 805 from the scattered matter in the regions 107 and 109 to be removed by etching.

However, in the process shown in FIG. 9E, since the region 107 or 109 containing nickel element at a high concentration does not exist, the above-mentioned concern can be eliminated.

In this example, an example in which the manufacturing process shown in Example 1 is improved will be described. First, as shown in FIG. 10A, a base film 102 is formed over a glass substrate 101, and a crystalline silicon film 105 is further formed.

Next, a mask formed of a stacked film of a silicon oxide film 1003 and a silicon nitride film 1002 is formed using the resist mask 1001. (Fig. 10 (A))

Next, heavy doping of P element is performed. (Fig. 10 (B))

Next, heat treatment is performed to move the nickel element from the region 108 to the regions 107 and 109. (Fig. 10 (C))

Next, using the silicon nitride film mask 1002, the silicon oxide film mask 1004 is etched by isotropic etching. As a result, a mask 1004 made of a silicon oxide film whose side surfaces are etched is obtained. (Figure 10 (D))

Next, the silicon nitride film mask 1002 is removed, and a silicon film pattern 1005 is obtained by using the silicon oxide film mask 1004 obtained in the step (D).

Also in this process, a silicon film pattern 1005 can be obtained in a self-aligning manner.

Further, in the process shown in FIG. 10, the following process may be performed.

When the step shown in FIG. 10C is completed, the exposed silicon film region, that is, the regions 107 and 109 are removed. And the process shown to (D) and (E) is implemented.

In this way, when the silicon film pattern 1005 is formed, it is possible to eliminate the influence of the nickel element contained in the region 107 or 109 at a high concentration.

10A and 10B illustrate a manufacturing process of a thin film transistor. 10A and 10B illustrate a manufacturing process of a thin film transistor. 10A and 10B illustrate a manufacturing process of a thin film transistor. 10A and 10B illustrate a manufacturing process of a thin film transistor. 10A and 10B illustrate a manufacturing process of a thin film transistor. 10A and 10B illustrate a manufacturing process of a thin film transistor. The figure which shows the structure of the apparatus using invention. 10A and 10B illustrate a manufacturing process of a thin film transistor. 10A and 10B illustrate a manufacturing process of a thin film transistor. 10A and 10B illustrate a manufacturing process of a thin film transistor.

Explanation of symbols

101 glass substrate 102 base film (silicon oxide film)
103 Amorphous silicon film 104 Nickel element held in contact with the surface 105 Crystalline silicon film 106 Mask made of silicon oxide film 107 Region doped with P (phosphorus) element 108 P (phosphorus) element was not doped Region 109 region doped with P (phosphorus) element 110 resist mask 111 pattern of silicon oxide film to be an active layer 11 silicon oxide film formed by CVD method 112 source region 113 channel region 114 drain region 115 silicon nitride film 116 Resin film 117 Source electrode 118 Drain electrode

Claims (9)

A metal element that promotes crystallization of silicon is selectively introduced into an amorphous silicon film formed over the substrate, and heat treatment is performed, so that the metal element is selectively introduced from the first region into the substrate. Crystal growth is performed in parallel directions to form a crystalline silicon film,
A portion of the crystalline silicon film is covered with a mask, and an impurity element is implanted into a second region of the crystalline silicon film that is not covered with the mask;
The metal element present in the crystalline silicon film covered with the mask by heat treatment is moved to the second region into which the impurity element is implanted,
Removing the mask,
Forming a resist mask having a smaller area than a part of the crystalline silicon film on the crystalline silicon film;
A method for manufacturing a semiconductor device, wherein the second region is removed by patterning the crystalline silicon film using the resist mask . In claim 1 ,
A method for manufacturing a semiconductor device, wherein heat treatment for moving the metal element to the second region is performed in an atmosphere containing oxygen. A metal element that promotes crystallization of silicon is selectively introduced into an amorphous silicon film formed over the substrate, and heat treatment is performed, so that the metal element is selectively introduced from the first region into the substrate. Crystal growth is performed in parallel directions to form a crystalline silicon film,
Forming a first mask made of a silicon oxide film on the crystalline silicon film using a first resist mask;
Impurity elements are implanted into the first resist mask and the second region not covered with the first mask of the crystalline silicon film,
Performing isotropic etching to recede the first resist mask isotropically to form a second resist mask;
Patterning the first mask using the second resist mask to form a second mask;
Removing the second resist mask;
Moving the metal element present in the crystalline silicon film covered with the first mask to the second region into which the impurity element is implanted;
A method for manufacturing a semiconductor device, wherein the crystalline silicon film is patterned using the second mask. A metal element that promotes crystallization of silicon is selectively introduced into an amorphous silicon film formed over the substrate, and heat treatment is performed, so that the metal element is selectively introduced from the first region into the substrate. Crystal growth is performed in parallel directions to form a crystalline silicon film,
Forming a mask made of a silicon oxide film on the crystalline silicon film using a resist mask;
Injecting an impurity element into the second region not covered with the resist mask and the mask made of the silicon oxide film of the crystalline silicon film,
Removing the resist mask;
Moving the metal element present in the crystalline silicon film covered with the mask made of the silicon oxide film to the second region into which the impurity element is implanted;
Patterning the crystalline silicon film using a mask made of the silicon oxide film;
Isotropic etching is performed to etch the side surfaces of the patterned crystalline silicon film,
A method for manufacturing a semiconductor device, wherein the mask made of the silicon oxide film is removed. A metal element that promotes crystallization of silicon is selectively introduced into an amorphous silicon film formed over the substrate, and heat treatment is performed, so that the metal element is selectively introduced from the first region into the substrate. Crystal growth is performed in parallel directions to form a crystalline silicon film,
Forming a first mask covering a part of the crystalline silicon film using a resist mask by a laminated film of a silicon oxide film and a silicon nitride film;
Injecting an impurity element into the second region of the crystalline silicon film that is not covered with the resist mask and the first mask,
Removing the resist mask;
Moving the metal element present in the crystalline silicon film covered with the first mask to the second region into which the impurity element is implanted;
Isotropic etching is performed on the silicon oxide film using the silicon nitride film as a mask to form a second mask made of the silicon oxide film,
Removing the silicon nitride film;
A method for manufacturing a semiconductor device, wherein the crystalline silicon film is patterned using the second mask. In any one of Claims 1 to 5 ,
The method for manufacturing a semiconductor device, wherein the concentration of the impurity element is higher by one digit or more than the concentration of the metal element in the second region of the crystalline silicon film into which the impurity element is implanted. In any one of Claims 1 thru | or 6,
A method for manufacturing a semiconductor device, wherein the second region is amorphized by implanting the impurity element into the second region. In any one of Claims 1 thru | or 7,
A method for manufacturing a semiconductor device, wherein the impurity element is phosphorus. In claim 8,
The method for manufacturing a semiconductor device, wherein the concentration of phosphorus implanted into the crystalline silicon film is 1 × 10 ²⁰ atoms cm ⁻³ or more.

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