JP2004260202A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the reliability of a semiconductor device by preventing impurities from creeping from a glass substrate and the like into an active layer in the semiconductor device. <P>SOLUTION: A crystalline silicon film used as the active layer, a first silicon oxide film, a second silicon oxide film, a third silicon oxide film overlying them, further a silicon nitride film overlying the third silicon oxide film, and the silicon nitride film are covered by a resin film in the semiconductor device. This constitution can prevent impurities from creeping into the active layer. Therefore, a highly reliable semiconductor device can be obtained. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The invention disclosed in this specification relates to a semiconductor device formed over a glass substrate. Further, the present invention relates to a manufacturing method thereof. Specific technical fields include a thin film transistor formed over a glass substrate and a method for manufacturing the thin film transistor.

  A technique for forming a thin film transistor (hereinafter, referred to as a TFT) on a glass substrate is known.

  This technology has been developed in the process of realizing an active matrix type liquid crystal display device.

  At present, a-Si TFTs using an amorphous silicon film are mainly used.

  However, the operation speed of the a-SiTFT is slow, and therefore, the a-SiTFT is not applicable except for forming an active matrix circuit.

  In recent years, a configuration has been proposed in which a peripheral driving circuit and other circuits other than the active matrix circuit are integrated on a single glass substrate. This configuration is called a system-on-panel.

  This configuration called a system-on-panel is a form required for a device on which a liquid crystal display device is mounted to be further reduced in size and weight in the future.

  In addition, it is useful to integrate circuits having various functions on one substrate in order to simplify a manufacturing process and operation check.

  When a TFT is manufactured on a glass substrate, there are problems of low characteristics and variations in characteristics.

  If the characteristics are low, the characteristics of the constituent circuits are also low. Also, if the variation in the characteristics is large, the variation in the characteristics of the constituent circuits and the low characteristics are problematic.

  Low characteristics are mainly related to the physical properties of the semiconductor film to be used. The characteristics of the TFT can be enhanced by using a silicon film having high crystallinity.

On the other hand, regarding variations in TFT characteristics,
(1) Due to process instability.
(2) Those resulting from electrical instability of the obtained thin film semiconductor.
Etc. are considered. However, at present, no fundamental solution has been found.

  The present inventors measured the film quality and impurities of a gate insulating film that greatly affects the characteristics of the TFT, and examined the relationship with the above-described variation in the characteristics of the TFT.

  FIG. 3 shows data on the presence of impurities at the interface between the gate insulating film and the gate electrode of the TFT formed on the Corning 1737 glass substrate.

  This data is a result measured by EDX (energy dispersive X-ray micro analysis).

  EDX has sensitivity with respect to elements whose abundance exists in the order of comma% or more. Therefore, the elements detected by EDX analysis indicate that their abundance ratios (element number ratios) are on the order of comma% or more.

  This sample uses a silicon oxide film formed by a plasma CVD method as a gate insulating film, and uses aluminum formed by a sputtering method as a gate electrode.

  Accordingly, peaks of silicon (Si), oxygen (O), and aluminum (Al) appear in FIG. However, a trace amount of barium (Ba) or calcium (Ca) also appears.

  The vertical axis of the measured values shown in FIG. 4 does not accurately reflect the abundance ratio of atoms. However, their relative abundance relationships are shown.

  In FIG. 4, the count number of barium or calcium is smaller than that of aluminum or silicon, but it can be said that the density is high when electric influence is considered. (At least a few percent of commas)

  Barium and calcium have a high ionization tendency. Therefore, the presence of such an element at a concentration of comma% or more at the interface between the gate insulating film and the gate electrode is a major factor that makes the operation of the TFT unstable.

  FIG. 5 shows the result of analyzing the Corning 1737 glass substrate used as the substrate by the same measurement method as shown in FIG.

  As is clear from FIG. 5, the glass substrate contains barium and calcium at a relatively high concentration.

  From this, it can be considered that barium and calcium shown in FIG. 4 have come from the glass substrate used.

  It is considered that the sneaking of the impurity from the glass substrate is caused by the substrate being sputtered at the time of forming the gate electrode, and the impurity scattered into the atmosphere at that time.

  In view of the above-described recognition, an object of the invention disclosed in this specification is to provide a structure for preventing impurities from flowing from a glass substrate (or another appropriate substrate) into a TFT.

  One of the inventions disclosed in this specification is a step of forming a blocking layer on the exposed outer peripheral surface of a glass substrate or a quartz substrate by a low-pressure thermal CVD method, and a step of covering the insulating film with an amorphous by a low-pressure thermal CVD method. A step of forming a silicide film, a step of forming an insulating film of the same film quality as the insulating film by the low pressure thermal CVD method over the silicide film, and an insulating film formed by covering the silicide film in the step. And a step of completing a thin film transistor using the gate insulating film as a gate insulating film.

  According to another aspect of the present invention, there is provided a process of forming an insulating film on the exposed upper surface, back surface and side surfaces of a glass substrate or a quartz substrate by a reduced pressure thermal CVD method, and forming an amorphous silicide by a reduced pressure thermal CVD method covering the insulating film. A step of forming a film, a step of forming an insulating film having the same film quality as the insulating film by the low-pressure thermal CVD method covering the silicide film, and a step of forming the insulating film formed by covering the silicide film in the step. And a step of completing a thin film transistor as a gate insulating film.

  As the glass substrate, a Corning 1737 glass substrate, a 7059 glass substrate, a neoceram N0 glass substrate, an N11 glass substrate, or the like can be used.

As the amorphous silicide film, an amorphous silicon film or a film represented by amorphous Si _x Ge _1-x (0 ≦ X ≦ 1) can be used.

  Examples of the blocking layer include a silicon oxide film, a silicon oxynitride film, and a silicon nitride film.

  As a method for forming the silicon oxide film, a low-pressure thermal CVD method using silane and oxygen or dichlorosilane and oxygen as source gases can be used.

As a method for forming the silicon nitride film and the silicon oxynitride film, a low-pressure CVD method using silane and N ₂ O or silane and NO ₂ as a source gas can be used. If a silicon nitride film is formed, a low pressure thermal CVD method using dichlorosilane and ammonia can be used.

  In particular, in a plasma CVD method using dichlorosilane and ammonia, a defect in a film to be formed is terminated by chlorine, which is effective in forming a film with few defects.

  Another structure of the invention is characterized in that a thin film transistor is formed on one surface of a glass substrate, and an insulating film constituting a gate insulating film of the thin film transistor is provided so as to surround the glass substrate.

  Another embodiment of the invention is characterized in that a thin film transistor is formed on one surface of a glass substrate, and an insulating film forming a gate insulating film of the thin film transistor is also formed on the back surface side of the glass substrate. I do.

  Another aspect of the invention is a semiconductor device using a thin film transistor on one surface of a glass substrate, wherein an insulating film forming a gate insulating film of the thin film transistor is also formed on the back surface side of the glass substrate. A semiconductor device characterized by the above-mentioned.

  In the structures of the above three inventions, an insulating film is formed on the lower surface of the active layer forming the thin film transistor, and the insulating film is also formed on the back surface of the glass substrate.

  According to another aspect of the present invention, there is provided a semiconductor device using a thin film transistor on one surface of a glass substrate, wherein an insulating film forming a gate insulating film of the thin film transistor and an insulating film formed on a base of an active layer of the thin film transistor are provided. The film has the same components as the film, and the insulating film is also formed on the back surface side of the glass substrate.

  According to another aspect of the present invention, there is provided a semiconductor device using a thin film transistor on one surface of a glass substrate, wherein an insulating film forming a gate insulating film of the thin film transistor and an insulating film formed on a base of an active layer of the thin film transistor are provided. The film has the same components as the film, and the insulating film formed on the base is formed so as to surround the glass substrate.

  In the above invention, it is effective to include a halogen element in the insulating film. For example, according to a method using dichlorosilane for forming an insulating film, chlorine can be contained in the film. At this time, the concentration of the halogen element is desirably within 5 atomic%.

  By utilizing the invention disclosed in this specification, it is possible to provide a structure for preventing impurities from entering a TFT from a glass substrate (or an appropriate substrate).

  Then, a TFT having high reliability can be manufactured. Further, a device (semiconductor device) using a TFT can have higher performance and higher reliability.

  As shown in FIG. 2C, the glass substrate is covered with a silicon oxide film 102. By doing so, diffusion of impurities from the glass substrate can be suppressed.

  In addition, the base film 102 of the active layer and the gate electrodes 115 and 116 are formed as insulating films having the same film quality.

  By doing so, it is possible to suppress an adverse effect on the operation due to the electrical state (difference in interface characteristics) between the upper surface and the lower surface of the active layer.

[Example 1]
1 to 3 show a manufacturing process of this embodiment. First, a Corning 1737 glass substrate 101 is prepared. (Fig. 1 (A))

  As the glass substrate, a Corning 7059 glass substrate, a quartz substrate, or another suitable glass substrate can be used.

  The structure shown in this embodiment is particularly useful when low-grade quartz glass having a high impurity content is used.

  Next, a silicon oxynitride film 102 is formed to a thickness of 200 nm on the exposed surface of the glass substrate 101 by a low-pressure thermal CVD method. (FIG. 1 (B))

Here, a silicon oxide film 102 (strictly containing nitrogen) is formed to a thickness of 300 nm using SiH ₄ and NO ₂ as source gases.

  The heating temperature at this time is 600 ° C. The heating temperature is preferably selected from the range of 600 ° C. ± 50 ° C.

When a quartz substrate is used as the substrate, a film can be formed at a heating temperature of about 850 ° C. using silane and N ₂ O as source gases. Alternatively, a silicon nitride film may be formed using dichlorosilane and ammonia.

  The silicon oxide film 102 is formed on the front surface, the back surface, and the side surface of the substrate. Note that, during film formation for holding the substrate, the edge portion of the substrate is not formed because it is in contact with the substrate holder.

  It is important that the area of the region where the film is not formed in contact with the substrate holder is within 5% of the total surface area.

Next, an amorphous silicon film 103 is formed to a thickness of 50 nm by a low pressure thermal CVD method using Si ₂ H ₆ as a source gas. (Fig. 1 (C))

  Next, heat treatment is performed to crystallize the amorphous silicon film 103. Thus, a crystalline silicon film is obtained.

  As means for crystallization, other than heat treatment, means such as irradiation with laser light, combined use of heating and irradiation with laser light, or irradiation with strong light can be used.

  Next, a resist mask (not shown) is arranged, and the previously obtained crystalline silicon film is patterned by a wet etching method.

  By performing this patterning, patterns indicated by 104 and 105 are obtained. (Fig. 1 (D))

  Next, as shown in FIG. 2A, a silicon oxide film 106 forming a gate insulating film is formed to a thickness of 50 nm by a low pressure thermal CVD method.

The formation of the silicon oxide film 106 is also performed by a low pressure thermal CVD method using SiH ₄ and NO ₂ as source gases.

  In the steps so far, a plasma process using high-frequency power has not been used. The exposed surface of the glass substrate is covered with the silicon oxide film 102. (Excluding the area in contact with the holder)

  By not using a plasma process, emission of impurities from the glass substrate due to accelerated ion collision can be suppressed. In addition, by covering the glass substrate with a silicon oxide film, emission of impurities from the glass substrate can be further suppressed.

  Therefore, it is possible to prevent impurities from the substrate from reaching the surfaces of the silicon film patterns 104 and 105 and the surface of the silicon oxide film 106.

  After the state shown in FIG. 2A is obtained, an aluminum film (not shown) is formed to a thickness of 400 nm by a sputtering method. By patterning this aluminum film using the resist masks 20 and 21, patterns 107 and 108 are obtained. (FIG. 2 (B))

  The patterns shown by 107 and 108 are the base patterns constituting the gate electrode of the TFT.

  After the state shown in FIG. 2B is obtained, anodic oxidation is performed with the resist masks 20 and 21 remaining. Here, porous anodic oxide films 109 and 112 are formed by an anodic oxidation method using an aqueous solution containing 3% oxalic acid as an electrolytic solution. Here, the growth distance is 400 nm.

  At this time, anodic oxidation selectively proceeds on the side surface of the aluminum pattern because the resist mask remains on the aluminum pattern.

  Next, the resist masks 20 and 21 are removed, and anodic oxidation is performed again. Here, anodization is performed using a solution obtained by neutralizing an ethylene glycol solution containing 3% tartaric acid with aqueous ammonia as an electrolyte. In this step, anodic oxide films 110 and 113 are formed because the electrolytic solution penetrates into the porous anodic oxide film.

  The anodic oxide films 110 and 113 have dense film quality. The thickness of the anodic oxide films 110 and 113 having the dense film quality is 70 nm.

  Thus, the state shown in FIG. 2C is obtained. Next, the silicon oxide film 106 exposed on the upper surface is removed by a dry etching method having vertical anisotropy.

Further, the porous anodic oxide films 109 and 112 are removed. Thus, the state shown in FIG. 2D is obtained.

  Thus, the state shown in FIG. 2D is obtained. In the state shown in FIG. 2D, the silicon oxide film forming the gate insulating film remains on the back side of the substrate as indicated by 117.

  Further, as shown by 115 and 116, the silicon oxide film forming the gate electrode remains.

  Next, doping of an impurity element for forming source and drain regions is performed by a plasma doping method. (FIG. 3 (A))

  Here, the regions of the two TFTs are alternately masked with a resist mask, and P (phosphorus) and B (boron) are respectively doped.

  By performing this doping, a source region 118 and a drain region 122 of a PTFT (P-channel thin film transistor) are formed in a self-aligned manner.

  On the other hand, a source region 127 and a drain region 123 of an NTFT (N-channel thin film transistor) are formed in a self-aligned manner. (FIG. 3 (A))

  At this time, the lightly doped regions 119, 121, 124, and 126 are formed in a self-aligned manner due to the existence of the remaining silicon oxide films 115 and 116. (FIG. 3 (A))

  The regions 119 and 121 are low-concentration impurity regions having a lower B (boron) doping concentration than the regions 118 and 122. (FIG. 3 (A))

  The regions 124 and 126 are low-concentration impurity regions having a lower P (phosphorus) doping concentration than the regions 123 and 127.

  After completion of the doping, laser light irradiation is performed to activate the doped region. This step may be performed by irradiation with strong light such as infrared light or ultraviolet light.

  After the state shown in FIG. 3A is obtained, a silicon oxide film 128 is formed to a thickness of 300 nm by a plasma CVD method. Further, a silicon nitride film 129 is formed to a thickness of 50 nm. Further, a polyimide resin film 130 is formed by a spin coating method. Thus, the state shown in FIG. 3B is obtained.

  Other than polyimide, polyamide, polyimide amide, acryl, epoxy and the like can be used.

  After the state shown in FIG. 3B is obtained, a contact hole is formed, and a source electrode 131 and a drain electrode 132 of the PTFT, and a source electrode 134 and a drain electrode 133 of the NTFT are formed.

  Thus, the state shown in FIG. 3C is obtained. Here, if the drain electrodes 132 and 133 are connected, a CMOS structure can be obtained.

  By adopting the manufacturing process as shown in this embodiment, it is possible to suppress impurities from flowing from the glass substrate between the gate insulating film and the gate electrode, and to reduce the variation in the characteristics of the obtained TFT. Can be.

  In addition, it is possible to prevent impurities from flowing from the glass substrate between the active layer and the gate insulating film.

  By doing so, the reliability of the obtained device can be increased.

  In this embodiment, the case where aluminum is used as a material forming the gate electrode has been described. However, as a material for forming the gate electrode, various silicides, silicon having a conductivity type, and various metal materials can be used.

[Example 2]
In this embodiment, in the manufacturing process shown in Embodiment 1, the silicon oxide film 103 (see FIG. 1C) functioning as a gate insulating film is formed by a plasma CVD method instead of a low pressure thermal CVD method. This is an example of the case.

  FIG. 6 shows a manufacturing process. First, according to the manufacturing process described in Embodiment 1, as shown in FIG. 6A, a silicon oxide film is formed on the surface (upper surface, lower surface, and side surface) of the glass substrate 101 by a low-pressure thermal CVD method. Then, patterns 104 and 105 made of a crystalline silicon film are formed.

  In this state, a silicon oxide film 601 functioning as a gate insulating film is formed to a thickness of 20 to 150 nm (for example, 100 nm) by a plasma CVD method. (FIG. 6 (A))

  Here, in the case where the silicon oxide film 601 is formed by the plasma CVD method, there is a concern that impurities may flow from the glass substrate due to plasma damage as compared with the case of the first embodiment.

  However, also in the case of this embodiment, since the glass substrate is covered so as to be wrapped by the silicon oxide film 102, it is possible to greatly suppress the sneaking of impurities from the substrate in practical use.

  After the state shown in FIG. 6A is obtained, the aluminum film is patterned using the resist masks 20 and 21 to obtain aluminum patterns 107 and 108. (FIG. 6 (B))

  Next, with the resist masks 20 and 21 remaining, porous anodic oxide films 109 and 112 are formed by anodic oxidation. Then, the resist masks 20 and 21 are removed, and anodic oxide films 110 and 113 having denser film quality are formed. (FIG. 6 (C))

  Next, the exposed silicon oxide film 601 is removed, and the porous anodic oxide films 109 and 112 are further removed. Thus, the state shown in FIG. 6D is obtained.

  Thereafter, PTFTs (P-channel thin film transistors) and NTFTs (N-channel thin film transistors) are manufactured according to the same steps as those shown in FIGS.

[Example 3]
This embodiment shows an example in which an inverted staggered TFT is manufactured using the invention disclosed in this specification.

  FIG. 7 shows a manufacturing process of this embodiment. First, as shown in FIG. 7A, a silicon oxide film 702 is formed over the entire exposed surface of a glass substrate 701 by a low-pressure CVD method.

  Next, a gate electrode 703 made of a silicide material is formed. Here, the gate electrode 703 is formed using tungsten silicide formed by a sputtering method. Thus, the state shown in FIG. 7A is obtained.

  When the gate electrode is formed, a sputtering method is used. However, since the substrate is covered with the silicon oxide film, diffusion of impurities due to the substrate being sputtered can be suppressed.

  Next, a silicon oxide film 704 functioning as a gate electrode is formed by a low-pressure thermal CVD method. (FIG. 7 (B))

  Further, an amorphous silicon film 705 is formed by a low pressure thermal CVD method by a low pressure thermal CVD method, and is crystallized by a heat treatment. (FIG. 7 (B))

  After obtaining the state shown in FIG. 7B, patterning is performed on the silicon film to obtain a pattern indicated by 706 in FIG. 7C. This pattern becomes an active layer of the TFT.

  Next, a silicon nitride film is formed by a plasma CVD method, and is patterned to form a mask pattern 707. (FIG. 7 (C))

  Next, a source region 708, a drain region 710, and a channel region 709 are formed in a self-aligned manner by doping phosphorus ions by a plasma doping method. (FIG. 7 (D))

  When the doping is completed, laser light irradiation is performed to activate the doped phosphorus and anneal the crystal structure damaged at the time of the doping.

  Next, a source electrode 711 and a drain electrode 712 are formed using a stacked film of a titanium film, an aluminum film, and a titanium film. (FIG. 7E)

  Thus, a bottom gate type TFT is completed.

The key point in the above manufacturing process is
(1) With a structure in which the glass substrate 701 is covered with the base film 702, emission of impurities from the glass substrate 701 is suppressed in a later step.
(2) Each of a base film 702, a silicon oxide film 704 functioning as a gate insulating film, and an amorphous silicon film 705 serving as a starting film to form an active layer is formed by a low pressure thermal CVD method. Reduce plasma damage at times.
On the point.

  With such a configuration, it is possible to prevent impurities in the glass substrate from entering the active region of the TFT and adversely affecting the operation of the TFT.

  Here, the active region refers to a region that is sensitive to the operation of the TFT when viewed electrically, such as the surface of the active layer, in the gate insulating film, and the interface between the gate electrode and the gate insulating film.

[Example 4]
This embodiment relates to a method for growing a crystal. FIG. 8 shows an outline of a manufacturing process shown in this embodiment.

  First, a glass substrate 101 is prepared. (FIG. 8A)

Then, a silicon oxide film 102 having a thickness of 300 nm is formed on the exposed surface of the glass substrate 101 by a low pressure thermal CVD method. Here, a mixed gas of SiH ₄ and N ₂ O is used as a source gas. (FIG. 8 (B))

Next, an amorphous silicon film 103 is formed to a thickness of 50 nm by a low pressure thermal CVD method using Si ₂ H ₆ as a source gas. (FIG. 8 (C))

  Next, a mask 801 is formed by forming a silicon oxide film to a thickness of 100 nm and forming an opening 803 in the silicon oxide film. (FIG. 8 (D))

  The opening 803 has a slit shape having a longitudinal shape from the front of the drawing to the depth direction. (FIG. 8 (D))

  In this state, a nickel acetate solution containing 10 ppm of a nickel element is applied, and an excess solution is removed using a spin coater.

  In this way, as shown at 804, a state is obtained in which nickel is held in contact with the surface. In this state, the nickel element is held in contact with the surface of the amorphous silicon film 103 in the region of the opening 803. (FIG. 8 (D))

  Next, heat treatment at 560 ° C. for 18 hours is performed in a nitrogen atmosphere. In this step, crystal growth proceeds in a direction parallel to the substrate (a direction parallel to the film surface) as indicated by 805 from the region of the opening 803. This form of crystal growth is called lateral growth. (FIG. 9A)

  This crystal growth can be performed over several tens of μm. Thus, a silicon film 806 that has been laterally grown is obtained.

  Next, the mask 801 made of a silicon oxide film is removed. Then, a resist mask (not shown) is arranged, and the silicon film is patterned.

  Thus, the silicon film patterns 807 and 808 are obtained. (FIG. 9 (B))

    Thereafter, NTFT and PTFT are manufactured in accordance with the manufacturing process shown in FIG.

  In this embodiment, an example in which nickel is used has been described. In addition, one or more elements selected from Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au can be used.

[Example 5]
FIG. 10 shows a manufacturing process of this embodiment. First, a glass substrate 101 is prepared. (FIG. 10A)

  Next, a silicon oxide film 102 is formed by a low pressure thermal CVD method. (FIG. 10 (B))

  Next, an amorphous silicon film 103 is formed by a low pressure thermal CVD method. Then, a nickel acetate solution is applied to obtain a state in which the nickel element is held in contact with the surface of the amorphous silicon film as shown by 1001. (FIG. 10 (C))

  Next, the amorphous silicon film 103 is crystallized by performing a heat treatment at 600 ° C. for 8 hours to obtain a crystalline silicon film 1002. (FIG. 10 (D))

  Thereafter, the crystalline silicon film 1002 is patterned to form an active layer of the TFT.

[Example 6]
This embodiment basically relates to a manufacturing process in which the manufacturing process shown in Embodiment 4 is improved to obtain a crystalline silicon film having higher crystallinity.

  The manufacturing process of this embodiment will be described with reference to FIGS. First, a quartz substrate 101 is prepared. (FIG. 8A)

  In this embodiment, a low-grade quartz substrate can be used. That is, a quartz substrate having a relatively high impurity concentration can be used. This is because a manufacturing process that suppresses contamination of impurities from the substrate is employed.

  After the quartz substrate 101 is prepared, as shown in FIG. 8B, a silicon oxide film 102 is formed as a base film to a thickness of 300 nm by a low pressure thermal CVD method.

  Next, as shown in FIG. 8C, an amorphous silicon film 103 is formed to a thickness of 50 nm by a low pressure thermal CVD method.

  Next, a mask 801 made of a silicon oxide film is formed. An opening 803 is provided in this mask.

  Next, a nickel acetate solution adjusted to a nickel concentration of 100 ppm by weight is applied, and an excess solution is removed by spin coating. Thus, a state is obtained in which the nickel element is held in contact with the surface of the sample as indicated by reference numeral 804.

  Next, heat treatment at 560 ° C. for 18 hours is performed in a nitrogen atmosphere. In this step, crystal growth proceeds in a direction parallel to the substrate (a direction parallel to the film surface) as indicated by 805 from the region of the opening 803. This form of crystal growth is called lateral growth. (FIG. 9A)

  Next, the mask 801 made of a silicon oxide film is removed. Then, a heat treatment is performed at 950 ° C. for 30 minutes in an oxygen atmosphere at normal pressure containing 3% by volume of HCl to form a thermal oxide film with a thickness of 30 nm.

  In this step, the nickel element in the silicon film is vaporized as nickel chloride and removed therefrom.

  Further, with the formation of the thermal oxide film, the thickness of the silicon film is reduced from 50 nm to 35 nm.

  This step of forming a thermal oxide film has a tremendous effect on removing nickel elements and improving crystallinity.

  After the thermal oxide film is formed, the thermal oxide film is removed, and a TFT is manufactured using the obtained silicon film.

  In the manufacturing process described in this embodiment, a temperature of 950 ° C. (at least 900 ° C. is required) is required in the process of forming a thermal oxide film, so that a quartz substrate must be used as a substrate. However, a TFT having high characteristics can be obtained.

  For example, in the TFT obtained according to the manufacturing process shown in Embodiment 4, the level is such that oscillation of about 50 MHz can be performed by the oscillation of the ring oscillator, but in the TFT obtained by using the process shown in this embodiment, Oscillation of 10 times or more can be performed.

[Description of reduced pressure thermal CVD apparatus]
Here, an outline of a low-pressure thermal CVD apparatus used when carrying out the invention disclosed in this specification is shown.

  FIG. 11 shows a schematic side view. The configuration shown here includes two decompression chambers 1208 and 1209 made of quartz.

  1210 and 1211 are heating furnaces for heating the decompression chamber, respectively.

  Reference numeral 1201 denotes a substrate loading chamber. Reference numeral 1202 denotes a chamber for loading a substrate into the decompression chamber 1209 and unloading the substrate processed in the decompression chamber 1209.

  Reference numeral 1203 denotes a chamber for carrying a substrate into the decompression chamber 1208 and further carrying out a substrate processed in the decompression chamber 1208.

  Reference numeral 1204 denotes a chamber for carrying out the substrate.

  Reference numerals 1201, 1202, 1203, and 1204 denote airtight chambers, each having a structure isolated from an external atmosphere. Here, each chamber has a structure filled with an inert gas (nitrogen gas). In order to improve the airtightness, a configuration capable of realizing a reduced-pressure atmosphere may be adopted.

  This apparatus has a function of forming a silicon oxide film in one chamber and forming an amorphous silicon film in the other chamber.

  Further, gas supply systems 1212 and 1213 are arranged. Further, exhaust systems 1214 and 1215 are provided.

  Reference numeral 1207 denotes a cassette in which the substrates are stored, and the transfer and film formation of the substrates are performed in a state where the substrates are stored in the cassette.

[Example 7]
In this embodiment, a silicon oxynitride film is used instead of the silicon oxide film by the low pressure thermal CVD method used in the other embodiments.

In order to form a silicon oxynitride film by a low-pressure thermal CVD method, SiH ₄ , N ₂ O, and NH ₄ may be used as source gases.

Example 8
In this embodiment, examples of various semiconductor devices using a TFT obtained by using the present invention will be described.

  Example 1 In this example, an outline of an apparatus configured using a TFT manufactured using the invention disclosed in this specification will be described. FIG. 12 shows an outline of each device.

  FIG. 12A illustrates a portable information processing terminal, which has a communication function using a telephone line.

  This electronic device includes an integrated circuit 2006 using a TFT inside a main body 2001. An active matrix type liquid crystal display 2005 in which TFTs are arranged as switching elements, a camera unit 2002 for capturing an image, and an operation switch 2004 are provided.

  Portable information terminals as shown in FIG. 12A tend to be smaller and thinner in the future. In the case of smaller and thinner devices, a configuration in which various circuits for performing information processing, an oscillation circuit, and the like in addition to an active matrix circuit for display are integrated on one substrate (referred to as a system-on-panel) is required. It is said.

  For such a configuration, it is useful to manufacture a TFT using the invention disclosed in this specification.

  FIG. 12B illustrates an electronic device called a head-mounted display. This device has a function of attaching the main body 21201 to the head with a band 2103 and displaying an image in front of the eyes in a pseudo manner. The image is created by the active matrix type liquid crystal display device 2102 corresponding to the left and right eyes.

  In the active matrix section, TFTs are arranged as switching elements.

  FIG. 12C has a function of displaying map information and various types of information based on signals from artificial satellites. Information from a satellite captured by the antenna 2204 is processed by an electronic circuit provided in the main body 2201, and necessary information is displayed on an active matrix liquid crystal display device 2202.

  The operation of the device is performed by an operation switch 2203. In such an apparatus, a circuit using a TFT is used.

  FIG. 12D illustrates a mobile phone. This electronic device includes an antenna 2306, a sound output unit 2302, a liquid crystal display device 2304, operation switches 2305, and a sound input unit 2303 in a main body 2301.

  The electronic device illustrated in FIG. 12E is a portable imaging device called a video camera. This electronic device includes a liquid crystal display 2402 attached to an opening / closing member on a main body 2401, and an operation switch 2404 attached to the opening / closing member.

  Further, the main body 2401 is provided with an image receiving section 2406, an integrated circuit 2407, an audio input section 2403, operation switches 2404, and a battery 2405.

  The electronic device illustrated in FIG. 12F is a projection-type liquid crystal display device. This device includes a light source 2502, a liquid crystal display device 2503, and an optical system 2504 in a main body 2501, and has a function of projecting an image on a screen 2505.

  Further, as the liquid crystal display device in the electronic device described above, either a transmission type or a reflection type can be used. The transmission type is advantageous in terms of display characteristics, and the reflection type is advantageous in pursuit of low power consumption and reduction in size and weight.

  Further, a flat panel display such as an active matrix EL display or a plasma display can be used as the display device.

[Example 9]
The present embodiment relates to a manufacturing process in which a nickel element can be used to obtain a crystalline silicon film and a nickel element can be removed even when a glass substrate is used.

  FIG. 13 shows a manufacturing process.

  First, the state shown in FIG. 13A is obtained according to the manufacturing steps shown in FIGS. Here, a glass substrate is used as the substrate.

  FIG. 13A shows a state in which crystal growth as indicated by 805 proceeds from the region of the opening 803 formed in the mask 801.

  After the lateral growth is completed, the mask 801 made of a silicon oxide film is removed, and masks 1401 and 1402 made of a silicon oxide film are provided.

  Then, phosphorus ions are implanted at an accelerated rate by a plasma doping apparatus. In this step, as shown in FIG. 13B, the regions 1403, 1404, and 1405 are doped with phosphorus. These regions have a state in which the crystal structure is destroyed and defects are formed at a high density.

  After the state shown in FIG. 13B is obtained, heat treatment is performed at 600 ° C. for 2 hours in a nitrogen atmosphere.

  In this step, nickel moves from the areas 1406 and 1407 to the areas 1403, 1404, and 1405 as shown in FIG. That is, nickel existing in the regions 1406 and 1407 is gettered in the regions 1403, 1404, and 1405.

  Then, the regions 1403, 1404, and 1405 are removed. Utilizing the remaining silicon film, patterns 807 and 808 are formed.

  Thus, an active layer from which the nickel element has been removed is obtained.

  In the manufacturing process described in this embodiment, a high temperature such as 900 ° C. or higher is not required for removing nickel. For this purpose, a glass substrate can be used.

4A to 4C illustrate a manufacturing process of a TFT. 4A to 4C illustrate a manufacturing process of a TFT. 4A to 4C illustrate a manufacturing process of a TFT. FIG. 4 is a diagram showing the proportion of impurities in a TFT. FIG. 4 is a diagram showing the proportion of impurities in a glass substrate. 4A to 4C illustrate a manufacturing process of a TFT. 4A to 4C illustrate a manufacturing process of a TFT. 4A to 4C illustrate a manufacturing process of a TFT. 4A to 4C illustrate a manufacturing process of a TFT. 4A to 4C illustrate a manufacturing process of a TFT. The figure which shows the outline of a low pressure thermal CVD apparatus. FIG. 2 is a diagram showing an outline of a device using a TFT. 4A to 4C illustrate a manufacturing process of a TFT.

Explanation of reference numerals

101 glass substrate or quartz substrate 102 silicon oxide film (low pressure thermal CVD film)
103 amorphous silicon film (low pressure thermal CVD film)
104 Active layer of TFT 105 Active layer of TFT 106 Silicon oxide film 107, 108 Pattern 21 and 22 made of aluminum resist mask 109 Porous anodic oxide film 110 Anodized film 111 having dense film quality 111 Silicon oxide film (gate) electrode)
112 Porous anodic oxide film 113 Dense anodic oxide film 114 Gate electrode 115, 116 Silicon oxide film remaining (gate electrode)
117 Remaining silicon oxide film (gate electrode)
118 Source region 119 Low concentration impurity region 120 Channel region 121 Low concentration impurity region 122 Drain region 123 Drain region 124 Low concentration impurity region 125 Channel region 126 Low concentration impurity region 127 Source region 128 Silicon oxide film 129 Silicon nitride film 130 Polyimide resin film 131 source electrode 132 drain electrode 133 drain electrode 134 source electrode

Claims (7)

A crystalline silicon film on the first silicon oxide film;
A second silicon oxide film on the crystalline silicon film;
An electrode formed on the crystalline silicon film via the second silicon oxide film;
A third silicon oxide film covering the crystalline silicon film, the electrode, and the second silicon oxide film;
A silicon nitride film covering the third silicon oxide film;
A resin film covering the silicon nitride film;
Has,
The third silicon oxide film is in contact with the first silicon oxide film, the crystalline silicon film, the second silicon oxide film, and the electrode;
A semiconductor device, wherein the resin film includes polyimide, polyamide, polyimide amide, acrylic, or epoxy. In claim 1,
A semiconductor device, wherein each of the first and second oxide films contains a halogen element within 5 atomic%. In claim 2,
The semiconductor device, wherein the halogen is chlorine. In any one of claims 1 to 3,
The semiconductor device, wherein the crystalline semiconductor film contains a metal element that promotes crystallization. In any one of claims 1 to 4,
The crystalline silicon film is an active layer,
The second silicon oxide film is a gate insulating film;
The semiconductor device, wherein the electrode is a gate electrode. In any one of claims 1 to 5,
A semiconductor device, wherein an electrode reaching a source region or a drain region of the crystalline silicon film is formed on the resin film. In any one of claims 1 to 6,
A semiconductor device characterized in that barium (Ba) and calcium (Ca) do not exist in the second oxide film by more than a few percent of barium (Ba) and calcium (Ca) as detected by energy dispersive X-ray microanalysis (EDX). .

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