JPH10261803A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent impurities from creeping from a glass substrate or the like into a TFT by a method wherein a blocking layer is formed on the exposed outer peripheral surface of the glass substrate or the like by a reduced pressure thermal CVD method, an insulating film on the blocking layer is covered with an amorphous silicide film by the same CVD method as the above reduced pressure thermal CVD method and the silicide film is covered with an insulating film of the same film quality as that of the silicide film by the same CVD method as the above CVD method. SOLUTION: A silicon oxynitride film 102 is formed on the exposed surface of a glass substrate or a quartz substrate 101 utilizing SiH4 and NO2 by a reduced pressure thermal CVD method. This film 102 is formed on the surface, back and side surfaces of the substrate 101. Then, an amorphous silicon film is formed on the film 102 by the reduced pressure thermal CVD method, a heating treatment is performed on the amorphous silicon film and the amorphous silicon film is crystallized. Then, a resist mask is arranged and this crystalline silicon film is patterned by a wet etching method to obtain patterns 104 and 105. Then, a silicon oxide film constituting a gate insulating film is formed utilizing SiH4 and NO2 as raw gas by the reduced pressure thermal CVD method.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a semiconductor device formed on a glass substrate. Further, the present invention relates to a manufacturing method thereof. Specific technical fields include a thin film transistor formed over a glass substrate and a method for manufacturing the thin film transistor.

[0002]

2. Description of the Related Art A technique for forming a thin film transistor (hereinafter, referred to as a TFT) on a glass substrate is known.

[0003] This technology has been developed in the process of realizing an active matrix type liquid crystal display device.

At present, an a-Si TFT using an amorphous silicon film is mainly used.

[0005] However, the operation speed of the a-Si TFT is slow and cannot be applied except for forming an active matrix circuit.

In recent years, a configuration has been proposed in which peripheral driving circuits and other circuits other than the active matrix circuit are integrated on a single glass substrate. This configuration is called a system-on-panel.

The configuration called a system-on-panel is a form required for a device on which a liquid crystal display device is mounted to be further reduced in size and weight in the future.

[0008] Integrating circuits having various functions on one substrate is also useful for simplifying a manufacturing process and operation check.

[0009]

SUMMARY OF THE INVENTION TFT on a glass substrate
In the case where is manufactured, there is a problem that the characteristics are low and the characteristics vary.

If the characteristics are low, the characteristics of the constituent circuits are low. Further, if the variation in the characteristics is large, the variation in the characteristics of the constituent circuits and the low characteristics are problematic.

The low properties are mainly related to the physical properties of the semiconductor film to be used. The characteristics of the TFT can be improved by using a silicon film having high crystallinity.

On the other hand, variations in TFT characteristics are caused by (1) process instability. (2) Those resulting from electrical instability of the obtained thin film semiconductor. Etc. are considered. However, at present, no fundamental solution has been found.

The present inventors measured the film quality and impurities of the gate insulating film which greatly affects the characteristics of the TFT, and examined the relationship with the above-mentioned variation in the characteristics of the TFT.

FIG. 3 shows data on the presence of impurities at the interface between the gate insulating film and the gate electrode of the TFT formed on the Corning 1737 glass substrate.

This data is a result measured by EDX (energy dispersive X-ray microanalysis).

EDX has sensitivity with respect to elements whose abundance is in the order of comma% or more. Therefore, the elements detected by EDX analysis indicate that the abundance ratio (element number ratio) is on the order of the comma% or more.

In this sample, a silicon oxide film formed by a plasma CVD method is used as a gate insulating film, and aluminum formed by a sputtering method is used as a gate electrode.

Accordingly, peaks of silicon (Si), oxygen (O), and aluminum (Al) appear in FIG.
However, trace amounts of barium (Ba) and calcium (Ca)
Peak also appears.

The vertical axis of the measured values shown in FIG. 4 does not accurately reflect the abundance ratio of atoms. However, their relative density relationships are shown.

In FIG. 4, the count number of barium or calcium is smaller than that of aluminum or silicon, but it can be said that the density is high in consideration of electric influence. (At least a few percent of comma)

Barium and calcium have a high ionization tendency. Therefore, the presence of such an element at a concentration of comma% or more at the interface between the gate insulating film and the gate electrode is a major factor that makes the operation of the TFT unstable.

FIG. 5 shows the result of analyzing the Corning 1737 glass substrate used as the substrate by the same measuring method as shown in FIG.

As is clear from FIG. 5, the glass substrate contains barium and calcium at a relatively high concentration.

From this, it can be considered that barium and calcium shown in FIG. 4 come from the glass substrate used.

The impurities from the glass substrate are scattered around the substrate when the gate electrode is formed.
At this time, it is considered that the impurities are generated by scattering into the atmosphere.

The present invention disclosed in the present specification has been made in view of the above-mentioned circumstances, and has been made in view of the above-mentioned circumstances.
It is an object of the present invention to provide a configuration for preventing impurities from flowing into a TFT.

[0027]

Means for Solving the Problems One of the inventions disclosed in this specification is a step of forming a blocking layer on the exposed outer peripheral surface of a glass substrate or a quartz substrate by a reduced pressure thermal CVD method, and covering the insulating film. Forming an amorphous silicide film by a low pressure thermal CVD method, forming an insulating film of the same film quality as the insulating film by the low pressure thermal CVD method covering the silicide film, Forming a thin film transistor using an insulating film formed over the gate electrode as a gate insulating film.

According to another aspect of the present invention, there is provided a process of forming an insulating film on the exposed upper surface, the back surface, and the side surface of the glass substrate or the quartz substrate by a low pressure thermal CVD method, and a method of covering the insulating film by a low pressure thermal CVD method. A step of forming a crystalline silicide film, a step of forming an insulating film having the same film quality as the insulating film by covering the silicide film by a low pressure thermal CVD method, and forming a film by covering the silicide film in the step. Completing a thin film transistor using the insulating film as a gate insulating film.

As a glass substrate, Corning 1737 is used.
Glass substrate, 7059 glass substrate, Neoceram N0
A glass substrate, an N11 glass substrate, or the like can be used.

As the amorphous silicide film, an amorphous silicon film or a film represented by amorphous Si _x Ge _1-x (0 ≦ X ≦ 1) can be used.

Examples of the blocking layer include a silicon oxide film, a silicon oxynitride film, and a silicon nitride film.

As a method for forming the silicon oxide film, a low pressure thermal CVD method using silane and oxygen or dichlorosilane and oxygen as source gases can be used.

As a method for forming the silicon nitride film and the silicon oxynitride film, a low pressure CVD method using silane and N ₂ O or silane and NO ₂ as a source gas can be used. If a silicon nitride film is formed, a low pressure thermal CVD method using dichlorosilane and ammonia can be used.

In particular, in a plasma CVD method using dichlorosilane and ammonia, the defects in the film to be formed are terminated by chlorine, which is effective in forming a film with few defects.

According to another aspect of the invention, a thin film transistor is formed on one surface of a glass substrate, and an insulating film constituting a gate insulating film of the thin film transistor is provided so as to surround the glass substrate. I do.

According to another aspect of the present invention, a thin film transistor is formed on one surface of a glass substrate, and an insulating film constituting a gate insulating film of the thin film transistor is also formed on the back surface side of the glass substrate. It is characterized by.

Another aspect of the present invention is a semiconductor device using a thin film transistor on one surface of a glass substrate, wherein an insulating film forming a gate insulating film of the thin film transistor is also formed on the back surface side of the glass substrate. A semiconductor device characterized in that:

In the above three inventions, an insulating film is formed on the lower surface of the active layer constituting the thin film transistor, and the insulating film is also formed on the back surface of the glass substrate. And

According to another aspect of the invention, there is provided a semiconductor device using a thin film transistor on one surface of a glass substrate, wherein the semiconductor film is formed on an insulating film forming a gate insulating film of the thin film transistor and a base of an active layer of the thin film transistor. The insulating film has the same components as the insulating film, and the insulating film is also formed on the back surface side of the glass substrate.

According to another aspect of the invention, there is provided a semiconductor device using a thin film transistor on one surface of a glass substrate, the film being formed on an insulating film forming a gate insulating film of the thin film transistor and an underlayer of an active layer of the thin film transistor. The insulating film has the same components as the insulating film, and the insulating film formed on the base is formed so as to surround the glass substrate.

In the above invention, it is effective to include a halogen element in the insulating film. For example, according to a method using dichlorosilane for forming an insulating film, chlorine can be contained in the film. At this time, the concentration of the halogen element is desirably within 5 atomic%.

[0042]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 2C, a structure in which a glass substrate is covered with a silicon oxide film 102 is employed. By doing so, diffusion of impurities from the glass substrate can be suppressed.

The underlying film 102 of the active layer and the gate electrodes 115 and 116 are made of insulating films having the same film quality.

By doing so, it is possible to suppress an adverse effect on the operation caused by the electrical state (difference in interface characteristics) between the upper surface and the lower surface of the active layer.

[0045]

【Example】

[Embodiment 1] FIGS. 1 to 3 show the manufacturing steps of this embodiment. First, Corning 1737 glass substrate 101
Prepare (Fig. 1 (A))

As a glass substrate, Corning 7059
A glass substrate, a quartz substrate, or another suitable glass substrate can be used.

The structure shown in this embodiment is particularly useful when quartz glass is used for low grades having a high impurity content.

Next, the glass substrate 1 was formed by low pressure thermal CVD.
01 on the exposed surface of silicon oxynitride film 102
To a thickness of (FIG. 1 (B))

Here, SiH ₄ and NO were used as the source gases.
_The silicon oxide film 102 (strictly containing nitrogen) is formed to have a thickness of 300 nm by utilizing Step ₂ .

The heating temperature at this time is 600 ° C. This heating temperature is preferably selected from the range of 600 ° C. ± 50 ° C.

When a quartz substrate is used as a substrate, silane and N ₂ O are used as raw material gases to form a substrate.
Film formation can be performed at a heating temperature of about 0 ° C. Also,
A silicon nitride film may be formed using dichlorosilane and ammonia.

The silicon oxide film 102 is formed on the front surface, the back surface, and the side surface of the substrate. Note that, during film formation for holding the substrate, the edge portion of the substrate is not formed because it is in contact with the substrate holder.

It is important that the area of the region where the film is not formed in contact with the substrate holder is within 5% of the entire surface area.

Next, the amorphous silicon film 103 is formed to a thickness of 50 nm by a low pressure thermal CVD method using Si ₂ H ₆ as a source gas.
To a thickness of (Fig. 1 (C))

Next, a heat treatment is performed to form the amorphous silicon film 103.
Is crystallized. Thus, a crystalline silicon film is obtained.

As means for crystallization, means other than heat treatment such as irradiation with laser light, combined use of heating and irradiation with laser light, or irradiation with intense light can be used.

Next, a resist mask (not shown) is disposed,
The crystalline silicon film obtained earlier is patterned by a wet etching method.

By performing this patterning, 10
The pattern indicated by 4, 105 is obtained. (Fig. 1 (D))

Next, as shown in FIG. 2A, the silicon oxide film 106 constituting the gate insulating film is
A film is formed to a thickness of 0 nm.

The silicon oxide film 106 is also formed by a low pressure thermal CVD method using SiH ₄ and NO ₂ as source gases.

In the steps so far, a plasma process using high frequency power has not been used. The exposed surface of the glass substrate is covered with the silicon oxide film 102. (Excluding the area in contact with the holder)

By not using the plasma process, the emission of impurities from the glass substrate due to the collision of accelerated ions can be suppressed. In addition to that,
By covering the glass substrate with a silicon oxide film, emission of impurities from the glass substrate can be further suppressed.

Therefore, it is possible to prevent impurities from the substrate from reaching the surfaces of the silicon film patterns 104 and 105 and the surface of the silicon oxide film 106.

After obtaining the state shown in FIG. 2A, an aluminum film (not shown) is formed to a thickness of 400 nm by a sputtering method. Then, the aluminum film is patterned by using the resist masks 20 and 21 to obtain 10
The patterns shown at 7 and 108 are obtained. (FIG. 2 (B))

The pattern shown by 107 and 108 is T
It becomes the pattern of the base constituting the gate electrode of the FT.

After the state shown in FIG. 2B is obtained, anodic oxidation is performed with the resist masks 20 and 21 remaining. Here, porous anodic oxide films 109 and 112 are formed by an anodic oxidation method using an aqueous solution containing 3% oxalic acid as an electrolytic solution. Here, the growth distance is 400 nm.

At this time, since the resist mask remains on the aluminum pattern, anodic oxidation selectively proceeds on the side surface of the aluminum pattern.

Next, the resist masks 20 and 21 are removed, and anodic oxidation is performed again. Here, anodization is performed using a solution obtained by neutralizing an ethylene glycol solution containing 3% tartaric acid with aqueous ammonia as an electrolyte. In this step, anodic oxide films 110 and 113 are formed because the electrolytic solution penetrates into the porous anodic oxide film.

The anodic oxide films 110 and 113 have a dense film quality. Note that the thickness of the anodic oxide films 110 and 113 having the dense film quality is 70 nm.

Thus, the state shown in FIG. 2C is obtained. Next, the silicon oxide film 106 exposed on the upper surface is removed by a dry etching method having vertical anisotropy.

Further, the porous anodic oxide films 109 and 11
2 is removed. Thus, the state shown in FIG. 2D is obtained.

Thus, the state shown in FIG. 2D is obtained. In the state shown in FIG. 2D, the silicon oxide film forming the gate insulating film remains on the back side of the substrate as indicated by 117.

Further, as shown by 115 and 116, the silicon oxide film forming the gate electrode remains.

Next, doping of an impurity element for forming source and drain regions is performed by a plasma doping method. (FIG. 3 (A))

Here, two TFT regions are alternately masked with a resist mask, and P (phosphorus) and B
(Boron) doping.

By performing this doping, PT
A source region 118 and a drain region 122 of an FT (P-channel thin film transistor) are formed in a self-aligned manner.

On the other hand, the source region 127 and the drain region 123 of the NTFT (N-channel thin film transistor) are formed in a self-aligned manner. (FIG. 3 (A))

At this time, the remaining silicon oxide films 115 and 11
Due to the presence of 6, light-doped region 1
19, 121, 124 and 126 are formed in a self-aligned manner. (FIG. 3 (A))

The regions 119 and 121 are 118 and 122
A low-concentration impurity region having a lower doping concentration of B (boron) than the region indicated by. (FIG. 3 (A))

The areas 124 and 126 are 123,
This is a low-concentration impurity region having a lower doping concentration of P (phosphorus) than the region indicated by 127.

After completion of the doping, laser light irradiation is performed to activate the doped region. This step may be performed by irradiation with strong light such as infrared light or ultraviolet light.

After obtaining the state shown in FIG. 3A, a silicon oxide film 128 is formed to a thickness of 300 nm by a plasma CVD method. Further, a silicon nitride film 129 is formed to a thickness of 50 nm. Further, a polyimide resin film 130 is formed by a spin coating method. Thus, the state shown in FIG. 3B is obtained.

Other than polyimide, polyamide, polyimide amide, acryl, epoxy and the like can be used.

When the state shown in FIG. 3B is obtained, a contact hole is formed, and the source electrode 1 of the PTFT is formed.
31, drain electrode 132, source electrode 13 of NTFT
4. The drain electrode 133 is formed.

Thus, the state shown in FIG. 3C is obtained. Here, if the drain electrodes 132 and 133 are connected, C
A MOS structure is obtained.

By employing the manufacturing process as shown in this embodiment, it is possible to prevent impurities from flowing from the glass substrate between the gate insulating film and the gate electrode, thereby reducing the variation in the characteristics of the obtained TFT. Can be smaller.

In addition, it is possible to prevent impurities from flowing from the glass substrate between the active layer and the gate insulating film.

By doing so, the reliability of the obtained device can be increased.

In the present embodiment, the case where aluminum is used as the material forming the gate electrode has been described. However, as a material forming the gate electrode, various silicides, silicon having a conductivity type, and various metal materials can be used.

[Embodiment 2] In this embodiment, in the manufacturing process shown in Embodiment 1, the silicon oxide film 103 (see FIG. 1C) functioning as a gate insulating film is not formed by the low pressure thermal CVD method. This is an example of a case where a film is formed by a plasma CVD method.

FIG. 6 shows a manufacturing process. First, in accordance with the manufacturing process shown in Example 1, as shown in FIG.
A silicon oxide film is formed by the method D. Then, patterns 104 and 105 made of a crystalline silicon film are formed.

In this state, the silicon oxide film 601 functioning as a gate insulating film is
A film is formed to a thickness of 150 nm (for example, 100 nm).
(FIG. 6 (A))

Here, when the silicon oxide film 601 is formed by the plasma CVD method, compared with the case of the first embodiment,
There is a concern that impurities may flow from the glass substrate due to plasma damage.

However, also in the case of this embodiment, since the glass substrate is covered so as to be wrapped by the silicon oxide film 102, it is possible to greatly suppress the spillage of impurities from the substrate in practical use.

After the state shown in FIG. 6A is obtained, the aluminum film is patterned using the resist masks 20 and 21 to obtain aluminum patterns 107 and 108.
(FIG. 6 (B))

Next, with the resist masks 20 and 21 remaining, the porous anodic oxide film 10 is formed by anodic oxidation.
9 and 112 are formed. And the resist masks 20, 2
1 and an anodic oxide film 11 having a denser film quality.
0, 113 are formed. (FIG. 6 (C))

Next, the exposed silicon oxide film 601 is removed.
Further, the porous anodic oxide films 109 and 112 are removed. Thus, the state shown in FIG. 6D is obtained.

Thereafter, PTFTs (P-channel type thin film transistors) and NTFTs (N-channel type thin film transistors) are manufactured according to the same steps as those shown in FIGS. 3 (A) to 3 (C).

[Embodiment 3] This embodiment shows an example in which an inverted stagger type TFT is manufactured by utilizing the invention disclosed in this specification.

FIG. 7 shows a manufacturing process of this embodiment. First,
As shown in FIG. 7A, a silicon oxide film 702 is formed over the entire exposed surface of the glass substrate 701 by a low-pressure CVD method.

Next, a gate electrode 70 made of a silicide material is used.
Form 3 Here, the gate electrode 703 is formed using tungsten silicide formed by a sputtering method. Thus, the state shown in FIG. 7A is obtained.

When forming the gate electrode, a sputtering method is used. Since the substrate is covered with the silicon oxide film, diffusion of impurities due to the substrate being sputtered can be suppressed.

Next, a silicon oxide film 704 functioning as a gate electrode is formed by a low pressure thermal CVD method. (FIG. 7
(B))

Further, an amorphous silicon film 705 is formed by a low pressure thermal CVD method by a low pressure thermal CVD method, and is crystallized by a heat treatment. (FIG. 7 (B))

After the state shown in FIG. 7B is obtained, patterning is performed on the silicon film to obtain a pattern indicated by 706 in FIG. 7C. This pattern becomes an active layer of the TFT.

Next, a silicon nitride film is formed by a plasma CVD method and is patterned,
Is formed. (FIG. 7 (C))

Next, a source region 708, a drain region 710, and a channel region 709 are formed in a self-aligned manner by doping phosphorus ions by a plasma doping method. (FIG. 7 (D))

When the doping is completed, laser light irradiation is performed to activate the doped phosphorus and anneal the crystal structure at the time of the doping to damage it.

Next, a source electrode 711 and a drain electrode 7 are formed by a laminated film of a titanium film, an aluminum film and a titanium film.
12 are formed. (FIG. 7E)

Thus, a bottom gate type TFT is completed.

The points in the above manufacturing steps are as follows: (1) By adopting a structure in which the glass substrate 701 is covered with the base film 702, the glass substrate 70
1 to suppress the release of impurities. (2) A base film 702, a silicon oxide film 704 functioning as a gate insulating film, and an amorphous silicon film 705 serving as a starting film later forming an active layer are formed by low-pressure thermal CVD.
The plasma damage during the film formation is reduced. On the point.

With such a structure, it is possible to prevent impurities in the glass substrate from entering the active region of the TFT and adversely affecting the operation of the TFT.

The active region referred to here is a region that is sensitive to the operation of the TFT when viewed electrically, such as the surface of the active layer, the gate insulating film, and the interface between the gate electrode and the gate insulating film. Say.

[Embodiment 4] This embodiment relates to a method for growing a crystal. FIG. 8 shows an outline of a manufacturing process shown in this embodiment.

First, a glass substrate 101 is prepared. (8
(A))

Then, a silicon oxide film 102 having a thickness of 300 nm was formed on the exposed surface of the glass substrate 101 by a low pressure thermal CVD method.
To a thickness of Here, SiH is used as a source gas.
A mixed gas of ₄ and N ₂ O is used. (FIG. 8 (B))

Next, heat under reduced pressure C using Si ₂ H ₆ as a raw material gas
An amorphous silicon film 103 is formed to a thickness of 50 nm by the VD method. (FIG. 8 (C))

Next, a mask 801 is formed by forming a silicon oxide film to a thickness of 100 nm and forming an opening 803 in the silicon oxide film. (FIG. 8 (D))

It is assumed that the opening 803 has a slit shape having a longitudinal shape in the depth direction from the front of the drawing.
(FIG. 8 (D))

In this state, the nickel element is
A nickel acetate solution containing pm is applied, and an excess solution is removed using a spin coater.

In this way, as shown at 804, a state where nickel is held in contact with the surface is obtained. In this state, the amorphous silicon film 10
3 is a state in which the nickel element is held in contact with the surface. (FIG. 8 (D))

Next, heat treatment at 560 ° C. for 18 hours is performed in a nitrogen atmosphere. In this step, the opening 803
The crystal growth proceeds in the direction parallel to the substrate (the direction parallel to the film surface) as indicated by reference numeral 805 from the region. This form of crystal growth is called lateral growth. (FIG. 9A)

This crystal growth can be performed over several tens of μm. The silicon film 8 thus laterally grown
06 is obtained.

Next, the mask 801 made of a silicon oxide film is removed. Then, a resist mask (not shown) is arranged, and the silicon film is patterned.

Thus, the silicon film patterns 807 and 808 are obtained. (FIG. 9 (B))

Thereafter, NTFT and PTFT are manufactured according to the manufacturing process shown in FIG.

In this embodiment, an example in which nickel is used has been described. Fe, Co, Ru, Rh, Pd, Os, I
One or a plurality of elements selected from r, Pt, Cu, and Au can be used.

[Embodiment 5] FIG.
Shown in First, a glass substrate 101 is prepared. (FIG. 10
(A))

Next, the silicon oxide film 10 is formed by a low pressure thermal CVD method.
2 is formed. (FIG. 10B)

Next, an amorphous silicon film 103 is formed by low pressure thermal CVD. Then, a nickel acetate solution is applied to obtain a state in which the nickel element is held in contact with the surface of the amorphous silicon film as shown by 1001. (FIG. 10
(C))

Next, by performing a heat treatment at 600 ° C. for 8 hours, the amorphous silicon film 103 is crystallized, and a crystalline silicon film 1002 is obtained. (FIG. 10 (D))

Thereafter, the crystalline silicon film 1002 is patterned to form a TFT active layer.

[Embodiment 6] The present embodiment relates to a fabrication process in which the fabrication process shown in Embodiment 4 is basically improved to obtain a crystalline silicon film having higher crystallinity.

A manufacturing process of this embodiment will be described with reference to FIGS. First, a quartz substrate 101 is prepared. (FIG. 8
(A))

In this embodiment, a low-grade quartz substrate can be used. That is, a quartz substrate having a relatively high impurity concentration can be used. This is because a manufacturing process that suppresses contamination of impurities from the substrate is employed.

After preparing the quartz substrate 101, FIG.
As shown in FIG.
A film is formed to a thickness of 300 nm by the VD method.

Next, as shown in FIG. 8C, an amorphous silicon film 103 is formed to a thickness of 50 nm by low pressure thermal CVD.

Next, a mask 801 made of a silicon oxide film is formed. An opening 803 is provided in this mask.

Next, a nickel acetate solution adjusted to a nickel concentration of 100 ppm by weight is applied, and an excess solution is removed by spin coating. Thus,
As shown by 804, a state is obtained in which the nickel element is held in contact with the surface of the sample.

Next, heat treatment is performed at 560 ° C. for 18 hours in a nitrogen atmosphere. In this step, the opening 803
The crystal growth proceeds in the direction parallel to the substrate (the direction parallel to the film surface) as indicated by reference numeral 805 from the region. This form of crystal growth is called lateral growth. (FIG. 9A)

Next, the mask 801 made of a silicon oxide film is removed. Then, a heat treatment is performed at 950 ° C. for 30 minutes in an oxygen atmosphere at normal pressure containing 3% by volume of HCl to form a thermal oxide film with a thickness of 30 nm.

In this step, the nickel element in the silicon film is vaporized as nickel chloride and removed therefrom.

Further, with the formation of the thermal oxide film, the thickness of the silicon film decreases from 50 nm to 35 nm.

This step of forming a thermal oxide film has a tremendous effect on removing nickel elements and improving crystallinity.

After forming the thermal oxide film, it is removed, and a TFT is manufactured using the obtained silicon film.

In the manufacturing process shown in this embodiment, a temperature of 950 ° C. (at least 900 ° C. is required) is required in the process of forming a thermal oxide film, so a quartz substrate must be used as a substrate. Although there is a problem to be solved, a TFT having high characteristics can be obtained.

For example, in the TFT obtained according to the manufacturing process shown in the fourth embodiment, the oscillation of the ring oscillator
Although this is a level at which oscillation at about Hz can be performed, a TFT obtained by using the process described in this embodiment can oscillate 10 times or more.

[Description of Low Pressure Thermal CVD Apparatus] Here, an outline of a low pressure thermal CVD apparatus used in carrying out the invention disclosed in this specification is shown.

FIG. 11 is a schematic side view. The configuration shown here has two decompression chambers 120 made of quartz.
8 and 1209.

Reference numerals 1210 and 1211 denote heating furnaces for heating the decompression chamber, respectively.

Reference numeral 1201 denotes a substrate loading chamber. 120
Reference numeral 2 denotes a chamber for carrying the substrate into the decompression chamber 1209 and further carrying out the substrate processed in the decompression chamber 1209.

Reference numeral 1203 denotes a chamber for carrying the substrate into the decompression chamber 1208 and for carrying out the substrate processed in the decompression chamber 1208.

Reference numeral 1204 denotes a chamber for carrying out a substrate.

1201, 1202, 1203, 1204
Are all airtight chambers and have a structure that is isolated from the outside atmosphere. Here, each chamber has a structure filled with an inert gas (nitrogen gas). In order to improve the airtightness, a configuration capable of realizing a reduced-pressure atmosphere may be employed.

This apparatus has a function of forming a silicon oxide film in one chamber and forming an amorphous silicon film in the other chamber.

Further, gas supply systems 1212 and 1213 are provided. Further, exhaust systems 1214 and 1215 are provided.

[0158] Reference numeral 1207 denotes a cassette in which the substrates are stored, and the transfer and film formation of the substrates are performed in a state where the substrates are stored in the cassette. [Embodiment 7] In this embodiment, a silicon oxynitride film is used instead of a silicon oxide film by the low pressure thermal CVD method used in the other embodiments.

To form a silicon oxynitride film by a low pressure thermal CVD method, SiH ₄ , N ₂ O, and NH ₄ may be used as source gases.

[Embodiment 8] In this embodiment, examples of various semiconductor devices using TFTs obtained by using the present invention will be described.

In this embodiment, an outline of an apparatus constituted by using a TFT manufactured by using the invention disclosed in this specification will be described. FIG. 13 shows an outline of each device.

FIG. 13A shows a portable information processing terminal, which has a communication function using a telephone line.

This electronic device includes an integrated circuit 2006 using a TFT inside a main body 2001. An active matrix type liquid crystal display 2005 in which TFTs are arranged as switching elements, a camera unit 2002 for capturing images, and an operation switch 2004
It has.

Information terminals of the form shown in FIG. 13A tend to be smaller and thinner in the future. In the case of smaller and thinner devices, a configuration in which various circuits for performing information processing, an oscillation circuit, and the like in addition to an active matrix circuit for display are integrated on one substrate (called a system-on-panel) is required. It is said.

In such a configuration, it is useful to manufacture a TFT using the invention disclosed in this specification.

FIG. 13B shows an electronic device called a head mounted display. This device is
A function of attaching the main body 21201 to the head by the band 2103 and displaying an image in front of the eyes in a pseudo manner is provided. The image is created by the active matrix type liquid crystal display device 2102 corresponding to the left and right eyes.

In the active matrix section, TFTs are arranged as switching elements.

FIG. 13C has a function of displaying map information and various information based on signals from artificial satellites. Information from a satellite captured by the antenna 2204 is processed by an electronic circuit provided in the main body 2201, and necessary information is displayed on an active matrix liquid crystal display device 2202.

The operation of the apparatus is performed by operation switches 2203. In such an apparatus, a circuit using a TFT is used.

FIG. 13D shows a mobile phone. This electronic device includes an antenna 230
6, an audio output unit 2302, a liquid crystal display device 2304, operation switches 2305, and an audio input unit 2303.

[0171] The electronic device shown in FIG. 13E is a portable imaging device called a video camera. This electronic device includes a liquid crystal display 2402 attached to an opening / closing member on a main body 2401, and an operation switch 2404 attached to the opening / closing member.

Further, the main body 2401 includes an image receiving section 2406, an integrated circuit 2407, and an audio input section 240.
3, an operation switch 2404, and a battery 2405 are provided.

The electronic device shown in FIG. 13F is a projection type liquid crystal display device. This device includes a light source 2502, a liquid crystal display device 2503, and an optical system 2504 in a main body 2501, and has a function of projecting an image on a screen 2505.

As the liquid crystal display device in the electronic device described above, either a transmission type or a reflection type can be used. The transmission type is advantageous in terms of display characteristics, and the reflection type is advantageous in pursuit of low power consumption and reduction in size and weight.

As the display device, a flat panel display such as an active matrix type EL display or a plasma display can be used.

[Embodiment 9] This embodiment relates to a manufacturing process capable of removing a nickel element even when a glass substrate is used when a crystalline silicon film is obtained by using a nickel element.

FIG. 14 shows a manufacturing process.

First, the state shown in FIG. 14A is obtained according to the manufacturing steps shown in FIGS. 8A to 9A. Here, a glass substrate is used as the substrate.

FIG. 14A shows a state where crystal growth as indicated by 805 is proceeding from the region of the opening 803 formed in the mask 801.

After the lateral growth is completed, the mask 801 made of a silicon oxide film is removed, and the mask 140 made of a silicon oxide film is further removed.
1 and 1402 are arranged.

Then, phosphorus ions are acceleratedly implanted by a plasma doping apparatus. In this step, FIG.
1403, 1404, 1405 as shown in FIG.
Is doped with phosphorus. These regions have a state in which the crystal structure is destroyed and defects are formed at high density.

After obtaining the state shown in FIG. 14B, heat treatment is performed at 600 ° C. for 2 hours in a nitrogen atmosphere.

In this step, as shown in FIG.
4, nickel moves to the region of 1405. That is, 14
The nickel present in the areas 06 and 1407 is 140
3, 1404 and 1405 are obtained.

Then, the regions 1403, 1404 and 1405 are removed. 807 and 8 using the remaining silicon film
08 pattern is formed.

Thus, an active layer from which the nickel element has been removed is obtained.

In the manufacturing process shown in this embodiment, a high temperature such as 900 ° C. or higher is not required for removing nickel. For this purpose, a glass substrate can be used.

[0187]

By utilizing the invention disclosed in this specification, impurities can be removed from a glass substrate (or a suitable substrate) by TF.
It is possible to provide a configuration that prevents sneaking during T.

Further, a TFT having high reliability can be manufactured. Further, a device using a TFT can have higher performance and higher reliability.

[Brief description of the drawings]

FIG. 1 illustrates a manufacturing process of a TFT.

FIG. 2 illustrates a manufacturing process of a TFT.

FIG. 3 illustrates a manufacturing process of a TFT.

FIG. 4 is a diagram showing the proportion of impurities in a TFT.

FIG. 5 is a graph showing the proportion of impurities in a glass substrate.

FIG. 6 illustrates a manufacturing process of a TFT.

FIG. 7 illustrates a manufacturing process of a TFT.

FIG. 8 illustrates a manufacturing process of a TFT.

FIG. 9 illustrates a manufacturing process of a TFT.

FIG. 10 illustrates a manufacturing process of a TFT.

FIG. 11 is a diagram showing an outline of a low-pressure thermal CVD apparatus.

FIG. 12 is a diagram showing an outline of a device using a TFT.

FIG. 13 illustrates a manufacturing process of a TFT. Reference Signs List 101 glass substrate or quartz substrate 102 silicon oxide film (low-pressure thermal CVD film) 103 amorphous silicon film (low-pressure thermal CVD film) 104 active layer of TFT 105 active layer of TFT 106 silicon oxide film 107, 108 pattern made of aluminum film 21, 22 resist mask 109 porous anodic oxide film 110 anodic oxide film having dense film quality 111 silicon oxide film (gate electrode) 112 porous anodic oxide film 113 dense anodic oxide film 114 dense electrode 114 gate electrode 115 116, remaining silicon oxide film (gate electrode) 117 remaining silicon oxide film (gate electrode) 118 source region 119 low-concentration impurity region 120 channel region 121 low-concentration impurity region 122 drain region 123 drain region 124 low-concentration impurity region 125 channel Region 126 low Pure region 127 Source region 128 Silicon oxide film 129 Silicon nitride film 130 Polyimide resin film 131 Source electrode 132 Drain electrode 133 Drain electrode 134 Source electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 29/78 621 627G (72) Inventor Shunpei 398 Hase, Atsugi-shi, Kanagawa Prefecture Inside Semiconductor Energy Laboratory Co., Ltd.

Claims (13)

[Claims] 1. A step of forming a blocking layer on the exposed outer peripheral surface of a glass substrate or a quartz substrate by a reduced-pressure thermal CVD method, and a step of forming an amorphous silicide film by a reduced-pressure thermal CVD method covering the blocking layer. A step of forming an insulating film having the same film quality as the blocking layer by the low-pressure thermal CVD method over the silicide film; A method for manufacturing a semiconductor device, comprising the steps of: A step of forming an insulating film on the exposed upper surface, the back surface, and the side surface of the glass substrate or the quartz substrate by a reduced pressure thermal CVD method; and forming an amorphous silicide film on the exposed insulating film by a reduced pressure thermal CVD method. A step of forming an insulating film having the same film quality as the insulating film by covering the silicide film by a low pressure thermal CVD method, and forming a gate insulating film covering the silicide film in the step. A step of completing a thin film transistor as a film. 3. An amorphous silicon film or an amorphous Si _x G film according to claim 1, wherein the amorphous silicon film is an amorphous silicon film.
A method for manufacturing a semiconductor device, comprising forming a film represented by e _1-x (0 ≦ X ≦ 1). 4. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of crystallizing the amorphous silicide film using a metal element that promotes crystallization of silicon. 5. The method according to claim 1, wherein the step of crystallizing the amorphous silicide film using a metal element that promotes crystallization of silicon, and removing the region into which the metal element has been introduced. A method for manufacturing a semiconductor device, comprising: 6. A method according to claim 4, wherein the metal element for promoting crystallization of silicon is Fe, Co, Ni, or Ni.
A method for manufacturing a semiconductor device, comprising using an element selected from Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au. 7. A semiconductor device, wherein a thin film transistor is formed on one surface of a glass substrate, and an insulating film constituting a gate insulating film of the thin film transistor is provided so as to surround the glass substrate. 8. A semiconductor, wherein a thin film transistor is formed on one surface of a glass substrate, and an insulating film constituting a gate insulating film of the thin film transistor is also formed on the back surface side of the glass substrate. apparatus. 9. A semiconductor device using a thin film transistor on one surface of a glass substrate, wherein an insulating film constituting a gate insulating film of the thin film transistor is also formed on a back surface side of the glass substrate. Semiconductor device. 10. An insulating film according to claim 7, wherein an insulating film is formed on the lower surface of the active layer constituting the thin film transistor, and the insulating film is also formed on the back surface of the glass substrate. A semiconductor device characterized by the above-mentioned. 11. A semiconductor device using a thin film transistor on one surface of a glass substrate, comprising: an insulating film forming a gate insulating film of the thin film transistor; and an insulating film formed under an active layer of the thin film transistor. Have the same components, and the insulating film is also formed on the back side of the glass substrate. 12. A semiconductor device using a thin film transistor on one surface of a glass substrate, comprising: an insulating film forming a gate insulating film of the thin film transistor; and an insulating film formed under an active layer of the thin film transistor. Have the same components, and the insulating film formed on the base is formed so as to surround a glass substrate. 13. The method according to claim 11, wherein
A semiconductor device, wherein the insulating film contains a halogen element in an amount of 5 atomic% or less.