JP2006287005A - Stencil mask, its manufacturing method and method of use thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a thin layer of a stencil mask rises in its temperature owing to ionized atoms coming into collision therewith and is deformed by the heat produced thereby. <P>SOLUTION: The stencil mask 100 comprises the thin layer 25, and a thick layer 35 stacked on one surface of the thin layer 25. The thin layer 25 has a narrowed thin layer through-hole 22 formed therein, and the thick layer 35 has a wide thick layer through-hole 38 formed therein. The thin layer through hole 22 and the thick layer through-hole 38 are paired and communicated with each other. A step is formed between a side surface 29 of the thin layer 25 defining the thin layer through-hole 22 and a side surface of the thick layer 35 defining the thick layer through-hole 38. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a stencil mask used when manufacturing a semiconductor device. The stencil mask used in this specification refers to a shielding member used when selectively irradiating a predetermined position on the surface of a substrate to be processed with charged particles (ions, electrons, etc.) or electromagnetic waves such as X-rays. Say. The stencil mask of the present invention is suitably used for manufacturing an apparatus formed using a semiconductor substrate such as a switching element, a light emitting element, a light receiving element, or a micromachine.

  In the process of manufacturing a semiconductor device, a process is required in which ionized atoms (generally referred to as impurities) are introduced into a local range on the surface of the semiconductor substrate, while impurities are not introduced into other ranges. In general, this type of treatment uses a method in which a coating film is formed on the surface of a semiconductor substrate, a through hole is formed in the coating film, and impurities are introduced into the surface of the semiconductor substrate from the through hole. There are many cases. This method requires a step of forming a coating film on the surface of the semiconductor substrate, a step of forming a through hole in the coating film, a step of removing the coating film, and the like. Therefore, the number of processes required for manufacturing increases. In order to solve this problem, development of a stencil mask has been underway.

A stencil mask refers to a shielding member in which a through hole is formed in advance. In the method using a stencil mask, the surface of the semiconductor substrate is covered with a stencil mask, and then ionized atoms are introduced toward the surface of the semiconductor substrate through the stencil mask. The stencil mask is repeatedly used for a plurality of semiconductor substrates. If the stencil mask is used, a step of forming a coating film on the surface of the semiconductor substrate, forming a through hole in the coating film, and removing the coating film can be omitted. For this reason, the number of processes required for manufacturing the semiconductor device can be greatly reduced. The following is a patent document relating to this type of stencil mask.
JP 2004-207570 A JP 2004-207385 A JP 2003-37055 A JP 2003-1224097 A JP 2003-59819 A JP 2002-50565 A

The demand for miniaturizing semiconductor devices is increasing year by year. In order to obtain a miniaturized semiconductor device, the through hole of the stencil mask itself must be finely processed. Also, the distance between the through hole of the stencil mask and the adjacent through hole must be finely processed.
The stencil mask has a thin layer portion, and a plurality of through holes are formed in the thin layer portion. The through-hole is formed by etching the thin layer portion using an RIE (Reactive Ion Etching) method or the like. Since there is a limit to the size of the etching aspect ratio (the value obtained by dividing the depth of the through hole by the width of the through hole), the width of the through hole is reduced or the distance between adjacent through holes is reduced. In order to achieve this, it is preferable to make the thin layer portion thinner.
However, when the thin layer portion is thinned, when ionized atoms are introduced, the temperature of the thin layer portion increases due to ionized atoms that collide with the wall of the thin layer portion located between the adjacent through holes. The layer part may be deformed. When the thin layer portion is deformed, there arises a problem that the introduction range of ionized atoms shifts and a problem that the size of the introduction range of ionized atoms changes. As the thin layer portion becomes thinner, the mechanical strength of the thin layer portion also decreases, and there arises a problem that handling becomes very difficult.

  In order to suppress the deformation of the thin layer portion, it is conceivable to increase the mechanical rigidity by increasing the thickness of the thin layer portion. Increasing the thickness of the thin layer is expected to increase heat transfer efficiency and suppress temperature rise. For example, if an etching technique using an alkaline solution that realizes high anisotropy is used, it may be possible to process a fine through hole in a thick thin layer portion. Alternatively, it may be possible to process a through hole group in which the distance between adjacent through holes is miniaturized.

However, when the thickness of the layer forming the through-hole group is increased, the through-hole is defined when ionized atoms pass through a narrow and long through-hole (the thicker the layer, the longer the distance between the through-holes). The amount of ionized atoms that collide with the sides increases. For this reason, the passage amount of ionized atoms passing through the through hole is reduced. Therefore, it becomes difficult to introduce a desired amount of ionized atoms into the surface of the semiconductor substrate. In order to compensate for the decreasing passage amount, it is also conceivable to increase the output of an ion implantation apparatus used for introducing ionized atoms. However, when the output of the ion implantation apparatus is increased, the amount of ionized atoms that pass through can be secured, but the amount of ionized atoms that collide with the side surface that defines the through hole also increases. Therefore, even if the thickness of the layer forming the through hole group is increased, eventually the stencil mask is deformed due to the temperature rise.
The above phenomenon is not limited to the case of introducing ionized atoms, and can generally occur in a stencil mask used when irradiating charged particles or electromagnetic waves.
The objective of this invention is providing the stencil mask which can suppress a deformation | transformation, ensuring the passage amount of a charged particle or electromagnetic waves.

The stencil mask of the present invention has a thin layer portion and a thick layer portion laminated on one surface of the thin layer portion. A plurality of narrow through holes are formed in the thin layer portion, and a plurality of wide through holes are formed in the thick layer portion. The thin layer through-hole in the thin layer part and the thick layer through-hole in the thick layer part communicate with each other in pairs. As a result, a step is formed between the side surface of the thin layer portion that defines the thin layer through hole and the side surface of the thick layer portion that defines the thick layer through hole.
Here, “communicating in pairs” means that one thick layer through hole of the thick layer portion communicates with one thin layer through hole of the thin layer portion. This does not mean a case where a plurality of thin layer through holes in the thin layer portion communicate with one thick layer through hole or a case where one thin layer through hole communicates with a plurality of thick layer through holes.
Moreover, you may express the stencil mask of this invention as follows.
The stencil mask of the present invention has a thin layer portion and a thick layer portion laminated on one surface of the thin layer portion. A plurality of thin layer through holes are formed in the thin layer portion, and a plurality of thick layer through holes are formed in the thick layer portion. The wall located between the thin layer through hole penetrating the thin layer part is wide and located between the thick layer through hole penetrating the thick layer part and the thick layer through hole. The wall is narrow. The wall located between the thin layer through hole and the thin layer through hole penetrating the thin layer part has a wall located between the thick layer through hole and the thick layer through hole penetrating the thick layer part. Laminated. As a result, a step is formed between the side surface of the thin layer portion that defines the thin layer through hole and the side surface of the thick layer portion that defines the thick layer through hole.

In the above stencil mask, the thin layer penetrating the thick layer portion from one surface of the thin layer through hole penetrating the thin layer portion and the wall (corresponding to the shielding pattern) located between the thin layer through holes. A wall located between the through hole and the thick layer through hole extends. The wall of the thick layer portion has an effect of transferring the heat of the wall of the thin layer portion to the outside, and suppresses the temperature rise of the wall of the thin layer portion. Due to the presence of the thick layer wall, the mechanical strength of the stencil mask is improved, and the phenomenon that the thin layer wall is deformed due to a temperature rise can be further suppressed.
Further, the thin layer through hole penetrating the thin layer portion is formed narrow, and the thick layer through hole penetrating the thick layer portion is formed wide. When the through hole is viewed from the thick layer portion side, the wide thick layer through hole in the thick layer portion communicates with the narrow thin layer through hole in the thin layer portion. The thick layer portion side is a side on which charged particles or electromagnetic waves are incident, and the thin layer portion side is a side on which charged particles or electromagnetic waves are emitted. Therefore, for example, when ionized atoms are allowed to pass through using this stencil mask, the ionized atoms pass through the wide thick layer through-holes and the narrow thin layer through-holes and are adjusted to a predetermined pattern and emitted. . When ionized atoms pass through a wide thick layer through-hole, a sufficient width is ensured in the thick layer through-hole, so that the amount of passage does not extremely decrease. Further, even when ionized atoms pass through a narrow thin layer through-hole, the thickness of the thin layer portion is thin, so that the passing amount is not extremely reduced. For this reason, when ionized atoms pass through the thick layer part and also through the thin layer part, a decrease in the passing amount is suppressed in both cases. Therefore, a sufficient amount of ionized atoms can be secured. From this, it is possible to secure a sufficient amount of ionized atoms to pass without increasing the output of the ion implantation apparatus and irradiating the ionized atoms.
Moreover, since the temperature increase of the thin layer portion can be suppressed by the heat transfer effect of the thick layer portion wall, the stencil mask of the present invention irradiates many ionized atoms by increasing the output of the ion implantation apparatus. It can withstand the use. By using the stencil mask of the present invention, it is possible to form a high-concentration ion implantation region or to form an ion implantation region in a deep part of the substrate to be processed, and to form various ion implantation regions. Become.
When the above stencil mask is used, a fine-structured device can be manufactured by a fine through-hole formed in the thin layer portion. The heat of the wall of the thin layer portion can be effectively transferred to the outside by the wall of the thick layer portion. Thereby, the temperature rise of the wall of a thin layer part can be suppressed. The wall of the thick layer portion provides a wide thick layer through hole in the thick layer portion, so that the ionized atoms passing through the thin layer through hole of the thin layer portion are not extremely reduced by the thick layer portion wall.
A stencil mask having high transmission capability of ionized atoms and the like, excellent mechanical strength, and hardly deformed is realized.

It is preferable that the side surface of the thick layer portion defining the thick layer through hole extends in a direction substantially perpendicular to the one surface of the thin layer portion.
In this case, the wall of the thick layer portion can be elongated in the stacking direction within the range where the wall of the thin layer portion exists. The height in the stacking direction of the wall of the thick layer portion can be increased. By increasing the height of the thick layer portion in the stacking direction, the heat dissipation effect and the heat transfer effect can be improved, and the mechanical rigidity of the stencil mask can also be improved.

The thin layer portion is preferably a semiconductor layer containing a first conductivity type impurity, and the thick layer portion is preferably a semiconductor layer containing a second conductivity type impurity.
Conventionally known stencil masks are often manufactured using an SOI (Silicon On Insulator) substrate. The SOI substrate includes a silicon oxide film. The thermal conductivity of the silicon oxide film is extremely low. Therefore, the conventional stencil mask has a structure in which heat is easily accumulated in the thin layer portion. Therefore, an excessive temperature rise in the thin layer portion has been a problem. The stencil mask of the present invention has a structure that can be manufactured without using an SOI substrate. The stencil mask of the present invention has a structure that can be manufactured using a semiconductor layer containing impurities. For this reason, it is remarkably improved in terms of heat conduction as compared with a stencil mask manufactured using an SOI substrate. The temperature rise of the thin layer portion can be remarkably suppressed.
Further, the thin layer portion and the thick layer portion may be formed in a semiconductor layer having a continuous crystal structure.
The semiconductor layer is preferably formed of a silicon single crystal layer. The structure can be manufactured using a general-purpose silicon wafer or the like.

It is preferable that an encircling wall that goes around the periphery of the thick layer through hole group is formed in the thick layer portion.
The surrounding wall functions as a support portion for the thin layer portion. The mechanical rigidity of the stencil mask can be improved.

The surrounding wall is preferably connected to the cooling means.
By providing the cooling means, the heat accumulated in the thin layer portion can be transferred to the cooling means through the surrounding wall.

  It is preferable that the height in the stacking direction of the surrounding wall is equal to the height in the stacking direction of the wall located between the thick layer through hole penetrating the thick layer portion and the thick layer through hole. In addition, the height of the wall located between the thick layer through-hole penetrating the thick layer portion and the thick layer through-hole may be formed lower than the height of the surrounding wall.

The ion implantation apparatus provided with the stencil mask of the present invention is extremely useful. That is, an ion implantation apparatus according to the present invention includes an ion generation unit that generates ions, a mass analysis unit that selects necessary ions from the generated ions, an acceleration unit that accelerates selected ions, and a substrate to be processed. An implantation chamber is provided, and a stencil mask provided between the acceleration means and the substrate to be processed is provided.
In a stencil mask provided in a conventional ion implantation apparatus, deformation due to a temperature rise has been a serious problem. For this reason, the ion implantation apparatus can be used only within a range where the stencil mask is not deformed, and the performance of the ion implantation apparatus cannot be sufficiently exhibited. The stencil mask of the present invention can effectively cope with deformation and the like due to temperature rise. For this reason, by providing the stencil mask of the present invention, an extremely useful ion implantation apparatus can be realized.

It is preferable to use the stencil mask of the present invention by covering the surface of the substrate to be processed and irradiating the surface of the substrate to be processed with charged particles or electromagnetic waves through the stencil mask.
When the stencil mask of the present invention is used, the surface of the substrate to be processed can be finely processed. Moreover, since the temperature rise of a thin layer part is suppressed, the output of an apparatus can be enlarged and a charged particle or electromagnetic waves can be irradiated. When the stencil mask of the present invention is used, various introduction regions can be formed on the substrate to be processed.

The present inventors also created a method suitable for manufacturing the above stencil mask.
In one manufacturing method of the present invention, a semiconductor thin film is etched by etching from an exposed surface on the semiconductor thin layer side of a semiconductor substrate in which a semiconductor thick layer containing a second conductivity type impurity is stacked on a semiconductor thin layer containing a first conductivity type impurity. A step of forming a plurality of thin layer through holes penetrating the layer and a step of forming a plurality of thick layer through holes penetrating the semiconductor thick layer by etching from an exposed surface on the semiconductor thick layer side. At this time, the semiconductor thick layer is etched at a position corresponding to the thin layer through hole penetrating the semiconductor thin layer when viewed in plan. Further, the thin layer through hole is etched narrowly, and the thick layer through hole is etched wide. By etching the thin layer through hole narrowly and etching the thick layer through hole wide, between the side surface of the semiconductor thin layer defining the thin layer through hole and the side surface of the semiconductor thick layer defining the thick layer through hole A step can be formed.
The semiconductor thin layer is adjusted to be thin enough to make a fine thin layer through hole group. Thereby, a fine thin layer through-hole group can be made with respect to the semiconductor thin layer. In the step of forming the thin layer through hole group, an RIE method, a wet etching method using an alkaline solution, or other etching techniques can be used. Next, a wide thick through hole is formed from the exposed surface of the thick semiconductor layer toward the thin through hole of the thin semiconductor layer. Through these steps, a narrow thin layer through hole is formed in the semiconductor thin layer, and a wide thick layer through hole is formed in the semiconductor thick layer. When the through hole is viewed from the semiconductor thick layer side, a state in which the wide thick layer through hole communicates toward the narrow thin layer through hole is obtained. A step is formed between the side surface defining the thin layer through hole and the side surface defining the thick layer through hole. The stencil mask of the present invention can be obtained.

In the step of forming a plurality of thick layer through holes in the semiconductor thick layer, the following method can be suitably used. First, the surface orientation of the exposed surface of the semiconductor thick layer is selected as (211). Further, wet etching is performed using an alkaline solution from the exposed surface of the semiconductor thick layer in a state where a voltage at which the semiconductor thin layer and the semiconductor thick layer are reversely biased is applied between the semiconductor thin layer and the semiconductor thick layer. Thereby, a plurality of thick layer through holes reaching the semiconductor thin layer can be formed.
In wet etching using an alkaline solution, if (211) is selected as the surface orientation of the exposed surface of the semiconductor thick layer, anisotropic etching proceeds along the stacking direction of the semiconductor thick layer. Can do. Furthermore, since the semiconductor thin layer and the semiconductor thick layer are reversely biased, the progress of anisotropic etching can be stopped at the interface between the semiconductor thin layer and the semiconductor thick layer. A stencil mask can be manufactured with high accuracy.

Another manufacturing method of the present invention includes a step of forming a plurality of shallow recesses that enter the semiconductor substrate from the surface of the semiconductor substrate. Furthermore, a step of forming a mask material on the side surface of the semiconductor substrate that defines the recess group is provided. Furthermore, a step of forming a trench that penetrates deeply into the deep part of the semiconductor substrate from the semiconductor substrate exposed on the bottom surface of the recess group is provided by anisotropic etching. Furthermore, a step of expanding a side surface of the semiconductor substrate that defines the trench by isotropic etching is provided.
When this manufacturing method is used, a stencil mask can be manufactured using a semiconductor substrate having a continuous crystal structure. First, a plurality of shallow recesses that enter the semiconductor substrate from the surface of the semiconductor substrate are formed. Next, a mask material is formed on the side surface of the semiconductor substrate that defines the recess group. Next, a trench that penetrates deeply into the deep portion of the semiconductor substrate from the semiconductor substrate exposed at the bottom surface of the recess group is formed by anisotropic etching, and then the trench is expanded by isotropic etching. In this isotropic etching, since the mask material is formed on the side surface of the concave group, the width of the concave group is maintained. On the other hand, the width of the trench is expanded. Thereby, a narrow through-hole (concave) and a wide through-hole (trench) are formed. When the through hole is viewed from the back surface of the semiconductor substrate, a state in which the wide through hole (trench) communicates toward the narrow through hole (concave) is obtained. A step is formed between the side surface defining the narrow through-hole (concave) and the side surface defining the wide through-hole (trench). The stencil mask of the present invention can be obtained.

  The stencil mask of the present invention includes a thin layer portion having a small thickness, and a plurality of fine thin layer through holes are formed in the thin layer portion. Furthermore, by providing the wall of the thick layer part, the heat of the wall of the thin layer part can be effectively radiated or transferred to the outside. The strength of the stencil mask is improved by the thick wall. Due to these synergistic effects, deformation of the thin layer portion can be suppressed. A thick layer through-hole wider than the through-hole in the thin layer portion is formed in the thick layer portion, and ionized atoms passing through the thin layer through-hole in the thin layer portion are hardly shielded.

The main features of the examples are listed.
(1st form) It is a stencil mask provided with the thin layer part and the thick layer part laminated | stacked on one surface of the thin layer part.
(2nd form) The stencil mask of the 1st form is provided with the through-hole group connected from an entrance plane to an output surface, and the width | variety by the side of an entrance plane is formed larger than the width | variety by the side of an output surface.
(Third embodiment) In the stencil mask of the first embodiment, the width of the through hole penetrating the thick layer portion is formed larger than the width of the through hole penetrating the thin layer portion.
(4th form) In the stencil mask of 1st form, the side surface of the thin layer part which defines the thin layer through-hole which penetrates a thin layer part, and the thick layer part which defines the thick layer through hole which penetrates a thick layer part Side surfaces are not continuous in the stacking direction.
(5th form) The side surface which demarcates a thin layer through-hole, and the side surface which demarcates a thick layer through-hole have shifted | deviated to the direction orthogonal to the lamination direction, and the level | step difference is formed between both. The overhang width of the step is formed to be substantially constant at any step.

Embodiments will be described in detail below with reference to the drawings.
(First embodiment)
1 to 3 show a stencil mask 100 used in ion implantation. The stencil mask 100 is placed on the surface of a semiconductor layer to be processed for ion implantation, and is used to selectively introduce ions into the surface of the semiconductor layer to be processed. FIG. 1 is a perspective view showing the entire stencil mask 100. FIG. 2 is an enlarged perspective view of a main part of the stencil mask 100. FIG. 3 is a longitudinal sectional view of the stencil mask 100, which is schematically shown.
FIG. 4 shows a configuration of the ion implantation apparatus 10 in which the stencil mask 100 is used. The ion implantation apparatus 10 includes an ion source 2 (an example of an ion generation unit) that generates ions, a mass analyzer 3 (an example of a mass analysis unit) that selects necessary ions from the generated ions, and selected ions. And an implantation chamber 6 in which a semiconductor layer 7 to be processed to be ion-implanted is disposed. It can also be said that the surface of the semiconductor layer 7 to be processed is covered with the stencil mask 100 and the stencil mask 100 is provided between the accelerator 4 and the semiconductor layer 7 to be processed. Ions accelerated by the accelerator 4 are swept by the scanner device 5 and are irradiated almost planely toward the stencil mask 100. Ions that have passed along the pattern of the stencil mask 100 are introduced into the surface of the semiconductor layer 7 to be processed.

As shown in FIGS. 1 to 3, the stencil mask 100 includes a thin layer portion 25 and a thick layer portion 35 laminated on one surface of the thin layer portion 25. The stencil mask 100 is formed using a semiconductor substrate made of silicon single crystal. The plane orientation is shown in FIGS.
As shown in FIG. 1, a plurality of stripe-shaped thin layer through holes 22 are formed in the thin layer portion 25. 14 is an exit surface, and 16 is an entrance surface. The ionized atoms incident in a plane from the incident surface 16 side pass through the stripe-shaped thin layer through-holes 22 and are irradiated in a stripe pattern on the surface of the semiconductor layer to be processed.

As shown in FIGS. 2 and 3, the thin layer portion 25 of the stencil mask 100 is formed with a plurality of thin layer through holes 22 penetrating the thin layer portion 25. In the thick layer portion 35 of the stencil mask 100, a plurality of thick layer through holes 38 penetrating the thick layer portion 35 are formed. The thin layer through hole 22 penetrating the thin layer part 25 is narrow, and the thick layer through hole 38 penetrating the thick layer part 35 is formed wide. Also, the width of the thin layer portion wall 24 located between the thin layer through hole 22 and the thin layer through hole 22 of the thin layer portion 25 is wide, and the thick layer through hole 38 and the thick layer through hole of the thick layer portion 35 are wide. It can also be said that the width of the thick layer portion wall 32 located between 38 is narrow.
The thin layer through hole 22 of the thin layer portion 25 and the thick layer through hole 38 of the thick layer portion 35 communicate with each other in a pair. One thin layer through hole 22 communicates with one thick layer through hole 38. It can also be said that the thin layer wall 24 and the thick layer wall 32 are laminated in pairs.
A thick layer wall 32 extends from one surface of the thin layer wall 24. The thick layer wall 32 is formed in a thin plate shape. The side surface 39 (which is the side surface 39 of the thick layer portion wall 32) defining the thick layer through hole 38 is the side surface 29 (the thin layer portion wall 24) of the thin layer portion 25 defining the thin layer through hole 22. The side range 29) extends in the stacking direction. The side surface 39 of the thick layer portion wall 32 and the side surface 29 of the thin layer portion wall 24 are shifted in the direction orthogonal to the stacking direction. Therefore, a step 21 is formed between the side surface 29 of the thin layer portion 25 that defines the thin layer through hole 22 and the side surface 39 of the thick layer portion 35 that defines the thick layer through hole 38. The step 21 is formed in each of the plurality of through holes, and the overhang width 42 of all the steps 21 is formed to be substantially constant.

  As shown in FIG. 3, the surrounding thin layer portion wall 26 and the surrounding thick layer portion wall 34 are formed in a round at positions around the thin layer through hole 22 group and the thick layer through hole 38 group. The surrounding thin layer portion wall 26 and the surrounding thick layer portion wall 34 have a function of improving the mechanical rigidity of the thin layer portion 25. In addition, the surrounding thin layer portion wall 26 and the surrounding thick layer portion wall 34 are also used as contact portions with other installation apparatuses when the stencil mask 100 is placed above the semiconductor layer to be processed. The thick layer wall 32 and the surrounding thick layer wall 34 are connected at the peripheral position. A cooling device 82 is provided on the back surface of the surrounding thick layer portion wall 34.

  As shown in FIG. 2, since the thickness of the thin layer portion 25 (corresponding to that shown in FIG. 25) is thin, a plurality of narrow thin layer through holes 22 can be formed in the thin layer portion 25. Specifically, the thickness of the thin layer portion 25 is about 5 μm, and the width 28 of the thin layer through hole 22 of the thin layer portion 25 is about 0.5 μm. Therefore, the aspect ratio (a value obtained by dividing the thickness of the thin layer portion 25 by the width 28 of the thin layer through-hole 22) is about 10. If the aspect ratio is about 10, a plurality of thin layer through holes 22 having a narrow width with respect to the thin layer portion 25 can be formed by using an etching process using the RIE method. The width 27 of the thin layer portion wall 24 is 3.5 μm.

  The width 33 of the thick layer wall 32 is about 2 μm. The height of the thick layer portion 35 in the stacking direction (corresponding to 35 in the figure) is about 200 μm. The thick layer wall 32 can suppress the temperature rise of the thin layer wall 24 by radiating and transferring the heat of the thin layer wall 24 to the outside. Since the thick layer wall 32 is formed in a pair with each thin layer wall 24, the temperature rise of the thin layer wall 24 is remarkably suppressed. The phenomenon that the thin layer portion wall 24 is deformed is remarkably suppressed. Further, the mechanical rigidity of the thin layer portion wall 24 is also improved by the thick layer portion wall 32. Since the thick layer wall 32 is formed in pairs with each thin layer wall 24, the mechanical rigidity of the thin layer wall 24 is greatly improved. Further, since the thick layer wall 32 and the surrounding thick layer wall 34 are connected at the peripheral position, the mechanical rigidity of the thin layer wall 24 is remarkably improved.

  The width 28 of the thin layer through hole 22 of the thin layer portion 25 is 0.5 μm, and the width 38 of the thick layer through hole 38 of the thick layer portion 35 is 2.0 μm. The thin layer through hole 22 of the thin layer portion 25 is formed narrow, and the thick layer through hole 38 of the thick layer portion 35 is formed wide. When viewed from the thick layer portion 35 side, the wide thick layer through hole 38 of the thick layer portion 35 communicates with the narrow thin layer through hole 22 of the thin layer portion 25. Since the thick layer wall 32 extends within the range of the thin layer wall 24 substantially perpendicularly to the stacking direction, it does not obstruct the path of ionized atoms passing therethrough. When ionized atoms pass through the wide thick layer through-hole 38, a sufficient width is ensured, so that the passing amount does not extremely decrease. Even when ionized atoms pass through the narrow thin layer through hole 22, the thin layer wall 24 is formed thin, so that the ionized atom collides with the side surface of the thin layer wall 24 that defines the thin layer through hole 22. The phenomenon is suppressed, and the passing amount does not extremely decrease. For this reason, a sufficient amount of ionized atoms can be secured.

FIG. 5 schematically shows the distribution of the amount of ionized atoms passing through the stencil mask 100. FIG. 5A shows a case of the stencil mask 100, and FIG. 5B shows a case where no step is formed between the thin layer portion and the thick layer portion (as a comparative example), that is, the width is narrow. This is a case where the through hole extends long. It should be noted that the vertical positions of the entrance surface and the exit surface are inverted with respect to the illustrations of FIGS.
First, the case of a comparative example will be described. When the through-holes extend long, some of the ionized atoms that travel in the through-holes are caused by the space charge effect (a phenomenon that diverges outward based on the repulsive force between positively charged ionized atoms). It impacts and absorbs the defining side. Therefore, as shown in FIG. 5B, the distribution of the amount of ionized atoms that have passed through the stencil mask has a large difference between the side close to the side surface of the through hole and the center side of the through hole. Is extremely small. For this reason, it is difficult not only to form an ionized atom introduction region having a uniform distribution, but also to introduce ionized atoms at a high concentration. It is conceivable to increase the output of the ion implantation apparatus to increase the amount of ionized atoms introduced. In this case, however, the amount of ionized atoms that collide with the side surface of the through hole also increases, and the stencil mask is deformed.
On the other hand, in the stencil mask 100 of the present embodiment, the distribution of the amount of ionized atoms passing through the stencil mask 100 is made uniform, and the amount of ionized atoms passing therethrough is large. By using the wide thick layer through-hole 38, the amount of ionized atoms passing through the stencil mask 100 can be increased and a uniform distribution can be obtained. Furthermore, by making the overhang width 42 of the step 21 constant, the distribution of ionized atoms that pass through can be made extremely uniform. Since the amount of ionized atoms passing therethrough can be increased, a high concentration ionized atom introduction region can also be formed. By using the stencil mask 100 of this embodiment, various ionized atom introduction regions can be formed.

The stencil mask 100 has the following other features.
A cooling device 82 is connected to the back surface of the surrounding thick layer portion wall 34. An example of the cooling device 82 used here is an electrostatic chuck.
By connecting the cooling device 82, the heat accumulated in the thin layer portion wall 24 can be transferred to the cooling device 82 through the surrounding thick layer portion wall 34. In the case of a stencil mask formed using an SOI substrate as in the conventional structure, an embedded silicon oxide film is interposed between the surrounding thin layer portion wall and the surrounding thick layer portion wall. Even if a cooling device is provided on the wall, heat conduction is hindered by the buried silicon oxide film, and a sufficient cooling effect cannot be obtained. On the other hand, in the stencil mask 100 of this embodiment, since there is no buried silicon oxide film, the heat accumulated in the thin layer wall 24 is efficiently released to the cooling device 82 via the surrounding thick layer wall 34. Can do. By providing the cooling device 82, a cooling effect can be obtained effectively.

(Production method of the first embodiment)
A method for manufacturing the stencil mask 100 will be described with reference to FIGS.
First, as shown in FIG. 6, a semiconductor substrate in which an n-type semiconductor thin layer 20 and a p-type semiconductor thick layer 30 are stacked is prepared. The semiconductor thin layer 20 can be obtained by epitaxial growth from the surface of the semiconductor thick layer 30. Instead of epitaxial growth, an n-type impurity may be introduced into the surface of the p-type semiconductor thick layer to obtain a semiconductor substrate, or the semiconductor substrate may be obtained by bonding the n-type semiconductor thin layer and the p-type semiconductor thick layer together. You may get
Next, as shown in FIG. 7, a CVD oxide film 50 is patterned on the surface of the semiconductor thin layer 20 by using a CVD (Chemical Vapor Deposition) method. Instead of the CVD oxide film 50, an HTO (High Temperature Oxide) film, a thermal oxide film, or a resist film may be used.
Next, as shown in FIG. 8, a plurality of thin layer through holes 22 are formed in the semiconductor thin layer 20 exposed from the CVD oxide film 50 by using a reactive ion etching (RIE) method. By forming the thin layer through hole 22, a thin layer part wall 24 is formed in the semiconductor thin layer 20 positioned between the thin layer through hole 22 and the thin layer through hole 22. An encircling thin layer wall 26 is formed around the thin layer wall 24 in the semiconductor thin layer 20 located in the periphery. The thin layer through hole 22 passes through the semiconductor thin layer 20 and reaches the semiconductor thick layer 30.

Next, as shown in FIG. 9, the CVD oxide film 50 is removed using an etching method.
Next, as shown in FIG. 10, a thermal oxide film 52 is formed on all exposed surfaces of the semiconductor thin layer 20 and the semiconductor thick layer 30 using a thermal oxidation method.
Next, as shown in FIG. 11, a part of the thermal oxide film 52 formed on the back surface of the semiconductor thick layer 30 is removed to form a plurality of regions 54. When viewed in plan, the region 54 from which the thermal oxide film 52 has been removed corresponds to the position of the thin layer through-hole 22 on the surface side. The region 54 where the thermal oxide film 52 is removed is adjusted to be larger than the width of the thin layer through hole 22.

Next, as shown in FIG. 12, anisotropic etching is performed from the back surface of the semiconductor thick layer 30 exposed from the region 54 where the thermal oxide film 52 has been removed. The plurality of thick layer through holes 38 formed by anisotropic etching reach the thin layer through holes 22. Through this stage, a thick layer wall 32 is formed in the semiconductor thick layer 30 located between the thick layer through hole 38 and the thick layer through hole 38, and is positioned around the thick layer wall 32. An encircling thick layer wall 34 is formed around the thick layer wall 32 in the semiconductor thick layer 30.
For this anisotropic etching, electric field etching can be preferably used. The specific method will be described with reference to FIG.
Reference numeral 91 denotes an alkaline solution such as potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH). 92 is a potentiostat (electrochemical measurement device), 93 is an ammeter, 94 is a reference electrode, and 95 is a counter electrode. Terminals 96, 97, 98 extending from the potentiostat 92 are connected to the semiconductor thin layer 20, the reference electrode 94, and the counter electrode 95.
The anisotropic etching is performed by immersing the semiconductor substrate in the alkaline solution 91. At this time, the voltage applied to the semiconductor thin layer 20 is adjusted to be higher than that of the counter electrode 95. Since the semiconductor thick layer 30 is exposed to the alkaline solution 91, the potential of the semiconductor thick layer 30 is fixed to the potential of the alkaline solution 91. That is, the potential of the semiconductor thick layer 30 is fixed to the potential of the counter electrode 95. On the other hand, a voltage higher than that of the counter electrode 95 is applied to the semiconductor thin layer 20. Therefore, the n-type semiconductor thin layer 20 and the p-type semiconductor thick layer 30 are reverse-biased. In the wet etching using the alkaline solution 91, if (211) is selected as the surface orientation of the surface of the semiconductor thick layer 30, anisotropic etching proceeds toward the stacking direction of the semiconductor thick layer 30. Can be made. Specifically, since the etching rate ratio of the plane orientations (211), (110), and (111) is 1.3: 0.06: 0.005, it is directed toward the plane orientation (211). Etching can proceed. Further, since the semiconductor thin layer 20 and the semiconductor thick layer 30 are reverse-biased, the thick layer through-hole 38 that has progressed to the interface between the semiconductor thin layer 20 and the semiconductor thick layer 30 undergoes anodic oxidation at the interface and is etched. Progress stops. Note that by using the ammeter 93, it is possible to monitor whether or not the thick layer through hole 38 has advanced to the interface. By using the electric field etching, the thick layer through hole 38 can be formed with high accuracy.
Finally, the stencil mask 100 of this embodiment can be obtained by removing the thermal oxide film 52 using hydrofluoric acid (HF), buffered hydrofluoric acid (BHF), or the like.

(Second embodiment)
In FIG. 14, the longitudinal cross-sectional view of the stencil mask 200 is typically shown.
In the stencil mask 200, the height of the thick layer wall 132 is adjusted to be smaller than the height of the surrounding thick layer wall 134. The height of the thick layer wall 132 in the central region 162 where the thin layer through hole 122 group and the thick layer through hole 138 group are formed is adjusted to be smaller than the height of the surrounding thick layer wall 134. When the stencil mask 200 is used, even when ionized atoms pass through the thick layer through hole 138 of the thick layer portion 135, the phenomenon that the amount of passage is reduced by colliding with the side surface of the thick layer portion wall 132 is reduced. be able to. The stencil mask 200 can greatly increase the amount of ionized atoms passing therethrough.
The stencil mask 200 is lower in heat dissipation and mechanical rigidity than the stencil mask 100 of the first embodiment. However, the permeability of ionized atoms can be significantly improved. That is, the stencil mask 200 can be said to be a structure in which the balance of these characteristics can be adjusted by changing the height of the thick layer portion wall 132 in the stacking direction. When the structure of the stencil mask 200 is adopted, it is possible to obtain a stencil mask having a desired balance of heat dissipation, mechanical rigidity, and ionized atom permeability.

(Manufacturing method of the second embodiment)
A method for manufacturing the stencil mask 200 will be described with reference to FIGS.
Until the thermal oxide film 152 is formed, the same process as that of the stencil mask 100 of the first embodiment can be performed (until the stage shown in FIG. 10 of the first embodiment).
Next, as shown in FIG. 15, a part of the thermal oxide film 152 formed on the back surface of the semiconductor thick layer 130 is removed. When viewed in a plan view, the region 156 from which the thermal oxide film 152 has been removed corresponds to a region where the thin layer through-hole 122 group is formed.
Next, as shown in FIG. 16, the semiconductor thick layer 130 exposed from the region 156 from which the thermal oxide film 152 has been removed is removed by anisotropic etching. The anisotropic etching can utilize wet etching using an alkaline solution. At this time, anisotropic etching is stopped before the removed portion reaches the semiconductor thin layer 120 through the semiconductor thick layer 130. For example, it may be adjusted according to time or the like. As a result, as shown in FIG. 16, a recess corresponding to the central region 162 is formed on the back surface of the thick semiconductor layer 130.
Next, as shown in FIG. 17, a thermal oxide film 158 is formed on the semiconductor thick layer 130 exposed in the recess by using a thermal oxidation method.

Next, as shown in FIG. 18, a part of the thermal oxide film 158 formed in the semiconductor thick layer 130 is removed to form a plurality of regions 159. When viewed in plan, the region 159 from which the thermal oxide film 158 has been removed corresponds to the position of the thin through hole 122 on the surface side. The region 159 from which the thermal oxide film 158 has been removed is formed larger than the width of the thin through hole 122.
Next, as shown in FIG. 19, the semiconductor thick layer 130 exposed from the region 159 from which the thermal oxide film 158 has been removed is removed by anisotropic etching. The thick layer through hole 138 reaches the thin layer through hole 122. For this anisotropic etching, it is preferable to use the electric field etching described in the first embodiment. As in the case of the first embodiment, the progress of the trench 138 that has progressed to the interface can be stopped by reverse biasing the interface between the semiconductor thin layer 120 and the semiconductor thick layer 130.
Finally, the thermal oxide films 152 and 158 are removed using hydrofluoric acid (HF), buffered hydrofluoric acid (BHF), or the like, whereby the stencil mask 200 shown in FIG. 14 can be obtained.

(Third embodiment)
FIG. 20 schematically shows a longitudinal sectional view of the stencil mask 300.
In the stencil mask 300, the thin layer portion wall 224, the surrounding thin layer portion wall 226, the thick layer portion wall 232, and the surrounding layer portion wall 234 are integrally formed. The stencil mask 300 is manufactured using a single semiconductor substrate having a continuous crystal structure. The stencil mask 100 of the first embodiment and the stencil mask 200 of the second embodiment are both thick layer through-holes 38 and 138 from the back side with respect to the thin layer through-holes 22 and 122 previously formed on the front side. It is necessary to form the group by matching the positional relationship in the stacking direction. Both the stencil mask 100 of the first embodiment and the stencil mask 200 of the second embodiment often require accurate alignment. The stencil mask 300 of the third embodiment does not include an alignment step for matching the thin layer through hole and the thick layer through hole. The stencil mask 300 of the third embodiment can match the thin layer through hole and the thick layer through hole without performing the alignment step. It can be said that the stencil mask 300 of the third embodiment is a structure in which it is easy to obtain a desired structure.

(Manufacturing method of the third embodiment)
A method for manufacturing the stencil mask 300 will be described with reference to FIGS.
First, as shown in FIG. 21, a semiconductor substrate 270 is prepared.
Next, as shown in FIG. 22, the first CVD oxide film 282 is patterned on the surface of the semiconductor substrate 270 by using the CVD method. Instead of the first CVD oxide film 282, an HTO film, TEOS (tetraethyl orthosilicate) film, silicon nitride film, or thermal oxide film may be used.
Next, as shown in FIG. 23, a plurality of shallow recesses 222 are formed on the surface of the semiconductor substrate 270 exposed from the first CVD oxide film 282 by using the RIE method. The concave 222 group later constitutes the thin layer through hole 222 of the stencil mask 300. The height in the thickness direction of the thin layer portion wall 224 of the stencil mask 300 is adjusted by the depth of the recess 222 group.
Next, as shown in FIG. 24, a second CVD oxide film 284 is formed using the CVD method.
Next, as shown in FIG. 25, the second CVD oxide film 284 formed on the bottom surface of the recess 222 group is removed by using the RIE method. As a result, a state in which the second CVD oxide film 284 remains on the side surface of the semiconductor substrate 270 defining the recess 222 is obtained. In this embodiment, the second CVD oxide film 284 formed on the surface of the first CVD oxide film 282 is also removed. However, if necessary, the second CVD oxide film 284 in this portion may not be removed. Good.

Next, as shown in FIG. 26, a trench 272 that penetrates into the deep part of the semiconductor substrate 270 is formed from the semiconductor substrate 270 exposed on the bottom surface of the group of recesses 222 by wet etching using an alkaline solution. The trench 272 may remain in the semiconductor substrate 270 or may penetrate the semiconductor substrate 270, as shown in FIG. As a method for forming the trench 272, for example, an RIE method or the like may be used in addition to wet etching using an alkaline solution.
Next, as shown in FIG. 27, the trench 272 is expanded by performing isotropic etching from the side surface of the semiconductor substrate 270 defining the trench 272. Specifically, isotropic etching can be performed from the side surface defining the trench 272 by using a chemical dry etching (CDE) method. In this isotropic etching, since the second CVD oxide film 284 is formed on the side surface of the recess 222, the width of the recess 222 is maintained. On the other hand, the width of the trench 272 expands. Therefore, the shape of the recess 222 (which constitutes the thin layer through hole 222 of the stencil mask 300) is maintained. As a method of performing isotropic etching from the side surface defining the trench 272, isotropic etching can be performed by injecting an alkaline aqueous solution into the trench 272 in addition to chemical dry etching.
Next, as shown in FIG. 28, polishing is performed from the back surface of the semiconductor substrate 270 until the trench 272 is exposed. Through this stage, the thick layer wall 232 and the surrounding thick layer wall 234 are formed. Note that, when the trench 272 is formed, if the semiconductor substrate 270 is formed so as to penetrate, this polishing step can be omitted.
Finally, the second CVD oxide film 284 remaining on the side surface defining the recess 222 is removed using hydrofluoric acid (HF), buffered hydrofluoric acid (BHF), or the like, thereby removing the second CVD oxide film 284 shown in FIG. The stencil mask 300 shown in FIG.

(Modification)
In FIG. 29, the longitudinal cross-sectional view of the stencil mask 400 is typically shown.
The stencil mask 400 is an example in which the thick layer wall 332 and the surrounding thick layer wall 334 are formed by two members a and b. In the stencil mask 400 as well, the fine thin layer through-hole 322 can be obtained by the thin layer portion 425 having a small thickness, as in the above embodiments. Further, the thin layer portion wall 424 having a small thickness can sufficiently secure the passing amount of ionized atoms when passing through the thin layer through hole 322. Further, a sufficient amount of ionized atoms can be secured when passing through the thick layer through-hole 338 of the thick layer portion 335. Furthermore, by providing the thick layer wall 332, the heat of the thin layer wall 424 can be effectively radiated to the outside.
Furthermore, when the structure of the stencil mask 400 is adopted, the heat dissipation and mechanical rigidity of the two members a and b of the thick layer wall 332 and the surrounding thick layer wall 334 are adjusted. And a stencil mask each having a desired balance of ion atom permeability.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

The perspective view of the stencil mask of 1st Example is shown. The enlarged perspective view of the principal part of the stencil mask of 1st Example is shown. The longitudinal cross-sectional view of the stencil mask of 1st Example is typically shown. The structure of an ion implantation apparatus is shown. The distribution of ionized atoms passing through the through holes of the stencil mask is shown. The manufacturing process of the stencil mask of 1st Example is shown (1). The manufacturing process of the stencil mask of 1st Example is shown (2). The manufacturing process of the stencil mask of 1st Example is shown (3). The manufacturing process of the stencil mask of 1st Example is shown (4). The manufacturing process of the stencil mask of 1st Example is shown (5). The manufacturing process of the stencil mask of 1st Example is shown (6). The manufacturing process of the stencil mask of 1st Example is shown (7). The manufacturing process of the electric field etching of 1st Example is shown. The longitudinal cross-sectional view of the stencil mask of 2nd Example is shown typically. The manufacturing process of the stencil mask of 1st Example is shown (1). The manufacturing process of the stencil mask of 1st Example is shown (2). The manufacturing process of the stencil mask of 1st Example is shown (3). The manufacturing process of the stencil mask of 1st Example is shown (4). The manufacturing process of the stencil mask of 1st Example is shown (5). The longitudinal cross-sectional view of the stencil mask of 3rd Example is typically shown. The manufacturing process of the stencil mask of 1st Example is shown (1). The manufacturing process of the stencil mask of 1st Example is shown (2). The manufacturing process of the stencil mask of 1st Example is shown (3). The manufacturing process of the stencil mask of 1st Example is shown (4). The manufacturing process of the stencil mask of 1st Example is shown (5). The manufacturing process of the stencil mask of 1st Example is shown (6). The manufacturing process of the stencil mask of 1st Example is shown (7). The manufacturing process of the stencil mask of 1st Example is shown (8). The longitudinal cross-sectional view of the other modification of a stencil mask is shown typically.

Explanation of symbols

14: entrance surface 16: exit surface 20: semiconductor thin layer 22: thin layer through hole 24: thin layer wall 25: thin layer portion 26: surrounding thin layer wall 30: semiconductor thick layer 32: thick layer wall 34: Surrounding thick layer wall 35 Thick layer portion 38: Thick layer through hole 82: Cooling device

Claims (14)

A thin layer,
It has a thick layer part laminated on one side of the thin layer part,
A plurality of narrow thin layer through holes are formed in the thin layer part,
In the thick layer portion, a plurality of wide thick layer through holes are formed,
The thin layer through hole of the thin layer part and the thick layer through hole of the thick layer part are in communication with each other in pairs.
A stencil mask, wherein a step is formed between a side surface of a thin layer portion defining a thin layer through hole and a side surface of a thick layer portion defining a thick layer through hole. A thin layer,
It has a thick layer part laminated on one side of the thin layer part,
A plurality of thin layer through holes are formed in the thin layer portion,
A plurality of thick layer through holes are formed in the thick layer portion,
The wall located between the thin layer through hole penetrating the thin layer part is wide and located between the thick layer through hole penetrating the thick layer part and the thick layer through hole. The wall is narrow,
The wall located between the thin layer through hole and the thin layer through hole penetrating the thin layer part has a wall located between the thick layer through hole and the thick layer through hole penetrating the thick layer part. Laminated,
A stencil mask, wherein a step is formed between a side surface of a thin layer portion defining a thin layer through hole and a side surface of a thick layer portion defining a thick layer through hole.   The stencil mask according to claim 1 or 2, wherein a side surface of the thick layer portion defining the thick layer through hole extends in a direction substantially perpendicular to the one surface of the thin layer portion.   4. The stencil mask according to claim 1, wherein the thin layer portion is a semiconductor layer containing a first conductivity type impurity and the thick layer portion is a semiconductor layer containing a second conductivity type impurity.   The stencil mask according to any one of claims 1 to 3, wherein the thin layer portion and the thick layer portion are formed in a semiconductor layer having a continuous crystal structure.   6. The stencil mask according to claim 4, wherein the semiconductor layer is formed of a silicon single crystal layer.   The stencil mask according to any one of claims 1 to 6, wherein an encircling wall that goes around the periphery of the thick layer through hole group is formed in the thick layer portion.   The stencil mask according to claim 7, wherein the surrounding wall is connected to a cooling means.   The height in the stacking direction of the surrounding wall is equal to the height in the stacking direction of the wall located between the thick layer through hole penetrating the thick layer portion and the thick layer through hole. 8 stencil mask. An ion implantation apparatus using the stencil mask according to claim 1,
Ion generating means for generating ions;
A mass spectrometric means for selecting necessary ions from the generated ions;
Accelerating means for accelerating selected ions;
An injection chamber in which a substrate to be processed is disposed;
An ion implantation apparatus comprising a stencil mask provided between an acceleration means and a substrate to be processed.   A method for using a stencil mask, wherein the stencil mask according to any one of claims 1 to 9 is placed on a surface of a substrate to be processed, and charged particles or electromagnetic waves are irradiated to the surface of the substrate to be processed through the stencil mask. A plurality of thin layer penetrations penetrating through the semiconductor thin layer by etching from the exposed surface of the semiconductor thin layer side of the semiconductor substrate in which the semiconductor thick layer containing the second conductivity type impurity is laminated on the semiconductor thin layer containing the first conductivity type impurity Forming a hole;
Etching from an exposed surface on the semiconductor thick layer side to form a plurality of thick layer through holes penetrating the semiconductor thick layer,
When viewed in plan, the semiconductor thick layer is etched at a position corresponding to the thin layer through hole penetrating the semiconductor thin layer, the thin layer through hole is etched narrowly, the thick layer through hole is etched wide, and the thin layer A method of manufacturing a stencil mask, comprising forming a step between a side surface of a semiconductor thin layer defining a through hole and a side surface of a semiconductor thick layer defining a thick layer through hole. The surface orientation of the exposed surface of the semiconductor thick layer is selected as (211),
A semiconductor thin layer is obtained by performing wet etching using an alkaline solution from an exposed surface of the semiconductor thick layer in a state where a voltage at which the semiconductor thin layer and the semiconductor thick layer are reverse-biased is applied between the semiconductor thin layer and the semiconductor thick layer. The manufacturing method according to claim 12, wherein a plurality of thick layer through holes reaching the layer are formed. Forming a plurality of shallow recesses penetrating the semiconductor substrate from the surface of the semiconductor substrate;
Forming a mask material on the side surface of the semiconductor substrate that defines the recessed group; and
Forming a trench that penetrates deeply into the deep portion of the semiconductor substrate from the semiconductor substrate exposed at the bottom surface of the recess group by anisotropic etching;
A method for producing a stencil mask, comprising a step of expanding a side surface of a semiconductor substrate defining the trench by isotropic etching.

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