CN112903800B - Semiconductor structure analysis method - Google Patents
Semiconductor structure analysis method Download PDFInfo
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- CN112903800B CN112903800B CN202110105536.XA CN202110105536A CN112903800B CN 112903800 B CN112903800 B CN 112903800B CN 202110105536 A CN202110105536 A CN 202110105536A CN 112903800 B CN112903800 B CN 112903800B
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- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
- G01N27/62—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating the ionisation of gases, e.g. aerosols; by investigating electric discharges, e.g. emission of cathode
Abstract
The invention provides a semiconductor structure analysis method, which comprises the following steps: providing a substrate on an insulator, wherein the substrate comprises an upper semiconductor layer, a lower semiconductor layer and an oxide layer positioned between the upper semiconductor layer and the lower semiconductor layer; forming a test block on the surface of the upper semiconductor layer; etching the test block to form an etching groove, wherein the etching groove penetrates through the upper semiconductor layer and the oxide layer; filling a conductive medium into the etching groove to form a conductive path; and analyzing the test block by using a secondary ion mass spectrometry method. So configured, the etching groove is filled with a conductive medium to form a conductive path so as to connect the upper semiconductor layer and the lower semiconductor layer, thereby eliminating an electric field formed by enriching a large amount of positive charges in the test block, and enabling secondary ions to be normally deflected to the receiver when secondary ion mass spectrometry is carried out. Further, by studying the secondary ion signal spectra of the test block and the substrate, the location of the oxide layer in the substrate and the thickness of the oxide layer can be approximately determined.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure analysis method.
Background
The secondary ion mass spectrum is a high-sensitivity and high-resolution surface analysis instrument and is an indispensable tool in the manufacturing and research and development stages of semiconductor integrated circuits. In the semiconductor manufacturing process of 28/22/14/12nm and other nodes, trace doping SiGe and SiP in the material can have great influence on the characteristics of applied devices, and the prior art generally adopts secondary ion mass spectrometry to study the distribution of ultra-shallow implantation and ultra-thin layer impurity Ge/B/P elements.
For the process products such as LP/HKMG/FinFET, as shown in fig. 1a, fig. 1a is a schematic diagram of a conventional secondary ion mass spectrometry, where secondary ions sputtered from a substrate are biased toward a secondary ion receiver 02 by adjusting a voltage 01 applied to the substrate to a target value, so as to complete the secondary ion mass spectrometry.
As shown in fig. 1b to 1d, fig. 1b is a schematic diagram of a conventional FDSOI structure, fig. 1c is a front view of the FDSOI structure, and fig. 1d is a top view of the FDSOI structure, where FDSOI (fully depleted silicon on insulator) forms an oxide layer 03 on a silicon substrate compared to LP/HKMG/FinFET and other process products. In addition, a test area 04 is formed on the surface of the silicon substrate, as shown in fig. 1e, fig. 1e is a schematic diagram of a secondary ion mass spectrometry of an FDSOI structure, and a primary ion beam is continuously injected into the test area to bring a large amount of positive charges to the silicon substrate, so that the surface of the silicon substrate is enriched with a large amount of positive charges due to the non-conduction of the oxide layer 03, thereby forming an electric field, and the sputtered secondary ions deviate from the secondary ion receiver 02 under the action of the electric field, so that the secondary ion mass spectrometry cannot be performed.
Disclosure of Invention
The invention aims to provide a semiconductor structure analysis method for solving the problem that the conventional FDSOI product cannot be subjected to secondary ion mass spectrometry.
In order to solve the above technical problems, the present invention provides a semiconductor structure analysis method, which includes:
providing a substrate on an insulator, wherein the substrate comprises an upper semiconductor layer, a lower semiconductor layer and an oxide layer positioned between the upper semiconductor layer and the lower semiconductor layer; forming a test block on the surface of the upper semiconductor layer;
etching the test block to form an etching groove, wherein the etching groove penetrates through the upper semiconductor layer and the oxide layer;
filling a conductive medium into the etching groove to form a conductive path; and
and analyzing the test block by using a secondary ion mass spectrometry method.
Optionally, etching the test block to form at least four etching grooves.
Optionally, at least four of the etching grooves are configured to be distributed along the circumference of the test block.
Optionally, the step of etching the test block to form an etched trench includes: the test block is etched using a focused ion beam process.
Optionally, the step of filling the etched trench with a conductive medium to form a conductive path includes: and filling the conductive medium into the etching groove by utilizing a focused ion beam process.
Optionally, the step of analyzing the test block by using a secondary ion mass spectrometry method includes:
bombarding the test block by using a primary ion beam to sputter a secondary ion beam from the surface of the test block;
and receiving the secondary ion beam by using a detector, and performing secondary ion mass spectrometry.
Optionally, before bombarding the test block with the primary ion beam, the step of analyzing the test block with a secondary ion mass spectrometry method further comprises; and loading a power supply to the substrate, and regulating the voltage of the power supply to a preset value.
Optionally, one end of the power supply is grounded.
Optionally, the conductive medium comprises at least one of platinum and tungsten.
Optionally, the substrate comprises a fully depleted silicon-on-insulator substrate.
In summary, the semiconductor structure analysis method provided by the invention includes: providing a substrate on an insulator, wherein the substrate comprises an upper semiconductor layer, a lower semiconductor layer and an oxide layer positioned between the upper semiconductor layer and the lower semiconductor layer; forming a test block on the surface of the upper semiconductor layer; etching the test block to form an etching groove, wherein the etching groove penetrates through the upper semiconductor layer and the oxide layer; filling a conductive medium into the etching groove to form a conductive path; and analyzing the test block by using a secondary ion mass spectrometry method. And forming an etching groove by etching the test block of the upper semiconductor layer, enabling the etching groove to penetrate through the upper semiconductor layer and the oxide layer, filling a conductive medium in the etching groove to form a conductive path so as to connect the upper semiconductor layer and the lower semiconductor layer, eliminating an electric field formed by enriching a large amount of positive charges in the test block, and enabling secondary ions to normally deflect to a receiver when performing secondary ion mass spectrometry so as to perform secondary ion mass spectrometry. Further, by studying the secondary ion signal spectra of the test block and the substrate, the location of the oxide layer in the substrate and the thickness of the oxide layer can be approximately determined.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation on the scope of the invention. Wherein:
FIG. 1a is a schematic diagram of a prior art secondary ion mass spectrometry;
FIG. 1b is a schematic diagram of a prior art FDSOI structure;
FIG. 1c is a front view of a prior art FDSOI structure;
FIG. 1d is a top view of a prior art FDSOI structure;
FIG. 1e is a schematic diagram of a secondary ion mass spectrometry of an FDSOI structure;
FIG. 2a is a schematic diagram of a test block and a substrate according to an embodiment of the invention;
FIG. 2b is a front view of a test block and substrate according to one embodiment of the present invention;
FIG. 2c is a top view of a test block and substrate according to one embodiment of the present invention;
FIG. 2d is a schematic diagram of an etching tank according to an embodiment of the invention;
FIG. 2e is a schematic diagram of a conductive path according to an embodiment of the present invention;
FIG. 2f is a diagram illustrating an etch bath according to one embodiment of the present invention;
FIG. 2g is a schematic representation of a secondary ion mass spectrometry of a test block and substrate according to an embodiment of the present invention;
FIG. 2h is a signal spectrum of a secondary ion mass spectrometry of a test block and substrate according to an embodiment of the present invention.
In the accompanying drawings:
01-voltage; 02-a secondary ion receiver; 03-an oxide layer; 04-test area;
10-substrate; 11-an upper semiconductor layer; 111-test blocks; 112-etching a groove; 113-conductive vias; 12-a lower semiconductor layer; 13-an oxide layer; 20-a detector; 30-power supply.
Detailed Description
The invention will be described in further detail with reference to the drawings and the specific embodiments thereof in order to make the objects, advantages and features of the invention more apparent. It should be noted that the drawings are in a very simplified form and are not drawn to scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments.
As used in this disclosure, the singular forms "a," "an," and "the" include plural referents, the term "or" are generally used in the sense of comprising "and/or" and the term "several" are generally used in the sense of comprising "at least one," the term "at least two" are generally used in the sense of comprising "two or more," and the term "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying any relative importance or number of features indicated. Thus, a feature defining "a first", "a second", and "a third" may include one or at least two of the feature, either explicitly or implicitly, unless the context clearly dictates otherwise.
The invention provides a semiconductor structure analysis method, which aims to solve the problem that the conventional FDSOI product cannot be subjected to secondary ion mass spectrometry.
The following description refers to the accompanying drawings.
As shown in fig. 2 a-2 c, fig. 2a is a schematic diagram of a test block and a substrate according to an embodiment of the present invention, fig. 2b is a front view of the test block and the substrate according to an embodiment of the present invention, and fig. 2c is a top view of the test block and the substrate according to an embodiment of the present invention, the embodiment provides a substrate 10 on an insulator, the substrate 10 includes an upper semiconductor layer 11, a lower semiconductor layer 12, and an oxide layer 13 between the upper semiconductor layer 11 and the lower semiconductor layer 12; a test block 111 is formed on the surface of the upper semiconductor layer 11; the substrate 10 on the insulator in this embodiment is specifically a fully depleted silicon substrate 10, and the oxide layer 13 (specifically a silicon dioxide layer) located in the middle layer is insulated and isolates the upper semiconductor layer 11 from the lower semiconductor layer 12.
As shown in fig. 2d, fig. 2d is a schematic diagram of an etching groove according to an embodiment of the invention, the test block 111 is etched to form an etching groove 112, and the etching groove 112 penetrates the upper semiconductor layer 11 and the oxide layer 13.
As shown in fig. 2e, fig. 2e is a schematic diagram of a conductive path according to an embodiment of the present invention, where the etched trench 112 is filled with a conductive medium to form a conductive path 113; optionally, the conductive medium is at least one of platinum and tungsten, and of course, other materials for conducting electricity, such as copper and gold, are also possible.
As shown in fig. 2g, fig. 2g is a schematic diagram of a secondary ion mass spectrometry of a test block and a substrate according to an embodiment of the present invention, where the test block 111 is analyzed by a secondary ion mass spectrometry method, and of course, elements in the substrate 10 may also be analyzed.
In the above-described semiconductor structure analysis method, the etching groove 112 is formed by etching the test block 111, and the etching groove 112 penetrates through the upper semiconductor layer 11 and the oxide layer 13, and the conductive medium is filled in the etching groove 112 to form the conductive path 113, so that the upper semiconductor layer 11 and the lower semiconductor layer 12 can be connected through the conductive path 113, and when performing secondary ion mass spectrometry, a large amount of positive charges brought by the primary ion beam to the surface of the test block 111 can be introduced into the lower semiconductor layer 12 through the conductive path 113, thereby eliminating a surface electric field formed by the large amount of positive charges, and the secondary ions sputtered from the surface of the test block 111 can be normally deflected to the secondary ion receiver (detector 20), thereby performing secondary ion mass spectrometry.
Referring to fig. 2f, fig. 2f is a layout diagram of etching grooves according to an embodiment of the present invention, optionally, the test block 111 is etched to form at least four etching grooves 112 (four etching grooves 112 are shown in fig. 2 f). Further, at least four of the etching grooves 112 are arranged to be distributed along the circumferential direction of the test block 111. In this embodiment, the top view of the test block 111 is rectangular, and four etching grooves 112 are respectively located at four corners of the rectangle. The shape of the test block 111 is not particularly limited in the present invention, and may be any shape such as a circle, a polygon, an ellipse, … …. It should be noted that the shape of the etching groove 112 is not limited in the present invention, and the shape of the etching groove may be similar to that of the test block 111, for example, the cross section of the etching groove is rectangular or circular … …; in addition, the extending direction of the etching groove 112 (the direction from the upper semiconductor layer 11 to the lower semiconductor layer 12) is not limited to be perpendicular to the upper semiconductor layer 11, and may be inclined (for example, inclined at 60 ° or 45 °) to the upper semiconductor layer 11.
Further, the step of etching the test block 111 to form an etched trench 112 includes: the test block 111 is etched using a focused ion beam process.
Further, the step of filling the etched trench 112 with a conductive medium to form a conductive via 113 includes: the conductive medium is filled into the etch tank 112 using a focused ion beam process.
A Focused Ion Beam (FIB) system is a micromachining instrument that focuses an Ion beam into a very small size using an electric lens. The stripping, deposition, injection and modification of the material are realized by the bombardment of the surface of the material by charge energy ions. The basic functions of a focused ion beam microscope can be broadly divided into four types: (1) fixed point cutting (precision cutting): the physical collision of ions is used to achieve the purpose of cutting. Is widely used for processing and analyzing Cross Section (Cross Section) of Integrated Circuits (ICs) and LCDs. (2) selective material evaporation (Selective Deposition): the deposition of metal and oxide layers (Metal and TEOS Deposition) can be provided by decomposing an organometallic vapor or vapor phase insulating material with the energy of an ion beam, either conductive or nonconductive, in localized areas, with common metal depositions of both Platinum (Pt) and tungsten (tunestun, W). (3) Enhanced Etching or selective Etching (Enhanced Etching-Iodine/Selective Etching-XeF 2): assisted by corrosive gases, to accelerate the efficiency of the cut or selective material removal. (4) etch endpoint detection (End Point Detection): the signal of the secondary ion is detected to know the progress of the dicing or etching. In this embodiment, the conductive medium is filled into the etching groove 112 by using the (2) th function of the focused ion beam, and the etching groove 112 is formed by etching the test block 111 by using the (3) th function of the focused ion beam.
Further, the step of analyzing the test block 111 and the substrate 10 by using the secondary ion mass spectrometry method includes:
using a primary ion beam (O) 2 The test block 111 is bombarded, so that the surface of the test block 111 is sputtered with a secondary ion beam (Ge+/P+);
the secondary ion beam is received by detector 20 for secondary ion mass spectrometry.
It should be understood that the principle of secondary ion mass spectrometry is: when the surface of the test block 111 is bombarded by the high-energy focused primary ion beam, the primary ion beam is injected into the test block 111, kinetic energy is transferred to solid atoms, neutral particles and secondary ion beams with positive and negative charges are sputtered through cascade collision, and element distribution characteristics of the test block 111 and the substrate 10 are analyzed according to mass signals of the sputtered secondary ion beams.
Further, the step of analyzing the test block 111 and the substrate 10 by using a secondary ion mass spectrometry method before bombarding the test block 111 with the primary ion beam further comprises; the power supply 30 is applied to the substrate 10, and the voltage of the power supply 30 is adjusted to a predetermined value. Still further, one end of the power supply 30 is grounded. So configured, the electric field of the substrate 10 can be directed toward the lower semiconductor layer 12 and toward the upper semiconductor layer 11 to properly deflect the sputtered secondary ion beam toward the secondary ion receiver (detector 20). Further, the predetermined value of the voltage is set according to the actual situation.
Further, referring to fig. 2h, fig. 2h is a signal spectrum diagram of a secondary ion mass spectrometry of the test block 111 and the substrate 10 according to an embodiment of the present invention, in which an X-axis represents a depth (in nm) in a direction from the surface of the test block 11 to the lower semiconductor layer 12, a Y-axis represents a concentration of each element, typically, the material of the test block 111 is SiGe (silicon-germanium) and is doped with B (boron), the material of the upper semiconductor layer 11 and the lower semiconductor layer 12 is silicon, and it is understood that the concentrations of each element refer to concentration ratios (i.e., percentages) for Ge and Si, and the sum of the concentrations is 100%; the term "B" means its concentration (i.e., the number of atoms per unit volume). As shown in fig. 2h, when the oxide layer 13 (i.e. the silicon dioxide layer) is tested, the effect of the focused ion beam process for assisting in conduction fails, the surface of the tested region (specifically, the silicon dioxide layer) is enriched with positive charges again, the sputtered secondary ion beam cannot reach the detector, the content of the B element is suddenly reduced at X1, after the oxide layer 13 is finished, the content of the B element is suddenly increased at X2 due to the abrupt change of the material of the surface of the tested region (i.e. the lower semiconductor layer 12 is reached), and then the curve is restored to be normal, so that it can be determined that the thickness of the oxide layer 13 is approximately (X2-X1) nm, and the depth of the oxide layer 13 in the substrate is approximately X1 nm. It should be noted that, in fig. 2h, the depth of the substrate 10 is only 40nm, and it should be understood that the depth of the substrate 10 is greater than 40nm.
In summary, the semiconductor structure analysis method provided by the invention includes: providing a substrate on an insulator, wherein the substrate comprises an upper semiconductor layer, a lower semiconductor layer and an oxide layer positioned between the upper semiconductor layer and the lower semiconductor layer; forming a test block on the surface of the upper semiconductor layer; etching the test block to form an etching groove, wherein the etching groove penetrates through the upper semiconductor layer and the oxide layer; filling a conductive medium into the etching groove to form a conductive path; and analyzing the test block and the substrate by using a secondary ion mass spectrometry method. And forming an etching groove by etching the test block of the upper semiconductor layer, enabling the etching groove to penetrate through the upper semiconductor layer and the oxide layer, filling a conductive medium in the etching groove to form a conductive path so as to connect the upper semiconductor layer and the lower semiconductor layer, eliminating an electric field formed by enriching a large amount of positive charges in the test block, and enabling secondary ions to normally deflect to a receiver when performing secondary ion mass spectrometry so as to perform secondary ion mass spectrometry. Further, by studying the secondary ion signal spectra of the test block and the substrate, the location of the oxide layer in the substrate and the thickness of the oxide layer can be approximately determined.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (10)
1. A method of analyzing a semiconductor structure, comprising:
providing a substrate on an insulator, wherein the substrate comprises an upper semiconductor layer, a lower semiconductor layer and an oxide layer positioned between the upper semiconductor layer and the lower semiconductor layer; forming a test block on the surface of the upper semiconductor;
etching the test block to form an etching groove, wherein the etching groove penetrates through the upper semiconductor layer and the oxide layer;
filling a conductive medium into the etching groove to form a conductive path; and
and analyzing the test block by using a secondary ion mass spectrometry method.
2. The method of claim 1, wherein the test block is etched to form at least four of the etched trenches.
3. The semiconductor structure analysis method according to claim 2, wherein at least four of the etching grooves are arranged to be distributed along a circumferential direction of the test block.
4. The method of claim 1, wherein etching the test block to form an etched trench comprises: the test block is etched using a focused ion beam process.
5. The method of claim 1, wherein the step of filling the etched trenches with a conductive medium to form conductive paths comprises: and filling the conductive medium into the etching groove by utilizing a focused ion beam process.
6. The method of claim 1, wherein analyzing the test block using a secondary ion mass spectrometry method comprises:
bombarding the test block by using a primary ion beam to sputter a secondary ion beam from the surface of the test block;
and receiving the secondary ion beam by using a detector, and performing secondary ion mass spectrometry.
7. The method of claim 6, wherein analyzing the test block with a secondary ion mass spectrometry method before bombarding the test block with a primary ion beam further comprises; and loading a power supply to the substrate, and regulating the voltage of the power supply to a preset value.
8. The method of claim 7, wherein one end of the power supply is grounded.
9. The semiconductor structure analysis method according to claim 1, wherein the conductive medium comprises at least one of platinum and tungsten.
10. The method of claim 1, wherein the substrate comprises a fully depleted silicon-on-insulator substrate.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102386071A (en) * | 2010-08-25 | 2012-03-21 | 株式会社半导体能源研究所 | Electronic device, manufacturing method of electronic device, and sputtering target |
| CN110211947A (en) * | 2019-06-10 | 2019-09-06 | 武汉新芯集成电路制造有限公司 | The forming method of semi-conductor test structure |
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| CA2031254A1 (en) * | 1989-12-01 | 1991-06-02 | Kenji Aoki | Doping method of barrier region in semiconductor device |
| US7002175B1 (en) * | 2004-10-08 | 2006-02-21 | Agency For Science, Technology And Research | Method of making resonant tunneling diodes and CMOS backend-process-compatible three dimensional (3-D) integration |
| KR20120020526A (en) * | 2010-08-30 | 2012-03-08 | 삼성전자주식회사 | Substrate have buried conductive layer and formation method thereof, and fabricating method of semiconductor device using the same |
| CN103137511B (en) * | 2011-11-25 | 2016-01-06 | 中芯国际集成电路制造(上海)有限公司 | The method of testing of silicon through hole test structure and correspondence |
| CN106290544B (en) * | 2015-05-22 | 2019-04-16 | 中芯国际集成电路制造(上海)有限公司 | A kind of SIMS analysis method |
| CN107316856B (en) * | 2016-04-26 | 2020-02-07 | 中芯国际集成电路制造(上海)有限公司 | Structure for detecting ion implantation abnormality, method for manufacturing same, and method for detecting ion implantation abnormality |
| CN112038225A (en) * | 2020-08-06 | 2020-12-04 | 上海华力集成电路制造有限公司 | Method for forming gate oxide |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102386071A (en) * | 2010-08-25 | 2012-03-21 | 株式会社半导体能源研究所 | Electronic device, manufacturing method of electronic device, and sputtering target |
| CN110211947A (en) * | 2019-06-10 | 2019-09-06 | 武汉新芯集成电路制造有限公司 | The forming method of semi-conductor test structure |
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