JPH10284378A - Alignment mark and electron beam exposing mask employing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure of a rear alignment mark in which a silicon oxide layer is not destructed even if the rear alignment mark is etched under such etching conditions as a supporting frame part and an opening are made therein, and an electron beam exposing mask employing it. SOLUTION: The alignment mark comprises a combination of rectangular patterns each having a side arranged in parallel with or perpendicular to the orientation flat of a silicon wafer having an orientation of the (100) plane. A rear alignment mask 49 is formed by wet etching a rear silicon wafer 41 using protective film patterns 47a, 47b as a mask. Since etching proceeds in the direction normal to the silicon wafer but does not proceed easily in the lateral direction, inclining faces 50 are formed on the opposite sides of the rear alignment mask 49 through etching and the etching is stopped at the position where the inclining faces 50 meet each other thus producing electron beam exposing mask which does not penetrate the rear silicon wafer 41.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an alignment mark used for alignment between a front surface and a back surface pattern when manufacturing an electron beam exposure mask of an electron beam exposure apparatus used in a manufacturing process of a semiconductor device such as an IC or an LSI. The present invention relates to an electron beam exposure mask using the same.

[0002]

2. Description of the Related Art The electron beam exposure method is an exposure technique capable of exposing a pattern having a width of 0.1 μm, and is an effective exposure technique for manufacturing semiconductors such as ICs and LSIs. For electron beam exposure, an electron beam exposure mask having a fine opening pattern formed on a silicon wafer is used. FIG. 6 shows a manufacturing process of the electron beam exposure mask. A resist pattern 64 is formed on the front side silicon wafer 63 of the SOI wafer 60 where two silicon wafers are bonded, and the front side silicon wafer 63 is etched by dry etching to form an opening pattern 65.
To form Next, the protective film 6 is formed on the backside silicon wafer 61.
6, and the protective film 66 is patterned to form a protective film pattern 66a. Next, the protective film pattern 66
The back side silicon wafer 61 is wet-etched using a as a mask to form the support frame 61 a and the opening 67. Further, the silicon oxide layer 62 of the bonding layer is removed by using the support frame 61a as a mask to manufacture an electron beam exposure mask.

The thicknesses of the front silicon wafer 63, the bonded silicon oxide layer 62 and the back silicon wafer 61 are generally about 20 microns, 1 micron and 500 microns, respectively. When forming the protective film pattern 66a on the backside silicon wafer 61, the backside alignment mark is formed by aligning it with the position corresponding to the front side alignment mark.

The alignment of the alignment marks is performed using a microscope, but the entire size is about 1 to 3 mm square in order to easily find the pattern position. The pattern line width for forming the alignment mark is about 10 to 50 microns. As the wet etching liquid for the backside silicon wafer, an alkaline liquid such as a NaOH liquid or a KOH liquid is heated and used. SOI wafers usually have a plane orientation (10
A wafer obtained by bonding silicon wafers consisting of 0) is used.

FIG. 7A shows a conventional back side alignment mark pattern, FIG. 7B shows a shape of the back side alignment mark after etching the conventional back side alignment mark pattern, and FIG. 8 shows a front side alignment mark.
When the backside silicon wafer 61 is wet-etched with a hot alkaline solution using the protective film pattern 66a as a mask, the backside alignment mark pattern is also etched at the same time. Therefore, etching starts from the etched portions 71 and 72 of the back side alignment mark pattern.

Usually, the alignment mark is formed in parallel with the orientation flat. Further, since the silicon wafer of the SOI wafer is usually a silicon wafer having a plane orientation (100), the sides perpendicular and parallel to the orientation flat are etched slowly and the shape is maintained, but have an angle with these sides. Plane orientation (21
In the directions 1) and the like (here, the four corners of the remaining portion of the back side alignment mark pattern), since the wet etching rate is high (Si micromachining advanced technology pages 111 to 145, published by Science Forum Co., Ltd., March 31, 1992) Progressing rapidly, the etched portions 71 and 72 of the backside alignment mark pattern
In FIG. 7B, the opening becomes large as shown by 71a and 72a in FIG. 7B, and the etching proceeds in the cross-sectional direction of the wafer and eventually penetrates.

Usually, since the electron beam exposure pattern formed on the front silicon wafer has a small pattern width, even if the back silicon wafer is wet-etched to form an opening, it is etched with the silicon oxide layer which is a bonding layer of the SOI wafer. Stops.

However, the alignment mark formed on the backside silicon wafer has a pattern width of 10 to 50 microns. The plane orientation (10) as shown in FIG.
0) Backside alignment mark 71 having a side parallel to the plane
The etching of the straight portions 72 and 72 proceeds only in the direction perpendicular to the wafer. However, since the four corners of the inner rectangular remaining portion 73 where the alignment marks 71 and 72 intersect have a plane such as the plane orientation (211), the etching proceeds in the horizontal direction, and the area to be etched is reduced. At the time when the rear silicon wafer penetrates, the rectangular remaining portion 73 becomes an octagonal shape as shown by 73a in FIG. 7B. Further, in the alignment mark portion, since the entire size of the mark is as large as 1 to 3 mm, the silicon oxide layer in the alignment mark portion is destroyed, and the etching solution flows to the front side silicon wafer surface.

[0009]

As described above, in the conventional alignment mark, when the backside alignment mark is formed, wet etching does not stop at the silicon oxide layer when the backside silicon wafer is etched, and the silicon oxide layer is broken and the front side is destroyed. The etchant flows around the silicon wafer surface. For this reason, the etchant stains the front side pattern,
In a severe case, there is a problem that the pattern is destroyed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem. When forming an alignment mark of an electron beam exposure mask, the back side silicon wafer for forming a support frame and an opening is formed under the same wet etching conditions as a back side silicon wafer. An object of the present invention is to provide an alignment mark in which a silicon oxide layer is not destroyed even when the alignment mark is etched, and an electron beam exposure mask using the alignment mark.

[0011]

In order to solve the above-mentioned problems, according to the present invention, first, a front side pattern and a back side formed on a front side silicon wafer of an SOI wafer in which two silicon wafers are bonded are described. An electron beam exposure mask having an alignment mark for aligning a backside pattern formed on a silicon wafer, wherein the alignment mark is formed by a combination of rectangular patterns.

According to a second aspect of the present invention, the front side silicon wafer and the back side silicon wafer of the SOI wafer have a plane orientation of (100), and the rectangular pattern forming the alignment mark is oriented with respect to an orientation flat. The alignment mark according to claim 1, wherein the alignment mark is arranged in parallel or at a right angle.

According to a third aspect of the present invention, the line width w of the rectangular pattern satisfies a condition of w <1.4t with respect to the thickness t of the backside silicon wafer. An alignment mark according to item 2.

According to a fourth aspect of the present invention, there is provided an electron beam exposure mask manufactured using the alignment mark according to any one of the first to third aspects.

In the alignment mark of the present invention, the etched portion of the alignment mark is formed in a rectangular pattern to prevent the etching in the direction such as the plane direction (211) from proceeding. For this reason, it is possible to prevent the back etchant from penetrating through the back side silicon wafer and circling to the front side silicon wafer to stain or damage the front side pattern.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The contents of the present invention will be described below in more detail. 1 and 2 are explanatory views showing an embodiment of the alignment mark pattern of the present invention. FIG. 3 (a)
FIG. 3 is a plan view showing an embodiment in which an alignment mark of the present invention is formed on an SOI wafer. FIG. 3B is a plan view showing an embodiment in which the alignment mark of the present invention is formed on an electron beam exposure mask. FIGS. 4A to 4F are cross-sectional views showing steps of manufacturing an electron beam exposure mask having an alignment mark according to the present invention. FIG. 5 is a partially enlarged sectional view showing an alignment mark portion of an electron beam exposure mask using the alignment mark of the present invention.

According to the present invention, in the manufacturing process of the electron beam exposure mask, S
Even if an alignment mark is formed on the backside silicon wafer under the same etching conditions as when the backside silicon wafer of the OI wafer is wet-etched to form the support frame and the opening, the silicon oxide layer as the bonding layer is destroyed. This is related to the configuration of alignment marks that are not used.

Specifically, the pattern configuration of the alignment mark of the present invention shown in FIGS. 1 and 2 was devised in consideration of the plane orientation of the silicon crystal plane and the wet etching property. The effect of the alignment mark of the present invention is remarkable when it is formed on the silicon wafer on the back side of the SOI wafer. S
Since the alignment marks on the front side silicon wafer of the OI wafer are produced under the conditions for forming a fine pattern, there is no particular limitation on the pattern configuration.

FIG. 3 (a) shows a case where alignment marks 33 for positioning are formed on an SOI wafer when an electron beam exposure mask is formed on multiple surfaces, and FIG. 3 shows a case where the alignment marks 33 are arranged on an electron beam exposure mask. (B).

The electron beam exposure mask having the alignment mark of the present invention is manufactured by the steps shown in FIGS. First, an SOI wafer 40 in which a front silicon wafer 41 and a back silicon wafer 43 are bonded together with a silicon oxide layer 42 is prepared (see FIG. 4A).

Next, the front silicon 4 of the SOI wafer 40
3, a photosensitive layer is formed, and is exposed and developed in a predetermined pattern to form a resist pattern 44 (see FIG. 4B).

Next, the front side silicon wafer 43 is dry-etched using the resist pattern 44 as a mask, and the resist pattern 44 is subjected to a film removing process to form an opening pattern 45 and a front side alignment mark 46. Further, a protection film 47 (such as a nitride film) for wet etching is formed on the backside silicon wafer 41 (see FIG. 4C).

Next, a resist pattern (not shown) for etching the protective film is formed on the protective film
Is patterned to form a protective film pattern 47a for forming an opening and a protective film pattern 47b for forming a backside alignment mark (see FIG. 4D).

Next, using the protective film patterns 47a and 47b as a mask resist, the backside silicon wafer 41 is etched with a hot alkali solution of potassium hydroxide to form the support frame 41a, the opening 48 and the backside alignment mark 4
9 (see FIG. 4E).

Next, the protective film patterns 47a and 47b are removed to obtain an electron beam exposure mask having the alignment mark of the present invention (see FIG. 4 (f)).

Here, the formation process will be described focusing on the alignment mark portion. FIG. 5 is an enlarged sectional view of the alignment mark portion of the electron beam exposure mask. The back side alignment mark 49 is arranged such that the pattern as shown in FIG. 1B or FIG. 2B is parallel or perpendicular to the orientation flat 34. When the back side silicon wafer 41 is wet-etched using the protective film pattern 47b as a mask, the etching proceeds in the direction perpendicular to the silicon wafer, but the etching in the plane direction (111) is slow, so that the etching does not easily proceed in the horizontal direction, so An inclined surface 50 having an etching angle θ is formed. The etching angle θ becomes approximately 54 degrees with the wafer surface, and when the two inclined surfaces 50 meet, the etching of the wafer in the vertical direction stops.

Since the angle between the wafer surface and the inclined surface 50 is about 54 degrees, when the etching depth is d and the width of the back side alignment mark is w, w = 1.4 × d. It is necessary that a sufficient thickness of the silicon wafer remain to maintain the strength when the etching stops after the two inclined surfaces 50 meet. When the etching residue of the back side silicon wafer 41 when the back side alignment mark is formed is r and the thickness of the back side silicon wafer is t, r = t−0.7w. The etching residue r of the backside silicon wafer 41 when the backside alignment mark is formed may be 20 μm or more, preferably 50 μm or more.
Here, when the thickness t of the backside silicon wafer 41 is 500 microns and the remaining thickness is 200 microns, the width w of the backside alignment mark is approximately 400 microns from the above equation.

Incidentally, since the electron beam exposure mask is produced by mounting the SOI wafer on multiple surfaces, the alignment mark of the present invention may be provided on the wafer, or may be provided on the imposed electron beam exposure mask. You may. Further, the wafer on which the electron beam exposure mask is manufactured is not limited to the SOI wafer, and the alignment mark of the present invention is also effective when a normal wafer is used.

[0029]

The present invention will be described in detail with reference to the following examples. <Example 1> Plasma CVD was performed on a front side silicon wafer 43 of an SOI wafer 40 (manufactured by Mitsubishi Materials) in which a back side silicon wafer 41 having a diameter of 4 inches and a thickness of 500 μm and a front side silicon wafer 43 having a thickness of 10 μm were bonded with a silicon oxide layer 42. A silicon oxide layer (not shown) having a thickness of 1 μm was formed by the method (see FIG. 4A).

Next, a resist (PMER: manufactured by Tokyo Ohka Co., Ltd.) is applied on the silicon oxide layer on the front side silicon wafer 43 to form a photosensitive layer, and a predetermined pattern is exposed and developed to form an opening pattern and a front side alignment. A resist pattern 44 for forming a mark was formed (see FIG. 4B). Here, the pattern shown in FIG. 1A was used for the front side alignment mark.

Next, the silicon oxide layer is first etched by reactive ion etching (RIE) using the resist pattern 44 as an etching mask, and the 10 μm thick front side silicon wafer 43 is etched using the silicon oxide layer as an etching mask. An opening pattern 45 and a front side alignment mark 46 were formed. Further, a silicon nitride film having a thickness of 0.4 μm was formed on the backside silicon wafer 41 by plasma CVD to form a protective film 47.
(C)).

Next, a resist was applied on the protective film 47 on the backside silicon wafer 41, a predetermined pattern was aligned with the front side alignment mark 46, and exposed and developed to form a resist pattern. Here, the pattern width is set to 4 using the back side alignment mark as shown in FIG.
It was set to 00 μm. Using this resist pattern as a mask, etching was performed by reactive ion etching (RIE) to form protective film patterns 47a and 47b (FIG. 4).
(D)).

Next, the backside silicon wafer 41 is wet-etched with a potassium hydroxide solution (15% by weight) heated to 90 ° C. using the protective film patterns 47a and 47b as a resist mask. The wafer 41 is etched so that the opening area reaches the silicon oxide layer 42, the opening 48 of the exposure mask, the support frame 41a.
And the back side alignment mark 49 is formed (FIG. 4).
(E)).

Subsequently, protective film patterns 47a and 47b
, And the silicon oxide layer 42 in the opening 48 was removed to obtain an electron beam exposure mask having an alignment mark of the present invention (see FIG. 4F). When the pattern width of the back side alignment mark was 400 μm, the remaining etching was almost 200 μm.

<Example 2> An electron beam exposure mask was manufactured in the same process as in Example 1 using the back side alignment mark pattern 22 in which square patterns each having a pattern width of 200 μm shown in FIG. 2B were combined. The backside alignment marks had been etched to a depth of about 140 microns.

[0036]

By producing an electron beam exposure mask using the alignment mark of the present invention, the back side silicon wafer is wet-etched by wet etching to form an opening and a support frame portion even if the back side silicon wafer penetrates. The alignment mark is etched only to a preset depth, preventing the etchant from sneaking into the front side silicon wafer, resulting in damage to the front side opening pattern,
Destruction can be prevented.

[Brief description of the drawings]

FIG. 1A is an explanatory diagram showing a front-side alignment mark pattern showing one embodiment of an alignment mark of the present invention. (B) is an explanatory view showing a backside alignment mark pattern showing one embodiment of the alignment mark of the present invention.

FIG. 2A is an explanatory diagram showing a front-side alignment mark pattern showing one embodiment of the alignment mark of the present invention. (B) is an explanatory view showing a backside alignment mark pattern showing one embodiment of the alignment mark of the present invention.

FIG. 3 (a) shows an alignment mark of the present invention in SO
FIG. 3 is a plan view showing one embodiment formed on an I wafer.
(B) is a plan view showing an embodiment in which the alignment mark of the present invention is formed on an electron beam exposure mask.

FIGS. 4A to 4F are process cross-sectional views illustrating a method for manufacturing an electron beam exposure mask using an alignment mark according to the present invention.

FIG. 5 is a partially enlarged sectional view showing an alignment mark portion of an electron beam exposure mask using the alignment mark of the present invention. .

FIGS. 6A to 6F are process cross-sectional views illustrating a method of manufacturing an electron beam exposure mask.

FIG. 7A is an explanatory view showing a conventional backside alignment mark pattern formed on a backside silicon wafer. (B) is an explanatory view showing a shape change after etching a conventional backside alignment mark pattern formed on a backside silicon wafer.

FIG. 8 is an explanatory view showing a pattern of a conventional front side alignment mark formed on a front side silicon wafer.

[Explanation of symbols]

11, 21 front-side alignment mark pattern 12, 22 back-side alignment mark pattern 31, 40, 60 SOI wafer 32 electron beam exposure mask 33, 36 alignment mark 34 orientation flat 35 electronic Mask portions 41, 61 of the line exposure mask Back silicon wafers 41a, 61a Support frame portions 42, 62 Silicon oxide layers 43, 63 Front silicon wafers 44, 64 Resist patterns 45, 65 Opening pattern 46 Front alignment mark 47, 66 Protective film 47a, 66a Protective film pattern 47b for forming an opening 47b Protective film pattern 48, 67 for forming a backside alignment mark Opening 49 … Back side alignment mark 50 …… Slope of back side alignment mark Surface 71, 72: Etched portion of back side alignment mark pattern 71a, 72a: Etched portion of back side alignment mark pattern after wet etching 73 ... Remaining portion of back side alignment mark pattern 73a: Back side alignment after wet etching Remaining portion of mark pattern 81 Front alignment mark w after etching w Back alignment mark (rectangular pattern) width t Back silicon wafer thickness d Back alignment mark etching depth θ Backside alignment mark etching Angle r: etching residue of silicon wafer on the back side of back side alignment mark

Claims (4)

[Claims] 1. An SO in which two silicon wafers are bonded together.
An electron beam exposure mask having an alignment mark for aligning a front side pattern formed on a front side silicon wafer of an I (Silicon on Insulator) wafer and a back side pattern formed on a back side silicon wafer, wherein the alignment mark is a rectangular pattern. An alignment mark comprising a combination. 2. The front side silicon wafer and the back side silicon wafer of the SOI wafer have a plane orientation of (100), and the rectangular patterns forming the alignment marks are arranged parallel or perpendicular to an orientation flat. The alignment mark according to claim 1, wherein 3. The method according to claim 1, wherein a pattern width w of the rectangular pattern satisfies a condition of w <1.4t with respect to a thickness t of the back side silicon wafer. Alignment mark. 4. An electron beam exposure mask manufactured using the alignment mark according to claim 1.