JP2006286847A - Method of manufacturing substrate of semiconductor apparatus - Google Patents

Method of manufacturing substrate of semiconductor apparatus Download PDF

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Publication number
JP2006286847A
JP2006286847A JP2005103410A JP2005103410A JP2006286847A JP 2006286847 A JP2006286847 A JP 2006286847A JP 2005103410 A JP2005103410 A JP 2005103410A JP 2005103410 A JP2005103410 A JP 2005103410A JP 2006286847 A JP2006286847 A JP 2006286847A
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Prior art keywords
substrate
plating
opening
conductor pattern
bonding pad
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JP2005103410A
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Japanese (ja)
Inventor
Kiyoshi Yoshida
清 吉田
Takahiro Kumazawa
隆浩 熊沢
Tokuji Yamamoto
徳治 山本
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Eastern Co Ltd
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Eastern Co Ltd
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Priority to JP2005103410A priority Critical patent/JP2006286847A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a substrate of a semiconductor apparatus with which a burr that occurs in an opening formed in the substrate is prevented and sealing resin leakage from a metallic mold is prevented when sealing resin. <P>SOLUTION: A bonding pad 22 and a conductor pattern/outer connection terminal pad 26 are formed on one face side of a resin substrate 20 by electrolytic plating for supplying power from a plating conductor pattern. A recess is formed where the pads 22 and 26 are exposed. A solder resist layer 30 where a substrate face is formed between the opening 12 and a peripheral edge of the opening 12, and the edge of the bonding pad 22 is removed. The substrate face is covered with a mask 31. Desired plating layers 27b and 27a are formed on respective exposure faces of the bonding pad 22 and the outer connection terminal pad 26 by electrolytic plating. The mask 31 is removed and the plating conductor pattern is removed by etching. The opening 12 is formed by a router. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は半導体装置用基板の製造方法に関し、更に詳細には基板の中央部近傍に形成され、搭載される半導体素子の電極端子が臨む開口部と、前記開口部の周縁近傍の基板面上に形成され、搭載された半導体素子の電極端子とワイヤボンディングされるボンディング用パッドと、前記ボンディング用パッドと導体パターンによって電気的に接続されていると共に、前記ボンディング用パッドよりも外周縁側の基板面上に形成され、外部接続端子が装着される外部接続端子用パッドとが設けられた半導体装置用基板の製造方法に関する。   The present invention relates to a method for manufacturing a substrate for a semiconductor device, and more specifically, an opening formed near the center of the substrate and facing an electrode terminal of a semiconductor element to be mounted, and a substrate surface near the periphery of the opening. A bonding pad to be wire-bonded to the electrode terminal of the semiconductor element formed and mounted, and electrically connected by the bonding pad and the conductor pattern, and on the substrate surface on the outer peripheral side of the bonding pad The manufacturing method of the board | substrate for semiconductor devices provided with the pad for external connection terminals formed in 1 and to which an external connection terminal is mounted | worn.

半導体装置には、図５に示す様に、基板１０の中央部近傍に穿設された開口部１２に、電極端子１４ａ，１４ａ・・が臨むように半導体素子１４が搭載されたものがある。この図５に示す半導体装置では、基板１０の一面側に形成されたボンディング用パッドと半導体素子１４の電極端子１４ａとがワイヤ１６によってワイヤボンディングされて電気的に接続されている。更に、ボンディング用パッドは、外部接続端子としてのはんだボール１８が装着される外部接続端子用パッドと導体パターンによって電気的に接続されている。このワイヤ１６及び電極端子１４ａ、及び半導体素子１４の側面側は封止樹脂１７によって封止されている。
図５に示す基板１０を製造する際には、先ず、一面側の全面が銅箔等の金属箔で覆われた樹脂基板を用い、金属箔にパターニングを施し、図６に示す様に、樹脂基板２０の一面側に、ボンディング用パッド部２２’、外部接続端子用パッド部２６’、及びボンディング用パッド部２２’と外部接続端子用パッド部２６’とを電気的に接続する導体パターン部２４’を形成する。
更に、かかるパターニングの際に、樹脂基板２０の中央部近傍に、めっき用導体パターンとして、主めっき用導体パターン２８，２８及びその分岐導体パターン２８ａ，２８ａ・・を形成する。
このめっき用導体パターンから給電する電解めっきによって、ボンディング用パッド部２２’、導体パターン部２４’及び外部接続端子用パッド部２６’に、所定の電解めっきを施した後、樹脂基板２０の中央部近傍にスリット状の開口部１２を形成する。 As shown in FIG. 5, there is a semiconductor device in which a semiconductor element 14 is mounted so that electrode terminals 14a, 14a,... Face an opening 12 formed near the center of the substrate 10. In the semiconductor device shown in FIG. 5, a bonding pad formed on one surface side of the substrate 10 and the electrode terminal 14a of the semiconductor element 14 are wire-bonded by a wire 16 and electrically connected. Further, the bonding pads are electrically connected to the external connection terminal pads on which the solder balls 18 as external connection terminals are mounted by a conductor pattern. The side surfaces of the wire 16, the electrode terminal 14 a, and the semiconductor element 14 are sealed with a sealing resin 17.
When the substrate 10 shown in FIG. 5 is manufactured, first, a resin substrate whose entire surface on one side is covered with a metal foil such as a copper foil is used, and the metal foil is patterned. As shown in FIG. On one surface side of the substrate 20, a bonding pad portion 22 ′, an external connection terminal pad portion 26 ′, and a conductor pattern portion 24 that electrically connects the bonding pad portion 22 ′ and the external connection terminal pad portion 26 ′. 'Form.
Further, during the patterning, main plating conductor patterns 28 and 28 and branch conductor patterns 28a, 28a,... Are formed as plating conductor patterns in the vicinity of the center of the resin substrate 20.
After electrolytic plating is performed by feeding power from the plating conductor pattern, predetermined electroplating is performed on the bonding pad portion 22 ′, the conductor pattern portion 24 ′, and the external connection terminal pad portion 26 ′, and then the central portion of the resin substrate 20. A slit-shaped opening 12 is formed in the vicinity.

かかる開口部１２をプレス加工によって形成すると、樹脂基板２０に衝撃が加えられることに因って、樹脂基板２０が白化したり、微小なクラックが発生したりし易い。この白化現象や微小クラックの発生は、最終的に得られる半導体装置の信頼性を低下させるおそれがある。
かかるプレス加工に代えてルータ加工によって開口部１２を形成すると、開口部１２を形成する際の衝撃に因る樹脂基板２０の白化現象や微小クラックの発生を防止できる。
しかし、開口部１２は、主めっき用導体パターン２８，２８及びその分岐導体パターン２８ａ，２８ａ・・をルータで切断しつつ形成するため、開口部１２の内壁面から分岐導体パターン２８ａ等のバリが発生し易い。
ところで、下記特許文献１には、銅パターン等のパターンが形成された基板にルータ加工によってスリットを形成する際に、ルータ加工を施す基板の箇所の凹凸面をソルダレジスト層の形成によって可及的に平坦面にした後、ルータ加工を施すことによって、形成したスリットの内壁面からのバリの発生を防止できることが提案されている。
特開２００２−２９９７９０号（特許請求の範囲） When the opening 12 is formed by press working, the resin substrate 20 is likely to be whitened or minute cracks are easily generated due to an impact applied to the resin substrate 20. This whitening phenomenon and the occurrence of microcracks may reduce the reliability of the finally obtained semiconductor device.
If the opening 12 is formed by router processing instead of the press working, it is possible to prevent the whitening phenomenon of the resin substrate 20 and the occurrence of microcracks due to the impact when the opening 12 is formed.
However, since the opening 12 is formed by cutting the main plating conductor patterns 28 and 28 and the branch conductor patterns 28a, 28a,... With a router, burrs such as the branch conductor pattern 28a are formed from the inner wall surface of the opening 12. It is easy to generate.
By the way, in Patent Document 1 below, when a slit is formed on a substrate on which a pattern such as a copper pattern is formed by router processing, the uneven surface of the portion of the substrate to be subjected to router processing is made possible by forming a solder resist layer. It has been proposed that the burr can be prevented from being generated from the inner wall surface of the formed slit by performing router processing after making the surface flat.
JP 2002-299790 (Claims)

本発明者等は、図６に示す樹脂基板２０の中央部近傍にルータ加工によってスリット状の開口部１２を形成する際に、主めっき用導体パターン２８，２８等を形成した樹脂基板２０の一面側の全面にソルダレジスト層を形成して平坦面とした後、ルータ加工によって開口部１２を形成したところ、開口部１２の内壁面から分岐導体パターン２８ａ等のバリの発生を防止できることが判明した。
しかし、開口部１２を形成した基板１０の他面側に、図７に示す様に、半導体素子１４を接着剤３２で接着した後、開口部１２に臨む半導体素子１４の電極端子１４ａと基板１０のボンディング用パッド２２とワイヤ１６によってワイヤボンディングしたところ、ワイヤ１６がソルダレジスト層３０と接触することがある。ワイヤ１６がソルダレジスト層３０と接触すると、ワイヤ１６の形状が歪んだりして、隣接するワイヤ１６と接触するおそれがある。 When forming the slit-shaped opening 12 near the center of the resin substrate 20 shown in FIG. 6 by router processing, the present inventors provide one surface of the resin substrate 20 on which the main plating conductor patterns 28, 28, etc. are formed. After forming a solder resist layer on the entire surface of the side to form a flat surface and then forming the opening 12 by router processing, it has been found that the occurrence of burrs such as the branch conductor pattern 28a from the inner wall surface of the opening 12 can be prevented. .
However, as shown in FIG. 7, the semiconductor element 14 is bonded to the other surface side of the substrate 10 on which the opening 12 is formed with an adhesive 32, and then the electrode terminal 14 a of the semiconductor element 14 facing the opening 12 and the substrate 10. When wire bonding is performed using the bonding pad 22 and the wire 16, the wire 16 may come into contact with the solder resist layer 30. When the wire 16 comes into contact with the solder resist layer 30, the shape of the wire 16 may be distorted and may come into contact with the adjacent wire 16.

かかるワイヤ１６の高さは、予め定められているため、ソルダレジスト層３０を薄くすると、ワイヤ１６及び半導体素子１４の電極端子１４ａを樹脂封止するモールド金型３４が当接する部分のシールが不十分となり易く、封止樹脂洩れが発生するおそれがある。
この封止樹脂洩れを防止すべく、モールド金型３４のソルダレジスト層３０に対する当接圧力を高くすると、ソルダレジスト層３０で覆われている導体パターン２４等に悪影響を与えるおそれがある。
そこで、本発明の課題は、ルータ加工によって基板に開口部を形成しても、その内壁面に発生するバリを防止でき、且つ樹脂封止する際に、モールド金型からの封止樹脂洩れを防止できる半導体装置用基の製造方法を提供することにある。 Since the height of the wire 16 is determined in advance, if the solder resist layer 30 is thinned, sealing of the portion where the wire 16 and the mold die 34 for resin-sealing the electrode terminal 14a of the semiconductor element 14 are not sealed. This is likely to be sufficient, and sealing resin leakage may occur.
If the contact pressure of the mold die 34 against the solder resist layer 30 is increased to prevent this leakage of the sealing resin, the conductor pattern 24 covered with the solder resist layer 30 may be adversely affected.
Therefore, the object of the present invention is to prevent burr generated on the inner wall surface of the substrate even when the opening is formed in the substrate by router processing, and to prevent sealing resin leakage from the mold when sealing with resin. An object of the present invention is to provide a method for manufacturing a semiconductor device substrate that can be prevented.

本発明者等は、前記課題を解決するには、ルータ加工前に、開口部を形成する基板部分の基板面を露出し、露出した基板面に表れた主めっき用導体パターン２８等のめっき用導体パターンを除去した後、ルータ加工を施すことが有利であると考え検討した結果、本発明に到達した。
すなわち、本発明は、基板の中央部近傍に形成され、搭載される半導体素子の電極端子が臨む開口部と、前記開口部の周縁部近傍の基板面上に形成され、搭載された半導体素子の電極端子とワイヤボンディングされるボンディング用パッドと、前記ボンディング用パッドと導体パターンによって電気的に接続されていると共に、前記ボンディング用パッドよりも基板の外周縁側の基板面上に形成され、外部接続端子が装着される外部接続端子用パッドとが設けられた半導体装置用基板を製造する際に、該基板の基板面にボンディング用パッド、導体パターン及び外部接続端子用パッドを、前記開口部を形成する基板部分の一面側に形成しためっき用導体パターンから給電する電解めっきによって形成した後、前記基板の基板面の一面側全面に形成したソルダレジスト層に、前記ボンディング用パッド及び外部接続端子用パッドが底面に露出する凹部を形成すると共に、前記開口部を形成する基板部分及び前記ボンディング用パッドの端縁と開口部の周縁との間の基板部分の基板面を覆うソルダレジスト層を除去し、次いで、露出した前記基板面をマスクによって覆い、前記凹部の各底面に露出するボンディング用パッド及び外部接続端子用パッドの各上面に所望のめっき層を、前記めっき用導体パターンから給電する電解めっきによって形成した後、前記マスクを除去して、露出した基板面上に表れた前記めっき用導体パターンを、前記ボンディング用パッド及び外部接続端子用パッドの各上面に形成しためっき層をエッチングすることなくエッチングして除去し、その後、前記基板面が露出する基板部分にルータによって開口部を形成することを特徴とする半導体装置用基板の製造方法にある。 In order to solve the above problems, the inventors have exposed the substrate surface of the substrate portion where the opening is to be formed before processing the router, and for plating the main plating conductor pattern 28 and the like appearing on the exposed substrate surface. As a result of considering that it is advantageous to perform router processing after removing the conductor pattern, the present invention has been achieved.
That is, the present invention provides an opening formed near a central portion of a substrate and facing an electrode terminal of a semiconductor element to be mounted, and a substrate surface formed and mounted on a substrate surface near the peripheral edge of the opening. A bonding pad that is wire-bonded to the electrode terminal, and is electrically connected to the bonding pad and a conductor pattern, and is formed on the substrate surface on the outer peripheral side of the substrate with respect to the bonding pad. When manufacturing a substrate for a semiconductor device provided with a pad for external connection terminals to be mounted, a bonding pad, a conductor pattern, and an external connection terminal pad are formed on the substrate surface of the substrate. After forming by electrolytic plating that feeds power from the plating conductor pattern formed on one side of the substrate part, on the entire one side of the substrate surface of the substrate In the formed solder resist layer, a concave portion where the bonding pad and the external connection terminal pad are exposed to the bottom surface is formed, and the substrate portion forming the opening, the edge of the bonding pad, and the peripheral edge of the opening, The solder resist layer covering the substrate surface of the substrate portion between is removed, and then the exposed substrate surface is covered with a mask, and the bonding pads and the external connection terminal pads exposed on the bottom surfaces of the recesses After a desired plating layer is formed by electrolytic plating that feeds power from the plating conductor pattern, the mask is removed, and the plating conductor pattern that appears on the exposed substrate surface is connected to the bonding pad and external connection. The plating layer formed on each upper surface of the terminal pad is removed by etching without etching. In method of manufacturing a substrate for a semiconductor device, which comprises forming an opening by the router to the substrate portion where the surface is exposed.

かかる本発明において、露出した基板面を覆うマスクとして、ドライフィルムを用いることによって、露出した基板面に表れためっき用導体パターンを容易に覆うことができる。
また、露出した基板面上に表れためっき用導体パターンのエッチングを、ボンディング用パッド及び外部接続端子用パッドの各上面に形成しためっき層をエッチングすることのないエッチング液に基板を浸漬して施すことによって、露出した基板面上のめっき用導体パターンを容易に除去できる。
この際に、ボンディング用パッド、導体パターン、外部接続端子用パッド及びめっき用導体パターンを銅又はその合金によって形成し、前記ボンディング用パッド及び外部接続端子用パッドの各上面に、下地めっき層としてのニッケルめっき層と、前記ニッケルめっき層上に金めっき層とから成るめっき層を形成することが好適である。 In the present invention, by using a dry film as a mask for covering the exposed substrate surface, the plating conductor pattern appearing on the exposed substrate surface can be easily covered.
Further, the plating conductor pattern appearing on the exposed substrate surface is etched by immersing the substrate in an etching solution that does not etch the plating layer formed on each upper surface of the bonding pad and the external connection terminal pad. Thus, the conductive pattern for plating on the exposed substrate surface can be easily removed.
At this time, a bonding pad, a conductor pattern, an external connection terminal pad and a plating conductor pattern are formed of copper or an alloy thereof, and an upper plating layer is formed on each upper surface of the bonding pad and the external connection terminal pad. It is preferable to form a plating layer comprising a nickel plating layer and a gold plating layer on the nickel plating layer.

本発明によれば、ルータ加工前に、開口部を形成する基板部分及びボンディング用パッドの端縁と開口部の周縁との間の基板部分の基板面を露出し、この基板面上に表れためっき用導体パターンを除去した後、ルータ加工によって開口部を形成している。このため、ルータ加工によって開口部を形成する際に、めっき用導体パターンをルータによって切断することに因るバリの発生を防止できる。
更に、ボンディング用パッドと開口部との間の基板部分の基板面も露出しているため、開口部を形成した基板の他面側又は開口部内に半導体素子を搭載した後、開口部に臨む半導体素子の電極端子と基板のボンディング用パッドとをワイヤによってワイヤボンディングする際に、ワイヤがソルダレジスト層と接触することを防止できる。
一方、基板の開口部及びボンディング用パッドの部分を樹脂封止する際に、モールド金型が当接するソルダレジスト層は、ソルダレジスト層とモールド金型との間が充分にシールされ、モールド金型からの封止樹脂洩れを防止できる厚さにできる。
その結果、本発明に係る半導体装置用基板の製造方法によって、信頼性の高い半導体装置を得ることができる半導体装置用基板を提供できる。 According to the present invention, the substrate surface of the substrate portion between the edge of the bonding pad and the edge of the bonding pad and the periphery of the opening is exposed and appears on the substrate surface before processing the router. After removing the plating conductor pattern, an opening is formed by router processing. For this reason, when forming an opening by router processing, generation | occurrence | production of the burr | flash resulting from cutting | disconnecting the metal-plating conductor pattern with a router can be prevented.
Further, since the substrate surface of the substrate portion between the bonding pad and the opening is also exposed, the semiconductor element is mounted on the other surface side of the substrate in which the opening is formed or in the opening, and then the semiconductor facing the opening When wire bonding the electrode terminal of the element and the bonding pad of the substrate with the wire, the wire can be prevented from coming into contact with the solder resist layer.
On the other hand, when the opening of the substrate and the bonding pad portion are resin-sealed, the solder resist layer with which the mold die contacts is sufficiently sealed between the solder resist layer and the mold die. The thickness can prevent leakage of the sealing resin from.
As a result, a semiconductor device substrate capable of obtaining a highly reliable semiconductor device can be provided by the method for manufacturing a semiconductor device substrate according to the present invention.

本発明に係る製造方法の一例を図１に示す。先ず、樹脂基板２０の一面側にボンディング用パッド２２、外部接続端子用パッド２６及び導体パターン（図示せず）を形成する［図１（ａ）］。
かかるボンディング用パッド２２、外部接続端子用パッド２６及び導体パターンは、一面側の全面が銅箔等の金属箔で覆われた樹脂基板を用い、金属箔にパターニングを施し、図６に示す様に、樹脂基板２０の一面側に、ボンディング用パッド部分２２’、外部接続端子用パッド部分２６’、及びボンディング用パッド部分２２’と外部接続端子用パッド部分２６’とを電気的に接続する導体パターン部２４’を形成する。
更に、かかるパターニングの際に、図６に示す様に、樹脂基板２０の中央部近傍に、めっき用導体パターンとして、主めっき用導体パターン２８，２８及びその分岐導体パターン２８ａ，２８ａ・・を形成する。分岐導体パターン２８ａは、主めっき用導体パターン２８，２８とボンディング用パッド部分２２とを電気的に接続している。
このめっき用導体パターンから給電する電解めっきによって、ボンディング用パッド部２２’、導体パターン部２４’及び外部接続端子用パッド部２６’等に、所定の電解めっきを施すことによって、図１（ａ）に示す様に、ボンディング用パッド２２、外部接続端子用パッド２６及び導体パターン（図示せず）が形成された樹脂基板２０（図６に示す樹脂基板２０）を得ることができる。 An example of the manufacturing method according to the present invention is shown in FIG. First, a bonding pad 22, an external connection terminal pad 26, and a conductor pattern (not shown) are formed on one side of the resin substrate 20 [FIG. 1 (a)].
The bonding pad 22, the external connection terminal pad 26, and the conductor pattern are formed by patterning the metal foil using a resin substrate whose entire surface is covered with a metal foil such as a copper foil, as shown in FIG. The bonding pad portion 22 ′, the external connection terminal pad portion 26 ′, and the conductor pattern for electrically connecting the bonding pad portion 22 ′ and the external connection terminal pad portion 26 ′ on one surface side of the resin substrate 20. Form part 24 '.
Further, during the patterning, as shown in FIG. 6, the main plating conductor patterns 28 and 28 and the branched conductor patterns 28a, 28a,... Are formed as plating conductor patterns near the center of the resin substrate 20. To do. The branch conductor pattern 28 a electrically connects the main plating conductor patterns 28, 28 and the bonding pad portion 22.
By performing predetermined electroplating on the bonding pad portion 22 ′, the conductor pattern portion 24 ′, the external connection terminal pad portion 26 ′, etc. by electrolytic plating that feeds power from the plating conductor pattern, FIG. As shown in FIG. 6, a resin substrate 20 (resin substrate 20 shown in FIG. 6) on which bonding pads 22, external connection terminal pads 26, and conductor patterns (not shown) are formed can be obtained.

図１（ａ）に示す樹脂基板２０のボンディング用パッド２２等が形成された一面側の全面に、図１（ｂ）に示す様に、ソルダレジスト層３０を形成する。このソルダレジスト層３０は、スクリーン印刷又はドライフィルムの貼着によって形成できる。かかるソルダレジスト層３０の厚さは、樹脂封止等の際に、モールド金型からの封止樹脂洩れを防止できるように、当接したモールド金型とソルダレジスト層との間が充分にシールされる厚さとすることが好ましい。
このソルダレジスト層３０には、図１（ｃ）に示す様に、ボンディング用パッド２２及び外部接続端子用パッド２６を露出すると共に、開口部を形成する基板部分及びボンディング用パッド２２の端縁と開口部の周縁との間の基板部分の基板面を覆うソルダレジスト層３０も除去する。この様に、ソルダレジスト層３０の特定の箇所を除去するには、例えばソルダレジスト層３０を形成するソルダレジストとして、感光性ソルダレジストを用いて現像処理を施すことによって行うことができる。 As shown in FIG. 1B, a solder resist layer 30 is formed on the entire surface of the resin substrate 20 shown in FIG. 1A on which the bonding pads 22 and the like are formed. The solder resist layer 30 can be formed by screen printing or dry film sticking. The thickness of the solder resist layer 30 is sufficiently sealed between the abutting mold die and the solder resist layer so that sealing resin leakage from the mold die can be prevented during resin sealing or the like. It is preferable to set the thickness to be set.
As shown in FIG. 1C, the solder resist layer 30 exposes the bonding pads 22 and the external connection terminal pads 26, and forms a substrate portion that forms an opening and an edge of the bonding pad 22. The solder resist layer 30 covering the substrate surface of the substrate portion between the periphery of the opening is also removed. In this manner, a specific portion of the solder resist layer 30 can be removed by performing development using a photosensitive solder resist as a solder resist for forming the solder resist layer 30, for example.

更に、ソルダレジスト層３０を除去して露出した基板面には、分岐導体パターン２８ａ等のめっき用導体パターンが表れるため、露出した基板面を図１（ｄ）に示す様に、マスク３１で覆う。このマスク３１としては、ドライフィルムを用いて現像処理を施すことによって必要な箇所を容易に覆うことができる。
この様に、マスク３１によって覆われためっき用導体パターンから給電する電解めっきによって、ボンディング用パッド２２及び外部接続端子用パッド２６の露出面に、図１（ｄ）に示す様に、めっき層２７ａ，２７ａを形成する。このめっき層２７ａ，２７ａとしては、ボンディング用パッド２２及び外部接続端子用パッド２６を銅又はその合金によって形成した場合、ボンディング用パッド２２及び外部接続端子用パッド２６の各上面に、下地めっき層としてのニッケルめっき層と、このニッケルめっき層上に形成した金めっき層とから成るめっき層２７ａ，２７ａを形成することが好ましい。 Further, since the plating conductor pattern such as the branched conductor pattern 28a appears on the substrate surface exposed by removing the solder resist layer 30, the exposed substrate surface is covered with a mask 31 as shown in FIG. . The mask 31 can easily cover a necessary portion by performing development processing using a dry film.
As shown in FIG. 1D, the plating layer 27a is formed on the exposed surfaces of the bonding pad 22 and the external connection terminal pad 26 by electrolytic plating in which power is supplied from the plating conductor pattern covered with the mask 31. , 27a. As the plating layers 27a and 27a, when the bonding pads 22 and the external connection terminal pads 26 are formed of copper or an alloy thereof, the base plating layers are formed on the upper surfaces of the bonding pads 22 and the external connection terminal pads 26, respectively. It is preferable to form plating layers 27a and 27a comprising a nickel plating layer and a gold plating layer formed on the nickel plating layer.

次いで、図１（ｅ）に示す様に、基板２０に開口部１２を形成する基板部分及びボンディング用パッド２２の端縁と開口部１２の周縁との間の基板部分の基板面を覆うマスク３１を除去する。
かかるマスク３１の除去は、ソルダレスト層３０を剥離することのないマスク３１の剥離液に浸漬することによって行うことができる。
この様に、マスク３１を剥離すると、図１（ｅ）に示す様に、露出した基板２０の基板面に分岐導体パターン２８ａ等のめっき用導体パターンが表れる。この基板面が露出した基板部分にルータによって開口部１２を形成すると、表れためっき用導体パターンをルータによって切断してバリの原因となり易い。
このため、露出した基板面上に表れた分岐導体パターン２８ａ等のめっき用導体パターンを、図１（ｆ）に示す様に、エッチングして除去する。この際に、めっき用導体パターン上には、めっき層２７ａ，２７ａが形成されていないため、ボンディング用パッド２２及び外部接続端子用パッド２６の各上面に形成しためっき層２７ａ，２７ａをエッチングすることなくめっき用導体パターンのみをエッチングするエッチング液を用いる。かかるエッチング液を用いることによってめっき用導体パターンの作業を簡単化できる。
特に、めっき層２７ａ，２７ａの最上層が金めっき層で形成されている場合には、エッチング液の選択の幅を広げることができ好ましい。 Next, as shown in FIG. 1E, a mask 31 that covers the substrate surface of the substrate portion where the opening 12 is formed in the substrate 20 and the substrate surface between the edge of the bonding pad 22 and the periphery of the opening 12. Remove.
Such removal of the mask 31 can be performed by immersing the solder rest layer 30 in a stripping solution of the mask 31 that does not peel off.
Thus, when the mask 31 is peeled off, plating conductor patterns such as the branch conductor pattern 28a appear on the exposed substrate surface of the substrate 20, as shown in FIG. If the opening 12 is formed by a router in the substrate portion where the substrate surface is exposed, the exposed conductor pattern for plating is likely to be cut by the router and cause burrs.
Therefore, the plating conductor patterns such as the branch conductor pattern 28a appearing on the exposed substrate surface are removed by etching as shown in FIG. At this time, since the plating layers 27a and 27a are not formed on the plating conductor pattern, the plating layers 27a and 27a formed on the upper surfaces of the bonding pad 22 and the external connection terminal pad 26 are etched. An etching solution for etching only the conductive pattern for plating is used. By using such an etching solution, the work of the plating conductor pattern can be simplified.
In particular, when the uppermost layer of the plating layers 27a and 27a is formed of a gold plating layer, it is preferable because the selection range of the etching solution can be widened.

その後、図１（ｇ）に示す様に、基板面が露出する樹脂基板２０の中央部近傍に、ルータによってスリット状の開口部１２を形成する。
かかるルータ加工によって開口部１２を形成する基板部分には、その露出面に表れた図６に示すめっき用導体パターンの表れた部分は除去されている。このため、基板面が露出した部分にルータ加工で開口部１２を形成しても、めっき用導体パターンを切断することに因るバリの発生を防止できる。
基板２０の中央部近傍にスリット状の開口部１２が形成された基板１０は、図２に示す様に、開口部１２を形成した基板１０の他面側に半導体素子１４を接着剤３２で接着し、開口部１２に臨む半導体素子１４の電極端子１４ａと、上面にめっき層２７ａを形成したボンディング用パッド２２とをワイヤ１６によってワイヤボンディングしている。
この基板１０では、ボンディング用パッド２２の端縁と開口部１２の周縁との間の基板部分では、その基板面が露出している。このため、基板１０の開口部１２に半導体素子１４の電極端子１４ａが臨むように、半導体素子１４を基板１０の他面側に接着剤３２によって接合して搭載した後、半導体素子１４の電極端子１４ａとボンディング用パッド２２とをワイヤ１６を用いてワイヤボンディングするとき、ワイヤ１６は基板構成部材との接触を充分に回避できる。
更に、ワイヤボンディングした後、ボンディング用パッド２２、この上面に形成しためっき層２７ａ、ワイヤ１６及び開口部１２を樹脂封止する際に、図２に示す様に、モールド金型３４は充分な厚さのソルダレジスト層３０に当接するため、ソルダレジスト層３０ｂとモールド金型３４との間が充分にシールされ、モールド金型３４からの封止樹脂洩れを防止できる。
このモールド金型３４の当接圧力は、ソルダレジスト層３０によって吸収されるため、ボンディング用パッド２２と外部接続端子用パッド２６とを電気的に接続する導体パターンに対する悪影響を防止できる。
また、上面にめっき層２７ａを形成した外部接続端子用パッド２６には、図２に示す様に、はんだボール１８を搭載する。この際に、めっき層２７ａを、下地層としてのニッケルめっき層と、このニッケルめっき層上に形成した金めっき層とから構成することによって、はんだボール１８と外部接続端子用パッド２６とは、両者の接合面近傍に共晶合金を形成して強固に接合できる。
以上の説明では、スリット状の開口部１２を形成しているが、矩形状の開口部であってもよく、任意の形状の開口部を形成できる。 Thereafter, as shown in FIG. 1G, a slit-like opening 12 is formed by a router in the vicinity of the center of the resin substrate 20 where the substrate surface is exposed.
In the substrate portion where the opening 12 is formed by the router processing, the portion where the plating conductor pattern shown in FIG. 6 appears on the exposed surface is removed. For this reason, even if the opening 12 is formed in the exposed portion of the substrate surface by router processing, it is possible to prevent the occurrence of burrs caused by cutting the plating conductor pattern.
As shown in FIG. 2, the substrate 10 in which the slit-shaped opening 12 is formed in the vicinity of the center of the substrate 20 is bonded to the semiconductor element 14 with the adhesive 32 on the other surface side of the substrate 10 on which the opening 12 is formed. The electrode terminal 14 a of the semiconductor element 14 facing the opening 12 and the bonding pad 22 having the plating layer 27 a formed on the upper surface are wire-bonded by the wire 16.
In this substrate 10, the substrate surface is exposed at the substrate portion between the edge of the bonding pad 22 and the periphery of the opening 12. For this reason, after mounting the semiconductor element 14 on the other surface side of the substrate 10 with the adhesive 32 so that the electrode terminal 14a of the semiconductor element 14 faces the opening 12 of the substrate 10, the electrode terminal of the semiconductor element 14 is mounted. When the wire bonding is performed between the wire 14a and the bonding pad 22 using the wire 16, the wire 16 can sufficiently avoid contact with the substrate constituent member.
Further, after wire bonding, when the bonding pad 22, the plating layer 27a formed on the upper surface, the wire 16 and the opening 12 are resin-sealed, the mold die 34 has a sufficient thickness as shown in FIG. Since it contacts the solder resist layer 30, the space between the solder resist layer 30b and the mold die 34 is sufficiently sealed, and sealing resin leakage from the mold die 34 can be prevented.
Since the contact pressure of the mold die 34 is absorbed by the solder resist layer 30, it is possible to prevent an adverse effect on the conductor pattern that electrically connects the bonding pad 22 and the external connection terminal pad 26.
In addition, as shown in FIG. 2, solder balls 18 are mounted on the external connection terminal pads 26 having the plating layer 27a formed on the upper surface. At this time, by forming the plating layer 27a from a nickel plating layer as an underlayer and a gold plating layer formed on the nickel plating layer, the solder ball 18 and the external connection terminal pad 26 are both It is possible to form a eutectic alloy in the vicinity of the joining surface and to join firmly.
In the above description, the slit-shaped opening 12 is formed, but it may be a rectangular opening, and an opening of an arbitrary shape can be formed.

また、半導体装置には、図３（ａ）に示す様に、基板１０の中央部近傍に開口部として穿設された矩形状のデバイスホール４０内に搭載された半導体素子１４の電極端子１４ａと基板１０の一面側に形成されたボンディング用パッドとがワイヤ１６によってワイヤボンディングされて電気的に接続されているものもある。かかるボンディング用パッドは、外部接続端子としてのはんだボール１８が装着される外部接続端子用パッドと導体パターンによって電気的に接続されている。このワイヤ１６及び電極端子１４ａ、及び半導体素子１４の側面側は封止樹脂１７によって封止されている。
更に、図３（ｂ）に示す様に、半導体素子１４が搭載された複数個の基板１０をスタックすべく、基板１０の両面側に外部接続端子としてのはんだボール１８が装着された半導体装置も存在する。図３（ｂ）に示す半導体素子１４が搭載された基板１０は、基板１０の中央部近傍に穿設された開口部としてのデバイスホール４０内に搭載された半導体素子１４の電極端子１４ａと基板１０の両面側に形成されたボンディング用パッドとがワイヤ１６によってワイヤボンディングされて電気的に接続されている。かかるボンディング用パッドは、外部接続端子としてのはんだボール１８が装着される外部接続端子用パッドと導体パターンによって電気的に接続されている。このワイヤ１６及び電極端子１４ａ、及び半導体素子１４の側面側は封止樹脂１７によって封止されている。 In addition, as shown in FIG. 3A, the semiconductor device includes an electrode terminal 14a of a semiconductor element 14 mounted in a rectangular device hole 40 formed as an opening in the vicinity of the center of the substrate 10. In some cases, a bonding pad formed on one surface of the substrate 10 is wire-bonded by a wire 16 and electrically connected. Such a bonding pad is electrically connected to an external connection terminal pad on which a solder ball 18 as an external connection terminal is mounted by a conductor pattern. The side surfaces of the wire 16, the electrode terminal 14 a, and the semiconductor element 14 are sealed with a sealing resin 17.
Further, as shown in FIG. 3B, there is also a semiconductor device in which solder balls 18 as external connection terminals are mounted on both sides of the substrate 10 in order to stack a plurality of substrates 10 on which the semiconductor elements 14 are mounted. Exists. The substrate 10 on which the semiconductor element 14 shown in FIG. 3B is mounted includes the electrode terminal 14a of the semiconductor element 14 mounted in the device hole 40 as an opening formed near the center of the substrate 10 and the substrate. Bonding pads formed on both sides of the wire 10 are wire-bonded by wires 16 and are electrically connected. Such a bonding pad is electrically connected to an external connection terminal pad on which a solder ball 18 as an external connection terminal is mounted by a conductor pattern. The side surfaces of the wire 16, the electrode terminal 14 a, and the semiconductor element 14 are sealed with a sealing resin 17.

図３（ａ）（ｂ）に示す基板１０を形成する際には、図４に示す様に、樹脂基板２０の一面側に、ボンディング用パッド部２２’、外部接続端子用パッド部２６’、及びボンディング用パッド部２２’と外部接続端子用パッド部２６’とを電気的に接続する導体パターン部２４’を形成する。
更に、かかるパターニングの際に、樹脂基板２０の中央部近傍に、めっき用導体パターンとして、主めっき用導体部２９に給電する給電用導体パターン２９ａ，２９ａ、及び主めっき用導体部２９と各ボンディング用パッド部２２’とを電気的に接続する分岐導体パターン２９ｂ，２９ｂ・・を形成する。
このめっき用導体パターンから給電する電解めっきによって、ボンディング用パッド部２２’、導体パターン部２４’及び外部接続端子用パッド部２６’に、所定の電解めっきを施した後、樹脂基板２０の中央部近傍に矩形状のデバイスホール４０（図４に点線で示す部分）を形成する。
かかる図３に示す基板１０は、図１に示す製造方法で得ることができ、その詳細な説明は省略するが、樹脂基板２０の中央部近傍に形成するめっき用導体パターンは、図４に示す様に、主めっき用導体部２９、主めっき用導体部２９に給電する給電用導体部２９ａ，２９ａ、及び主めっき用導体部２９と各ボンディング用パッド部２２’とを電気的に接続する分岐導体パターン２９ｂ，２９ｂ・・から構成される。また、ルータ加工によって形成されるデバイスホール４０は、搭載する半導体素子１４よりも大きい。 When forming the substrate 10 shown in FIGS. 3 (a) and 3 (b), as shown in FIG. 4, on one surface side of the resin substrate 20, a bonding pad portion 22 ′, an external connection terminal pad portion 26 ′, In addition, a conductor pattern portion 24 ′ that electrically connects the bonding pad portion 22 ′ and the external connection terminal pad portion 26 ′ is formed.
Further, during the patterning, in the vicinity of the central portion of the resin substrate 20, as the plating conductor pattern, the power supply conductor patterns 29a and 29a for supplying power to the main plating conductor portion 29, and the main plating conductor portion 29 and each bonding are provided. Branch conductor patterns 29b, 29b,... For electrically connecting to the pad portion 22 ′ are formed.
After electrolytic plating is performed by feeding power from the plating conductor pattern, predetermined electroplating is performed on the bonding pad portion 22 ′, the conductor pattern portion 24 ′, and the external connection terminal pad portion 26 ′, and then the central portion of the resin substrate 20. A rectangular device hole 40 (portion indicated by a dotted line in FIG. 4) is formed in the vicinity.
The substrate 10 shown in FIG. 3 can be obtained by the manufacturing method shown in FIG. 1, and detailed description thereof is omitted, but the plating conductor pattern formed in the vicinity of the central portion of the resin substrate 20 is shown in FIG. 4. Similarly, the main plating conductor portion 29, the power supply conductor portions 29a and 29a for supplying power to the main plating conductor portion 29, and the branch for electrically connecting the main plating conductor portion 29 and each bonding pad portion 22 ′. It is composed of conductor patterns 29b, 29b. Further, the device hole 40 formed by router processing is larger than the semiconductor element 14 to be mounted.

本発明に係る半導体装置用基板の製造方法の一例を説明する工程図である。It is process drawing explaining an example of the manufacturing method of the board | substrate for semiconductor devices which concerns on this invention. 図１に示す製造方法で得た半導体装置用基板を用いた半導体装置の一例を説明する断面図である。It is sectional drawing explaining an example of the semiconductor device using the board | substrate for semiconductor devices obtained with the manufacturing method shown in FIG. 半導体装置の他の例を示す断面図である。It is sectional drawing which shows the other example of a semiconductor device. 図３に示す基板にデバイスホールを形成する前の基板の状態を説明するための説明図である。It is explanatory drawing for demonstrating the state of the board | substrate before forming a device hole in the board | substrate shown in FIG. 半導体装置の一例を示す断面図である。It is sectional drawing which shows an example of a semiconductor device. 図５に示す基板に開口部を形成する前の基板の状態を説明するための説明図である。It is explanatory drawing for demonstrating the state of the board | substrate before forming an opening part in the board | substrate shown in FIG. ソルダレジスト層の厚さとワイヤボンディングのワイヤとの関係を説明するための部分断面図である。It is a fragmentary sectional view for demonstrating the relationship between the thickness of a soldering resist layer, and the wire of wire bonding.

符号の説明Explanation of symbols

１０ 半導体装置用基板
１２ 開口部
１４ 半導体素子
１４ａ 電極端子
１６ ワイヤ
１７ 封止樹脂
１８ ボール
２２ ボンディング用パッド
２４ 導体パターン
２６ 外部接続端子用パッド
２７ａ めっき層
２８ 主めっき用導体パターン
２９ 主めっき用導体部
２９ａ 給電用導体パターン
２８ａ，２９ｂ 分岐導体パターン
３０ ソルダレジスト層
３１ マスク
３２ 接着層
３４ モールド金型 DESCRIPTION OF SYMBOLS 10 Semiconductor device substrate 12 Opening 14 Semiconductor element 14a Electrode terminal 16 Wire 17 Sealing resin 18 Ball 22 Bonding pad 24 Conductive pattern 26 External connection terminal pad 27a Plating layer 28 Main plating conductor pattern 29 Main plating conductor 29a Feeding conductor patterns 28a, 29b Branching conductor pattern 30 Solder resist layer 31 Mask 32 Adhesive layer 34 Mold

Claims (4)

基板の中央部近傍に形成され、搭載される半導体素子の電極端子が臨む開口部と、前記開口部の周縁部近傍の基板面上に形成され、搭載された半導体素子の電極端子とワイヤボンディングされるボンディング用パッドと、前記ボンディング用パッドと導体パターンによって電気的に接続されていると共に、前記ボンディング用パッドよりも基板の外周縁側の基板面上に形成され、外部接続端子が装着される外部接続端子用パッドとが設けられた半導体装置用基板を製造する際に、
該基板の基板面にボンディング用パッド、導体パターン及び外部接続端子用パッドを、前記開口部を形成する基板部分の一面側に形成しためっき用導体パターンから給電する電解めっきによって形成した後、
前記基板の基板面の一面側全面に形成したソルダレジスト層に、前記ボンディング用パッド及び外部接続端子用パッドが底面に露出する凹部を形成すると共に、前記開口部を形成する基板部分及び前記ボンディング用パッドの端縁と開口部の周縁との間の基板部分の基板面を覆うソルダレジスト層を除去し、
次いで、露出した前記基板面をマスクによって覆い、前記凹部の各底面に露出するボンディング用パッド及び外部接続端子用パッドの各上面に所望のめっき層を、前記めっき用導体パターンから給電する電解めっきによって形成した後、
前記マスクを除去して、露出した基板面上に表れた前記めっき用導体パターンを、前記ボンディング用パッド及び外部接続端子用パッドの各上面に形成しためっき層をエッチングすることなくエッチングして除去し、
その後、前記基板面が露出する基板部分にルータによって開口部を形成することを特徴とする半導体装置用基板の製造方法。 An opening formed near the center of the substrate and facing an electrode terminal of the mounted semiconductor element, and formed on the substrate surface near the peripheral edge of the opening and wire-bonded to the electrode terminal of the mounted semiconductor element. A bonding pad that is electrically connected to the bonding pad and a conductor pattern, and is formed on a substrate surface on the outer peripheral side of the substrate with respect to the bonding pad, and is connected to an external connection terminal When manufacturing a substrate for a semiconductor device provided with a terminal pad,
After forming a bonding pad, a conductor pattern, and an external connection terminal pad on the substrate surface of the substrate by electrolytic plating that feeds power from a plating conductor pattern formed on one surface side of the substrate portion that forms the opening,
In the solder resist layer formed on the entire surface of the substrate surface of the substrate, a recess is formed in which the bonding pad and the external connection terminal pad are exposed on the bottom surface, and the substrate portion for forming the opening and the bonding Remove the solder resist layer covering the substrate surface of the substrate portion between the edge of the pad and the periphery of the opening,
Next, the exposed substrate surface is covered with a mask, and a desired plating layer is applied to each upper surface of the bonding pad and the external connection terminal pad exposed on each bottom surface of the recess by electrolytic plating that feeds power from the plating conductor pattern. After forming
The mask is removed, and the plating conductor pattern appearing on the exposed substrate surface is removed by etching without etching the plating layers formed on the upper surfaces of the bonding pads and the external connection terminal pads. ,
Thereafter, an opening is formed by a router in the portion of the substrate where the substrate surface is exposed. 露出した基板面を覆うマスクとして、ドライフィルムを用いる請求項１記載の半導体装置用基板の製造方法。   2. The method for manufacturing a substrate for a semiconductor device according to claim 1, wherein a dry film is used as a mask covering the exposed substrate surface. 露出した基板面上に表れためっき用導体パターンのエッチングを、ボンディング用パッド及び外部接続端子用パッドの各上面に形成しためっき層をエッチングすることのないエッチング液に基板を浸漬して施す請求項１又は請求項２記載の半導体装置用基板の製造方法。   The etching of the conductive pattern for plating appearing on the exposed substrate surface is performed by immersing the substrate in an etching solution that does not etch the plating layer formed on each upper surface of the bonding pad and the external connection terminal pad. A method for manufacturing a semiconductor device substrate according to claim 1. ボンディング用パッド、導体パターン、外部接続端子用パッド及びめっき用導体パターンを銅又はその合金によって形成し、前記ボンディング用パッド及び外部接続端子用パッドの各上面に、下地めっき層としてのニッケルめっき層と、前記ニッケルめっき層上に形成された金めっき層とから成るめっき層を形成する請求項１〜３のいずれか一項記載の半導体装置用基板の製造方法。   A bonding pad, a conductor pattern, an external connection terminal pad and a plating conductor pattern are formed of copper or an alloy thereof, and a nickel plating layer as a base plating layer is formed on each upper surface of the bonding pad and the external connection terminal pad. The manufacturing method of the board | substrate for semiconductor devices as described in any one of Claims 1-3 which forms the plating layer which consists of a gold plating layer formed on the said nickel plating layer.
JP2005103410A 2005-03-31 2005-03-31 Method of manufacturing substrate of semiconductor apparatus Pending JP2006286847A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190341908A1 (en) * 2017-01-19 2019-11-07 Murata Manufacturing Co., Ltd. Electronic component

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000315751A (en) * 1999-03-01 2000-11-14 Sumitomo Metal Mining Co Ltd Manufacture of printed wiring board
JP2001358257A (en) * 2000-06-16 2001-12-26 Toppan Printing Co Ltd Method for manufacturing substrate for semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000315751A (en) * 1999-03-01 2000-11-14 Sumitomo Metal Mining Co Ltd Manufacture of printed wiring board
JP2001358257A (en) * 2000-06-16 2001-12-26 Toppan Printing Co Ltd Method for manufacturing substrate for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190341908A1 (en) * 2017-01-19 2019-11-07 Murata Manufacturing Co., Ltd. Electronic component

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