JP2006278866A - Manufacturing method of semiconductor device - Google Patents
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Description
本発明は、トランジスタ又はダイオード等の半導体素子の製法、特に電子線、γ線、中性子線又はイオン線等の放射線の照射による結晶欠陥領域の形成工程を含む半導体素子の製法に関する。 The present invention relates to a method for manufacturing a semiconductor element such as a transistor or a diode, and more particularly to a method for manufacturing a semiconductor element including a step of forming a crystal defect region by irradiation with radiation such as an electron beam, γ-ray, neutron beam or ion beam.
電子線、γ線、中性子線又はイオン線等の放射線照射を利用する半導体素子のライフタイム制御技術は、金(Au)又は白金(Pt)等の重金属拡散を利用するライフタイム制御技術に比較して、ライフタイムの制御及び再現に優れていることが知られている。特に、プロトン等の各種イオン線の照射を利用するライフタイム制御技術では、イオン線の照射によって形成される結晶欠陥領域がイオン線の飛程を中心として半導体基板の厚さ方向に限定される領域に集中的に形成されるため、高精度でライフタイムを制御することができる。 The lifetime control technology for semiconductor devices using radiation such as electron beam, gamma ray, neutron beam or ion beam is compared with the lifetime control technology using heavy metal diffusion such as gold (Au) or platinum (Pt). Thus, it is known that the lifetime is excellent in control and reproduction. In particular, in a lifetime control technology using irradiation of various ion beams such as protons, a region in which a crystal defect region formed by ion beam irradiation is limited to the thickness direction of the semiconductor substrate centering on the range of the ion beam Therefore, the lifetime can be controlled with high accuracy.
ところで、半導体素子を構成する半導体基板の全体にわたって前記の結晶欠陥領域を形成すると、結晶欠陥領域の発生によって半導体基板の内部抵抗が増大し、半導体素子の動作抵抗(例えばオン抵抗)が増大する問題が生じる。そこで、半導体基板の全体にわたって結晶欠陥領域を均一な深さで形成せずに、半導体基板の主面に沿う方向の特定領域で結晶欠陥を選択的に深く形成する技術が知られている。例えば、下記の特許文献1には、半導体素子の一方の電極(例えば裏面のコレクタ電極)側にアルミニウム等の金属の薄膜(アブゾーバ)を接触させ、更にその上に微細孔が多数形成されたステンレス等の金属のマスクを設け、ヘリウム(He)等の軽イオン線をマスクに向けて照射して、微細孔を除く他の領域を通過する軽イオン線の飛程よりも、微細孔を通過する軽イオン線の飛程を長くすることにより、半導体基板内に形成される結晶欠陥領域の深さ方向の位置を領域毎に異ならせた半導体素子の製造方法が開示されている。
By the way, when the crystal defect region is formed over the entire semiconductor substrate constituting the semiconductor element, the internal resistance of the semiconductor substrate increases due to the generation of the crystal defect region, and the operating resistance (for example, on-resistance) of the semiconductor element increases. Occurs. Therefore, a technique is known in which crystal defects are selectively deeply formed in a specific region in a direction along the main surface of the semiconductor substrate without forming the crystal defect region with a uniform depth over the entire semiconductor substrate. For example, in
特許文献1に記載された半導体素子のライフタイム制御を行なうには、図6に示すように、例えば金属メッキ等により半導体基板(1)の一方の主面(1a)上に数100μm〜数mmの厚さでアルミニウム(Al)等の金属膜(2)を形成し、その後、図7に示すように、金属膜(2)の露出面(2a)を部分的にエッチングして、複数の凹部(3)を備えた金属製のマスク(4)を形成する。その後、図8に示すように、凹部(3)のない相対的に厚い部分と凹部(3)を設けた相対的に薄い部分とを備えた金属製のマスク(4)を介してヘリウム(He)等の軽イオン線(5)を半導体基板(1)に照射して、半導体基板(1)内に結晶欠陥領域(6)を形成する。この結晶欠陥形成法は、製造上安価であり、生産性にも優れる。
In order to perform the lifetime control of the semiconductor element described in
しかしながら、半導体基板(1)の一方の主面(1a)に厚い金属膜(2)を金属メッキにより形成するとき、図6に示すように、半導体基板(1)の周縁側(1b)と中心側(1c)で金属膜(2)の厚さに差異が生じて、金属膜(2)の上面が浅いすり鉢状に形成されることが多い。これは、半導体基板(1)を浸漬したメッキ液中で半導体基板(1)の中心部より周辺部で多くの電流が流れて、半導体基板(1)の中心部より周辺部により厚いメッキ層が形成されるためである。メッキ液の組成、温度及び攪拌条件を選択することにより、メッキ厚の不均一性をある程度解消できるが、メッキ液中の全メッキ領域で電流値を均等に制御することは事実上不可能であって、半導体基板(1)の全面にわたり完全に均一な厚さのメッキ層を形成することはできない。 However, when a thick metal film (2) is formed on one main surface (1a) of the semiconductor substrate (1) by metal plating, the peripheral side (1b) and the center of the semiconductor substrate (1) are formed as shown in FIG. A difference occurs in the thickness of the metal film (2) on the side (1c), and the upper surface of the metal film (2) is often formed in a shallow mortar shape. This is because a larger amount of current flows in the peripheral part than the central part of the semiconductor substrate (1) in the plating solution in which the semiconductor substrate (1) is immersed, and a thicker plating layer is formed in the peripheral part than the central part of the semiconductor substrate (1). This is because it is formed. By selecting the plating solution composition, temperature, and stirring conditions, the plating thickness non-uniformity can be eliminated to some extent, but it is practically impossible to control the current value evenly in the entire plating area of the plating solution. Thus, it is not possible to form a plating layer having a completely uniform thickness over the entire surface of the semiconductor substrate (1).
図7に示すように、半導体基板(1)の周縁側(1b)と中心側(1c)とで厚さの異なる金属膜(2)の露出面(2a)に凹部(3)を設けて金属製のマスク(4)を形成し、マスク(4)を介して半導体基板(1)に軽イオン線(5)を照射すると、半導体基板(1)の周縁側(1b)と中心側(1c)とに軽イオン線(5)の飛程差が生じる。このため、図8に示すように、半導体基板(1)の周縁側(1b)に形成される結晶欠陥領域(6)の深さD1,D2と中心側(1c)に形成される結晶欠陥領域(6)の深さD3,D4とに差異が生じるため、半導体基板(1)の周縁側(1b)と中心側(1c)とに形成される半導体素子の電気的特性に差異が発生して、半導体素子の歩留まりが低下する問題があった。 As shown in FIG. 7, a recess (3) is provided on the exposed surface (2a) of the metal film (2) having different thicknesses on the peripheral side (1b) and the central side (1c) of the semiconductor substrate (1). When the semiconductor substrate (1) is irradiated with the light ion beam (5) through the mask (4), the peripheral side (1b) and the center side (1c) of the semiconductor substrate (1) are formed. And there is a difference in the range of the light ion wire (5). Therefore, as shown in FIG. 8, the depths D 1 and D 2 of the crystal defect region (6) formed on the peripheral side (1b) of the semiconductor substrate (1) and the crystal formed on the central side (1c). Since there is a difference between the depths D 3 and D 4 of the defect region (6), the electrical characteristics of the semiconductor elements formed on the peripheral side (1b) and the central side (1c) of the semiconductor substrate (1) are different. Has occurred, and the yield of semiconductor elements has been reduced.
そこで、本発明では、半導体基板の全体にわたって均等な電気的特性が得られる半導体素子の製法を提供することを目的とする。 Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor element that can obtain uniform electrical characteristics over the entire semiconductor substrate.
本発明による半導体素子の製法は、アルミニウム(Al)、銅(Cu)、白金(Pt)、鉛(Pb)又はそれらの合金から成る群から選択された1種又は2種以上の金属のメッキにより半導体基板(1)の少なくとも一方の主面(1a)に金属膜(2)を形成する工程と、金属膜(2)の露出面(2a)を機械的に切削又は研磨して金属膜(2)の露出面(2a)を平滑化する工程と、平滑化された金属膜(2)の露出面(2a)をエッチングして複数の凹部(3)を形成する工程と、複数の凹部(3)を形成した金属膜(2)を介して半導体基板(1)に放射線(5)を照射し、半導体基板(1)内に結晶欠陥領域(6)を形成する工程とを含む。 A method of manufacturing a semiconductor device according to the present invention includes plating one or more metals selected from the group consisting of aluminum (Al), copper (Cu), platinum (Pt), lead (Pb), or alloys thereof. A step of forming a metal film (2) on at least one main surface (1a) of the semiconductor substrate (1), and mechanically cutting or polishing the exposed surface (2a) of the metal film (2) (2 ) Smoothing the exposed surface (2a), etching the exposed surface (2a) of the smoothed metal film (2) to form a plurality of recesses (3), and a plurality of recesses (3 And irradiating the semiconductor substrate (1) with radiation (5) through the metal film (2) on which the crystal defect region (6) is formed, and forming a crystal defect region (6) in the semiconductor substrate (1).
メッキにより半導体基板(1)の一方の主面(1a)に不均一な厚さで金属膜(2)が形成されても、金属膜(2)の露出面(2a)を機械的に切削又は研磨して、半導体基板(1)の一方の主面(1a)から金属膜(2)の厚さを全体にわたり均一に平滑化する。その後、エッチングにより金属膜(2)の露出面(2a)上に複数の凹部(3)を形成したとき、金属膜(2)の露出面(2a)上に形成された凹部(3)の深さと凹部(3)の底面(3a)から半導体基板(1)の一方の主面(1a)までの厚さが半導体基板(1)の全主面にわたり実質的に均等となる。その後、凹部(3)を形成した金属膜(2)を介して半導体基板(1)に放射線(5)を照射するとき、金属膜(2)は、半導体基板(1)内の放射線(5)の飛程を制御するマスクとなり、半導体基板(1)の全面にわたり凹部(3)を形成した位置と凹部(3)を形成しない位置とで略均等な各深さD1,D2に結晶欠陥領域(6)を形成できる。このため、半導体素子の実質的に均等の電気的特性を半導体基板(1)の全面に付与して、半導体素子の歩留まりを向上できる。 Even if the metal film (2) is formed with an uneven thickness on one main surface (1a) of the semiconductor substrate (1) by plating, the exposed surface (2a) of the metal film (2) is mechanically cut or By polishing, the thickness of the metal film (2) from one main surface (1a) of the semiconductor substrate (1) is uniformly smoothed throughout. Thereafter, when a plurality of recesses (3) are formed on the exposed surface (2a) of the metal film (2) by etching, the depth of the recess (3) formed on the exposed surface (2a) of the metal film (2). The thickness from the bottom surface (3a) of the recess (3) to one main surface (1a) of the semiconductor substrate (1) is substantially uniform over the entire main surface of the semiconductor substrate (1). Thereafter, when the semiconductor substrate (1) is irradiated with radiation (5) through the metal film (2) formed with the recess (3), the metal film (2) is exposed to the radiation (5) in the semiconductor substrate (1). The crystal defects are formed at substantially equal depths D 1 and D 2 at positions where the recesses (3) are formed over the entire surface of the semiconductor substrate (1) and positions where the recesses (3) are not formed. Region (6) can be formed. Therefore, substantially uniform electrical characteristics of the semiconductor element can be imparted to the entire surface of the semiconductor substrate (1), thereby improving the yield of the semiconductor element.
本発明によれば、複数の半導体素子の電気的特性の均質化及び安定化を達成し、半導体素子の品質の信頼性を向上することができる。また、金属メッキ、切削又は研磨及びエッチングを含む各加工工程を利用して半導体基板内の放射線の飛程を制御する金属膜を形成できるので、生産性を向上することができる。 According to the present invention, homogenization and stabilization of electrical characteristics of a plurality of semiconductor elements can be achieved, and the reliability of the quality of the semiconductor elements can be improved. In addition, since a metal film that controls the range of radiation in the semiconductor substrate can be formed by using each processing step including metal plating, cutting or polishing, and etching, productivity can be improved.
以下、本発明による半導体素子の製法の実施の形態を図1〜図5について説明する。これらの図面では、図6〜図8に示す箇所と実質的に同一の部分には同一の符号を付し、その説明を省略する。 Hereinafter, an embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. In these drawings, parts that are substantially the same as those shown in FIGS. 6 to 8 are given the same reference numerals, and descriptions thereof are omitted.
本実施の形態の半導体素子の製法では、まず、不純物拡散やエピタキシャル成長等により複数の半導体素子を形成した半導体基板(1)を用意する。本実施の形態では、半導体素子は、例えば絶縁ゲート型パイポーラトランジスタ(IGBT)であるが、これに限定されない。したがって、半導体基板(1)内に形成されたPN接合の構造、絶縁膜及び各種電極等の詳細な図示は省略する。 In the method of manufacturing a semiconductor element of this embodiment, first, a semiconductor substrate (1) on which a plurality of semiconductor elements are formed by impurity diffusion, epitaxial growth, or the like is prepared. In the present embodiment, the semiconductor element is, for example, an insulated gate bipolar transistor (IGBT), but is not limited thereto. Therefore, detailed illustration of the structure of the PN junction, the insulating film, various electrodes, and the like formed in the semiconductor substrate (1) is omitted.
続いて、図6に示すように、例えばアルミニウム(Al)から成る金属膜(2)を金属メッキにより半導体基板(1)の一方の主面(1a)上に例えば500μm程度の厚さに形成する。形成された直後の金属膜(2)の厚さは、図6に破線で示すように半導体基板(1)の周縁側(1b)と中心側(1c)とで相違する。即ち、半導体基板(1)の周縁側(1b)では金属膜(2)の厚さが相対的に厚く、半導体基板(1)の中心側(1c)では金属膜(2)の厚さが相対的に薄く形成される。例えば絶縁ゲート型パイポーラトランジスタ(IGBT)を半導体素子として製造するとき、金属膜(2)がエミッタ電極の露出面上に積層して形成される。 Subsequently, as shown in FIG. 6, a metal film (2) made of, for example, aluminum (Al) is formed on one main surface (1a) of the semiconductor substrate (1) to a thickness of, for example, about 500 μm by metal plating. . The thickness of the metal film (2) immediately after the formation is different between the peripheral side (1b) and the central side (1c) of the semiconductor substrate (1) as shown by a broken line in FIG. That is, the thickness of the metal film (2) is relatively large on the peripheral side (1b) of the semiconductor substrate (1), and the thickness of the metal film (2) is relatively large on the center side (1c) of the semiconductor substrate (1). Thinly formed. For example, when an insulated gate bipolar transistor (IGBT) is manufactured as a semiconductor element, the metal film (2) is formed on the exposed surface of the emitter electrode.
次に、金属膜(2)の露出面(2a)に機械的な切削加工、研磨加工又は切削研磨加工を施して、図1に示すように、金属膜(2)の露出面(2a)を平滑化して、金属膜(2)の厚さを均一にする。金属膜(2)の露出面(2a)を平滑化する際に、図2に示すように、回転止め(7b)により支持台(7)との相対的回転又は相対的移動を阻止して、支持台(7)の平坦な支持面(7a)上に半導体基板(1)を配置する。その後、金属膜(2)の露出面(2a)の少なくとも一部又は全面に接触させた切削具(8)又は研磨具を露出面(2a)に押圧し、相対的に回転し又は相対的に移動して、露出面(2a)の切削又は研磨を行う。例えば、切削具(8)又は研磨具を金属膜(2)に接触させ、押圧しながら、切削具(8)又は研磨具の水平面内で左右、前後に移動し又は回転運動、公転運動若しくは回転公転運動を行う。これにより、金属膜(2)が全面にわたり切削又は研磨されて、金属膜(2)の厚さが半導体基板(1)の一方の主面(1a)全体にわたって均一化される。切削加工は、グラインダ研削、ラッピング、ホーニング又は砥石による機械加工がある。研磨加工は、バフ研磨である。金属膜(2)の露出面(2a)を平滑化するには、半導体基板(1)の中心部と外周部での金属膜(2)の高さの差を20μm以下、好ましくは、10μm以下、更に好ましくは5μm以下とするのが好ましい。 Next, the exposed surface (2a) of the metal film (2) is subjected to mechanical cutting, polishing or cutting / polishing so that the exposed surface (2a) of the metal film (2) is formed as shown in FIG. Smoothing to make the thickness of the metal film (2) uniform. When smoothing the exposed surface (2a) of the metal film (2), as shown in FIG. 2, the rotation stop (7b) prevents relative rotation or relative movement with the support base (7), and The semiconductor substrate (1) is placed on the flat support surface (7a) of the support base (7). Thereafter, the cutting tool (8) or the polishing tool brought into contact with at least a part or the whole of the exposed surface (2a) of the metal film (2) is pressed against the exposed surface (2a) and relatively rotated or relatively rotated. Move to cut or polish the exposed surface (2a). For example, when the cutting tool (8) or the polishing tool is brought into contact with the metal film (2) and pressed, the cutting tool (8) or the polishing tool moves left and right, back and forth in the horizontal plane, or rotates, revolves or rotates. Perform a revolving movement. Thereby, the metal film (2) is cut or polished over the entire surface, and the thickness of the metal film (2) is made uniform over the entire one main surface (1a) of the semiconductor substrate (1). Cutting includes grinder grinding, lapping, honing, or machining by a grindstone. The polishing process is buffing. In order to smooth the exposed surface (2a) of the metal film (2), the difference in height of the metal film (2) between the central portion and the outer peripheral portion of the semiconductor substrate (1) is 20 μm or less, preferably 10 μm or less. More preferably, the thickness is 5 μm or less.
その後、図3に示すように、金属膜(2)とは異なる材質、例えば樹脂から成り且つ多数の開口部(9a)を有するマスク(9)を平滑化された金属膜(2)の露出面(2a)上に被着し、マスク(9)の開口部(9a)を通じて金属膜(2)を選択的にエッチングする。これにより、樹脂製のマスク(9)の開口部(9a)に対応する金属膜(2)の露出面(2a)で金属膜(2)が薄くエッチングされ、図4に示すように均等な深さの複数の凹部(3)が形成され、相対的に肉厚の部分と相対的に肉薄の部分を有する金属製のマスク(4)が形成される。凹部(3)の底面(3a)は、半導体基板(1)の一方の主面(1a)に達せず、凹部(3)の底面(3a)と半導体基板(1)の一方の主面(1a)との間に薄膜部(3b)を形成する。また、凹部(3)は、コ字形、U字形、V字形等の種々の断面形状を有する凹み、窪み、溝、溝部、溝条、蟻溝、切欠、切欠部、穴(ほぞ穴)等の種々の断面形状、幅及び長さの凹部を含む。なお、本実施の形態では、一つの半導体素子に対して少なくとも1個の肉厚部分と肉薄部分が対向するように金属膜(2)をエッチング加工する。 Thereafter, as shown in FIG. 3, the exposed surface of the metal film (2) obtained by smoothing a mask (9) made of a material different from that of the metal film (2), for example, resin and having a large number of openings (9a). (2a) is deposited, and the metal film (2) is selectively etched through the opening (9a) of the mask (9). As a result, the metal film (2) is thinly etched at the exposed surface (2a) of the metal film (2) corresponding to the opening (9a) of the resin mask (9), and the uniform depth as shown in FIG. A plurality of concave portions (3) are formed, and a metal mask (4) having a relatively thick portion and a relatively thin portion is formed. The bottom surface (3a) of the recess (3) does not reach one main surface (1a) of the semiconductor substrate (1), and the bottom surface (3a) of the recess (3) and one main surface (1a) of the semiconductor substrate (1) ) To form a thin film portion (3b). In addition, the concave portion (3) has various cross-sectional shapes such as U-shape, U-shape, V-shape, etc., such as dents, depressions, grooves, grooves, grooves, dovetails, notches, notches, holes (mortises), etc. Includes recesses of various cross-sectional shapes, widths and lengths. In the present embodiment, the metal film (2) is etched so that at least one thick portion and thin portion face each other with respect to one semiconductor element.
図4に示す樹脂製のマスク(9)を除去した後、図5に示すように、複数の凹部(3)を形成した金属膜(2)を介して半導体基板(1)にプロトン又はヘリウム(He)等の軽イオン線(5)(放射線)を照射する。これにより、金属膜(2)の相対的に肉厚の部分、即ち凹部(3)を除く部分を通じて照射された軽イオン線(5)は半導体基板(1)の比較的浅い位置に到達し、金属膜(2)の相対的に肉薄の部分、即ち凹部(3)を通じて照射された軽イオン線(5)は半導体基板(1)の比較的深い位置に到達する。この結果、金属膜(2)の凹部(3)を除く部分に対応する半導体基板(1)の一方の主面(1a)から比較的浅い深さD1と、金属膜(2)の凹部(3)に対応する半導体基板(1)の一方の主面(1a)から比較的深い深さD2に結晶欠陥領域(6)が形成される。更に、金属膜(2)を除去して半導体基板(1)を複数個に分割すれば、互いに同一の電気的特性を有する複数の半導体素子が得られる。 After removing the resin mask (9) shown in FIG. 4, as shown in FIG. 5, protons or helium (as shown in FIG. 5) are applied to the semiconductor substrate (1) through the metal film (2) having a plurality of recesses (3). Irradiate a light ion beam (5) (radiation) such as He). Thereby, the relatively thick portion of the metal film (2), that is, the light ion beam (5) irradiated through the portion excluding the recess (3) reaches a relatively shallow position of the semiconductor substrate (1), The light ion beam (5) irradiated through the relatively thin portion of the metal film (2), that is, the recess (3), reaches a relatively deep position of the semiconductor substrate (1). As a result, a relatively shallow depth D 1 from one main surface (1a) of the semiconductor substrate (1) corresponding to the portion of the metal film (2) excluding the recess (3), and the recess of the metal film (2) ( one main surface (1a) from a relatively deep depth D 2 to the crystal defect region of the semiconductor substrate (1) corresponding to 3) (6) is formed. Further, by removing the metal film (2) and dividing the semiconductor substrate (1) into a plurality of parts, a plurality of semiconductor elements having the same electrical characteristics can be obtained.
本実施の形態では、半導体基板(1)の一方の主面(1a)を金属メッキしてアルミニウム(Al)から成る金属膜(2)を形成した後、金属膜(2)の露出面(2a)に機械的切削加工を施すことにより、半導体基板(1)の一方の主面(1a)全体を平滑化して金属膜(2)の厚さを均一化する。その後、厚さが均一な金属膜(2)の露出面(2a)をエッチングして凹部(3)を形成すると、金属膜(2)の露出面(2a)上に形成された凹部(3)の深さが半導体基板(1)の周縁側(1b)と中心側(1c)とで均等となる。更に、凹部(3)が形成された金属膜(2)を介して半導体基板(1)にプロトン又はヘリウム(He)等の軽イオン線(5)を照射することにより、金属膜(2)が半導体基板(1)内の軽イオン線(5)の飛程を制御するマスクとして作用し、半導体基板(1)の周縁側(1b)と中心側(1c)で均等な深さD1,D2に結晶欠陥領域(6)を形成できるので、半導体基板(1)の周縁側(1b)及び中心側(1c)を含む半導体基板(1)の全面に均等な電気的特性の半導体素子を形成して、半導体素子の歩留まりを向上することができる。また、半導体基板(1)内の軽イオン線(5)の飛程を制御する金属製のマスク(4)を金属メッキ、切削又は研磨及びエッチングを含む加工技術を利用して安価に形成でき且つ生産性を向上することができる利点がある。 In the present embodiment, one main surface (1a) of the semiconductor substrate (1) is metal-plated to form a metal film (2) made of aluminum (Al), and then the exposed surface (2a of the metal film (2)) ) Is subjected to mechanical cutting, so that the entire one main surface (1a) of the semiconductor substrate (1) is smoothed to make the thickness of the metal film (2) uniform. Then, etching the exposed surface (2a) of the metal film (2) with a uniform thickness to form the recess (3), the recess (3) formed on the exposed surface (2a) of the metal film (2) Are equal on the peripheral side (1b) and the central side (1c) of the semiconductor substrate (1). Further, by irradiating the semiconductor substrate (1) with a light ion beam (5) such as proton or helium (He) through the metal film (2) in which the recess (3) is formed, the metal film (2) Acts as a mask for controlling the range of the light ion beam (5) in the semiconductor substrate (1), and has a uniform depth D 1 , D on the peripheral side (1b) and the central side (1c) of the semiconductor substrate (1). Since a crystal defect region (6) can be formed in 2 , a semiconductor element having uniform electrical characteristics is formed on the entire surface of the semiconductor substrate (1) including the peripheral side (1b) and the central side (1c) of the semiconductor substrate (1). Thus, the yield of semiconductor elements can be improved. Further, the metal mask (4) for controlling the range of the light ion beam (5) in the semiconductor substrate (1) can be formed at low cost by using a processing technique including metal plating, cutting or polishing and etching, and There is an advantage that productivity can be improved.
本発明の実施態様は前記の実施の形態に限定されず、種々の変更が可能である。例えば、上記の実施の形態では半導体基板(1)の一方の主面(1a)上に金属膜(2)を形成するが、他方の主面(1d)上に金属膜(2)を形成してもよい。また、上記の実施の形態では金属膜(2)を構成する金属としてアルミニウム(Al)を選択するが、アルミニウム(Al)、銅(Cu)、白金(Pt)又は鉛(Pb)又はこれらの合金から選択することができる。また、切削加工、バフ加工、バレル加工等の種々の機械的研磨加工又はCMP(Chemical Mechanical Polishing:化学的・機械的研磨)加工等により金属膜(2)の露出面(2a)を平滑化することもできる。更に、メッキにより、金属膜(2)の露出面(2a)に凹凸部、陥没部、ボイド、突起が形成される場合にも、機械的な切削又は研磨による平滑化は有効である。また、金属膜(2)の下方の半導体基板(1)に達する金属膜(2)の凹部(3)を形成して、金属膜(2)の底面と半導体基板(1)との間に薄膜部(3b)を形成しなくてもよい。 Embodiments of the present invention are not limited to the above-described embodiments, and various modifications can be made. For example, in the above embodiment, the metal film (2) is formed on one main surface (1a) of the semiconductor substrate (1), but the metal film (2) is formed on the other main surface (1d). May be. In the above embodiment, aluminum (Al) is selected as the metal constituting the metal film (2), but aluminum (Al), copper (Cu), platinum (Pt), lead (Pb), or alloys thereof. You can choose from. Also, the exposed surface (2a) of the metal film (2) is smoothed by various mechanical polishing processes such as cutting, buffing, barreling, or CMP (Chemical Mechanical Polishing). You can also. Further, smoothing by mechanical cutting or polishing is also effective when irregularities, depressions, voids, and protrusions are formed on the exposed surface (2a) of the metal film (2) by plating. Further, a recess (3) of the metal film (2) reaching the semiconductor substrate (1) below the metal film (2) is formed, and a thin film is formed between the bottom surface of the metal film (2) and the semiconductor substrate (1). The part (3b) may not be formed.
本発明は、半導体基板内に結晶欠陥領域を有する半導体素子の製造又は電子線の放射量の制御に良好に適用できる。 The present invention can be suitably applied to the manufacture of a semiconductor element having a crystal defect region in a semiconductor substrate or the control of the amount of electron beam radiation.
(1)・・半導体基板、 (1a)・・一方の主面、 (1b)・・周縁側、 (1c)・・中心側、 (1d)・・他方の主面、 (2)・・金属膜、 (2a)・・露出面、 (3)・・凹部、 (3a)・・底面、 (3b)・・薄膜部、 (5)・・軽イオン線(放射線)、 (6)・・結晶欠陥領域、 (7)・・支持台、 (7a)・・支持面、 (7b)・・回転止め、 (8)・・切削具、 (9)・・マスク、 (9a)・・開口部、 (1) ・ ・ Semiconductor substrate, (1a) ・ ・ One main surface, (1b) ・ ・ Rim, (1c) ・ ・ Center side, (1d) ・ ・ The other main surface, (2) ・ Metal Membrane, (2a) ·· Exposed surface, (3) ·· Concavity, (3a) ·· Bottom surface, (3b) ·· Thin film portion, (5) ·· Light ion beam (radiation), (6) ·· Crystal Defective area, (7) ・ ・ Support base, (7a) ・ ・ Support surface, (7b) ・ ・ Rotation stop, (8) ・ ・ Cutting tool, (9) ・ ・ Mask, (9a) ・ ・ Opening,
Claims (4)
該金属膜の露出面を機械的に切削又は研磨して前記金属膜の露出面を平滑化する工程と、
平滑化した前記金属膜の露出面をエッチングして、前記金属膜に複数の凹部を形成する工程と、
複数の前記凹部を形成した前記金属膜を介して前記半導体基板に放射線を照射して、前記半導体基板内に結晶欠陥領域を形成する工程とを含むことを特徴とする半導体素子の製法。 At least one main surface of the semiconductor substrate is plated with one or more metals selected from the group consisting of aluminum (Al), copper (Cu), platinum (Pt), lead (Pb), or alloys thereof. Forming a metal film;
Smoothing the exposed surface of the metal film by mechanically cutting or polishing the exposed surface of the metal film;
Etching the exposed surface of the smoothed metal film to form a plurality of recesses in the metal film;
Irradiating the semiconductor substrate with radiation through the metal film in which a plurality of the recesses are formed to form a crystal defect region in the semiconductor substrate.
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JP2010129798A (en) * | 2008-11-28 | 2010-06-10 | Sanken Electric Co Ltd | Semiconductor device and method of manufacturing the same |
KR20210011142A (en) * | 2019-07-22 | 2021-02-01 | 김종명 | Electrostatic chuck for adsorbing substrate |
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JP2010129798A (en) * | 2008-11-28 | 2010-06-10 | Sanken Electric Co Ltd | Semiconductor device and method of manufacturing the same |
KR20210011142A (en) * | 2019-07-22 | 2021-02-01 | 김종명 | Electrostatic chuck for adsorbing substrate |
KR102318925B1 (en) | 2019-07-22 | 2021-10-27 | 김종명 | Electrostatic chuck for adsorbing substrate |
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