JP5460975B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device capable of realizing ohmic contact of electrodes formed on a semiconductor element made of silicon carbide (hereinafter referred to as SiC).

  Conventionally, when a vertical power device is formed on an SiC substrate, an ohmic that reduces the contact resistance between the SiC substrate and the drain electrode when forming an electrode for connecting the device to an electric circuit or the like, particularly a drain electrode. It is desired to form an electrode.

  As a method of forming the ohmic electrode, in order to obtain an ohmic electrode that has a low resistance (potential barrier is small) connection to both n-type SiC and p-type SiC in a semiconductor device composed of a SiC substrate, There has been reported a method of forming a Ni silicide film on a SiC substrate by performing a silicide process in which Ni is vapor-deposited on a SiC substrate, followed by heat treatment (see, for example, Non-Patent Document 1).

  Further, as an ohmic electrode formation method, there is a method of forming an ohmic electrode by forming an impurity doped layer on a SiC substrate, forming a metal thin film on the impurity doped layer, and irradiating laser light from the upper surface of the metal thin film. It has been proposed (see Patent Document 1).

  Specifically, after forming an electrode on the surface side of the SiC substrate, the electrode on the surface side of the SiC substrate is protected by a resin film. Subsequently, the back surface of the SiC substrate is thinned, and impurity ions are implanted into the back surface of the SiC substrate. And after activating an impurity by high temperature heat processing, the metal thin film as an electrode is formed in the back surface of a SiC substrate, and the ohmic electrode is formed by performing the laser beam irradiation on the said metal thin film.

  Further, as an electrode forming surface treatment of the ohmic electrode, there has been proposed a method of forming an electrode after forming fine irregularities on the exposed surface by subjecting the exposed surface of the SiC substrate to polishing treatment or laser light irradiation ( Patent Document 2).

  Specifically, an electrode is formed on the surface side of the SiC substrate, and the electrode on the surface side of the SiC substrate is protected by a resin film. Subsequently, the back surface of the SiC substrate is thinned, and the back surface of the thinned SiC substrate is subjected to polishing treatment or laser light irradiation to form fine irregularities on the back surface of the SiC substrate. Thereafter, a metal thin film as an electrode is formed on the back surface of the SiC substrate on which fine irregularities are formed.

  However, in the technique disclosed in Non-Patent Document 1, Ni is used as an electrode material to generate Ni silicide, which is a Si compound of Ni and SiC, so that sintering at 800 ° C. or higher is required.

  Further, in the method described in Patent Document 1, laser light irradiation is performed in forming an ohmic electrode, but a layer doped with impurities is required on the back surface of the SiC substrate. In order to activate this impurity, it is necessary to perform heat treatment at a relatively high temperature after forming the impurity doped layer. In the ion implantation method, heat treatment is performed on the SiC substrate at a high temperature of about 1600 ° C. to 1700 ° C., for example.

  Therefore, in these methods, the surface electrode formed on the surface side of the SiC substrate in the step of activating the impurities by high-temperature heat treatment may be thermally damaged, which may cause various problems in device use. It was.

  In addition, in the case of passing a current in the front and back direction like a vertical power device, it is preferable to make the SiC substrate thin in order to reduce the operating resistance. However, when the SiC substrate is thinned to a thickness that makes it difficult to perform high-temperature heat treatment, there is a problem in that an ohmic electrode cannot be formed on the back surface of the SiC substrate because heat treatment cannot be performed.

  Therefore, Patent Document 3 proposes a method of irradiating a SiC substrate with laser light as a method of activating the impurity doped layer without heat treatment at a high temperature. The process of forming the back electrode when this method is used is as follows.

First, an electrode is formed on the surface side of a SiC substrate on which a vertical element is formed. Next, the surface of the SiC substrate is protected by the resin film, and the back surface of the SiC substrate is thinned. Then, ion implantation of impurities is performed on the back surface of the SiC substrate, and laser light irradiation is performed on the back surface of the SiC substrate. Thereafter, an electrode is formed by forming a metal thin film on the back surface of the SiC substrate.
Seisuke Imai and 1 other, "29p-ZM-14, n-type and p-type SiC simultaneous contact using Ni salicide process", Proceedings of the 51st Joint Conference on Applied Physics, Japan Society of Applied Physics, March 28, 2004, first volume, p. 437 JP 2004-158702 A JP 2006-41248 A JP 2002-289550 A

  However, in the method using ion implantation as shown in Patent Document 3, there is a problem that the ion implantation process itself is expensive in addition to the expensive ion implantation apparatus. Therefore, it is desirable to obtain an ohmic electrode without performing an ion implantation process.

  The present invention has been made in view of the above points, and an object thereof is to provide a method of manufacturing a semiconductor device capable of forming an ohmic electrode by a low temperature process without using an ion implantation step.

In order to achieve the above object, in the invention according to claim 1, a polishing step of preparing a semiconductor substrate (1) and polishing the back surface of the semiconductor substrate (1) to form irregularities on the back surface, and polishing After the step, a metal thin film forming step for forming a metal thin film (110) for forming silicide on the back surface of the semiconductor substrate (1), and after the metal thin film forming step, the metal thin film is irradiated with laser light (50). The first electrode (11) is formed by an electrode forming step, and in the electrode forming step, the laser beam (50) is irradiated with a solid-state laser and the wavelength of the laser beam (50) is set to 355 nm. Laser light as a laser output in a range where the product of photon energy (eV) and laser output (mJ / cm ² ) in light is 1000 (eV · mJ / cm ² ) or more and 8000 (eV · mJ / cm ² ) or less The irradiation is performed for a time during which the silicide layer (111) is formed on the metal thin film .

  By forming the first electrode in such a process order, the silicide layer (111) is generated on the first electrode (11) on the semiconductor substrate (1) without performing high temperature treatment on the semiconductor substrate (1). can do. Therefore, it is possible to make the first electrode (11) an ohmic electrode without using an ion implantation step and by a low temperature process.

The invention described in claim 1 is characterized in that, in the polishing step, the back surface is polished so that the roughness (Ra) of the back surface of the semiconductor substrate is 10 nm or more and 500 nm or less.

  As described above, the surface roughness (Ra) is set to be 10 nm or more and 500 nm or less when forming fine irregularities. For this reason, a better ohmic junction can be obtained.

The invention according to claim 2 is characterized in that a metal containing any one or more of Ni, Ti, Mo, and W is formed as the metal thin film during the metal thin film forming step.

Thus, a metal containing any one or more of Ni, Ti, Mo, and W can be used as the metal used to form the silicide layer (111). The thickness of such a metal thin film can be set to, for example, 10 nm as described in claim 3 .

Furthermore, when the semiconductor substrate (1) is prepared, as described in claim 5 , a vertical semiconductor in which an element structure and a second electrode (10) are formed on the main surface side of the semiconductor substrate (1). It is also possible to prepare a device in which an element is formed and polish the back surface (1b) of the semiconductor substrate (1) after the second electrode (10) is formed.

  As described above, since the first electrode can be formed by a low temperature process, even if an element structure or the like is formed on the semiconductor substrate before the first electrode (11) is formed, the element structure or the like is not heated. You can avoid damaging the target.

In this case, as described in claim 6 , it is preferable to form a protective film (40) covering the second electrode on the main surface side of the semiconductor substrate after forming the second electrode. Thereby, formation of the 1st electrode (11) can be performed, protecting the main surface side of a semiconductor substrate.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments shown in the drawings will be described below. FIG. 1 shows a cross-sectional view of a planar MOSFET (vertical power MOSFET) manufactured by the method of manufacturing an SiC semiconductor device shown in the present embodiment. This device is suitable when applied to, for example, an inverter. The structure of the vertical power MOSFET will be described with reference to FIG.

An n ⁺ type semiconductor substrate (hereinafter referred to as an n ⁺ type substrate) 1 has a top surface as a main surface 1a and a bottom surface opposite to the main surface 1a as a back surface 1b, and is made of single crystal SiC. The thickness of the n ⁺ type substrate 1 is 350 μm. On the main surface 1a of the n ⁺ -type substrate 1, n ⁺ -type substrate 1 n is constituted by SiC having a lower dopant concentration than ^- -type epitaxial layer (hereinafter, n ^- referred -type epitaxial layer) 2 is stacked Has been.

A p ⁻ type base region 3 a and a p ⁻ type base region 3 b (hereinafter referred to as p ⁻ type base regions 3 a and 3 b) having a predetermined depth are spaced apart from each other in a predetermined region in the surface layer portion of the n ⁻ type epi layer 2. Is formed. In addition, deep base layers 30a and 30b having a partially increased thickness are formed in the base regions 3a and 3b. The deep base layers 30a and 30b are formed in portions that do not overlap with the n ⁺ type source regions 4a and 4b, and the deep base layers 30a and 30b are formed thick in the p ⁻ type base regions 3a and 3b. The formed portion has a higher impurity concentration than the thin portion where the deep base layer 30a is not formed.

Such deep base layers 30a and 30b reduce the thickness of the n ⁻ type epi layer 2 below the deep base layers 30a and 30b (the n ⁺ type semiconductor n ⁺ type substrate 1 and the deep base layers 30a and 30b The electric field strength can be increased and the avalanche breakdown can be facilitated.

Further, p ^- is a predetermined region in the surface layer of type base region 3a, the p ^- type base region shallower n ⁺ -type source region 4a than 3a is formed, p ^- in a predetermined region in the surface layer of type base region 3b Are formed with an n ⁺ type source region 4b shallower than the p ⁻ type base region 3b.

Further, n ⁻ -type layer 5a and n ⁺ -type layer 5b are formed on the surface of n ⁻ -type epi layer 2 and p ⁻ -type base regions 3a and 3b between n ⁺ -type source region 4a and n ⁺ -type source region 4b. An n ⁻ -type SiC layer 5 made of is extended. That is, the n ⁻ type SiC layer 5 is arranged so as to connect the source regions 4a and 4b and the n ⁻ type epi layer 2 at the surface portions of the p ⁻ type base regions 3a and 3b. This n ⁻ -type SiC layer 5 functions as a channel forming layer on the device surface during device operation. Hereinafter, the n ⁻ -type SiC layer 5 is referred to as a surface channel layer.

The dopant concentration of the n ⁻ type layer 5a disposed on the p ⁻ type base regions 3a and 3b in the surface channel layer 5 is as low as about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ^−3. And the concentration is lower than the dopant concentration of the n ⁻ -type epi layer 2 and the p ⁻ -type base regions 3a and 3b. Thereby, low on-resistance is achieved.

Recesses 6a and 6b are formed in the surface portions of the p ⁻ type base regions 3a and 3b and the n ⁺ type source regions 4a and 4b.

A gate insulating film (silicon oxide film) 7 is formed on the upper surface of the surface channel layer 5 and the upper surfaces of the n ⁺ -type source regions 4a and 4b. Further, a gate electrode 8 is formed on the gate insulating film 7. The gate electrode 8 is covered with an insulating film 9. A silicon oxide film is used as the insulating film 9. A source electrode 10 is formed thereon, and the source electrode 10 is in contact with the n ⁺ type source regions 4a and 4b and the p ⁻ type base regions 3a and 3b. A drain electrode 11 is formed on the back surface 1 b of the n ⁺ type substrate 1. The drain electrode 11 is in ohmic contact with the back surface 1 b of the n ⁺ type substrate 1.

In the n ⁻ -type epi layer 2, the portion sandwiched between the p ⁻ -type base regions 3 a and 3 b constitutes a so-called J-FET portion. The source electrode 10 corresponds to the second electrode of the present invention, and the drain electrode 11 corresponds to the first electrode of the present invention.

  Next, a method for manufacturing the vertical power MOSFET shown in FIG. 1 will be described. However, since the basic manufacturing method of the vertical power MOSFET according to the present embodiment is the same as the conventional method, only the method for forming the drain electrode 11 different from the conventional method will be described.

  FIG. 2 is a diagram showing a manufacturing process of the drain electrode 11 in the vertical power MOSFET shown in FIG. In FIG. 2, the device structure of the vertical power MOSFET is not shown for simplification.

First, a device in which the device shown in FIG. 1 is formed on the surface side of the n ⁺ type substrate 1, that is, a device in which the source electrode 10 excluding the drain electrode 11 is formed is prepared.

Then, the process shown in FIG. Specifically, the n ⁺ type substrate 1 is thinned, and the thickness of the n ⁺ type substrate 1 is 350 μm. Then, a protective film 40 that covers the source electrode 10 is formed on the main surface 1 a side of the n ⁺ -type substrate 1. The protective film 40 protects the surface electrode formed on the n ⁺ -type substrate 1, that is, the source electrode 10, and a resin material such as polyimide is used, for example. The front surface side of the n ⁺ type substrate 1 is fixed by the protective film 40, and the drain electrode 11 is formed on the back surface 1b of the n ⁺ type substrate 1 by the following process.

Next, a polishing process is performed on the back surface 1b of the n ⁺ type substrate 1 (polishing step). In this embodiment, grinding is adopted as a polishing method. Grinding is a polishing method performed by rotating a grindstone and pressing the grindstone against a surface to be processed. By this polishing method, fine irregularities are formed on the back surface 1 b of the n ⁺ type substrate 1. At this time, the surface roughness Ra of the back surface 1b of the n ⁺ type substrate 1 is set to be 10 nm or more and 500 nm or less. The reason for this will be described later.

In the subsequent step shown in FIG. 2B, a metal thin film 110 is formed on the back surface 1b of the n ⁺ -type substrate 1 that has been made uneven in the step shown in FIG. 2A (metal thin film forming step). For example, by depositing Ni on the n ⁺ -type substrate 1 on the back surface 1b, forming a metal thin film 110 on the back surface 1b n ⁺ -type substrate 1. At this time, the thickness of the metal thin film 110 is set so as to correspond to the surface roughness Ra, for example, 10 nm or more.

In the step shown in FIG. 2C, the metal thin film 110 is irradiated with laser light (electrode formation step). Specifically, an LD-pumped solid-state laser (fundamental wavelength 1064 nm) is employed, and the laser beam 51 of the LD-pumped solid-state laser is scanned on the back surface 1b of the n ⁺ -type substrate 1, preferably by scanning or masking. The laser beam 51 is irradiated only on the portion where the is formed. Thereby, the metal (Ni in the present embodiment) constituting the metal thin film 110 and the Si constituting the n ⁺ type substrate 1 are reacted to generate the silicide layer 111 shown in FIG. . At this time, and the conditions such as the photon energy and the product of the laser power of the LD pumped solid laser is 1000eV · mJ / cm ² or more and 8000eV · mJ / cm ² or less. The reason for this will be described later.

  As described above, the vertical power MOSFET shown in FIG. 1 is completed. By such a process, the drain electrode 11 including the silicide layer 111 can be formed, and the drain electrode 11 can be an ohmic electrode by a low temperature process without using an ion implantation process.

  Here, the reason why the product of the surface roughness Ra in the polishing process shown in FIG. 2A and the photon energy and the laser output in the laser light irradiation process shown in FIG. .

First, the polishing process shown in FIG. 2A will be described. The inventors experimentally set the surface roughness Ra of the back surface 1b of the n ⁺ -type substrate 1 in the polishing process to five levels of 0.5 nm, 1 nm, 8 nm, 50 nm, and 200 nm, and the metal thin film at each level. 110 was formed, and the laser beam irradiation process shown in FIG. And when resistance measurement was performed about the sample which formed the drain electrode 11 by changing surface roughness Ra in this way, the result shown in FIG. 3 was obtained.

As shown in this figure, when the surface roughness Ra of the back surface 1b of the n ⁺ type substrate 1 is 0.5 nm, the drain electrode 11 has a Schottky junction. Further, when Auger analysis was performed in this case, Ni silicide was not generated.

On the other hand, when the surface roughness Ra of the back surface 1b of the n ⁺ -type substrate 1 is 1 nm or more, the resistance value is lower than when the surface roughness Ra is 0.5 nm. When Auger analysis was performed in the same manner as described above, a result that Ni silicide was generated when the surface roughness Ra was 1 nm or more was obtained, and the drain electrode 11 was in ohmic contact with the n ⁺ type substrate 1. I found out. In particular, when the surface roughness Ra of the back surface 1b of the n ⁺ type substrate 1 is 50 nm or 200 nm, a good ohmic electrode having a low resistance on the order of 10 ⁻³ Ω · cm ⁻² to 10 ⁻⁴ Ω · cm ⁻² is used. I was able to get it.

Based on these results, a good ohmic electrode can be obtained by setting the surface roughness Ra of the back surface 1b of the n ⁺ type substrate 1 to 1 nm or more. However, if the surface roughness Ra is less than 10 nm from the results shown in FIG. 3, the resistance value becomes high even if the surface is an ohmic junction. Further, since the surface roughness Ra has a width of about ± 20% for each value, it is preferable to set 10 nm considering the width of 20% as a lower limit value when the surface roughness Ra is measured at 8 nm. . Further, an ohmic electrode may be obtained with any value as long as the surface roughness Ra is 1 nm or more, but it is possible to achieve a surface roughness Ra exceeding 500 nm for the n ⁺ type substrate 1. Have difficulty. For this reason, it is preferable to make 500 nm which can be actually manufactured into an upper limit.

For this reason, as described above, the surface roughness Ra of the back surface 1b of the n ⁺ type substrate 1 is set to 10 nm or more and 500 nm or less. As can be seen from the results of FIG. 3, when the surface roughness Ra is 50 nm or more and 200 nm or less, a better ohmic junction can be obtained.

Next, the laser beam irradiation process shown in FIG. In the laser irradiation process shown in FIG. 2 (c), the present inventors use an LD-excited solid laser having a fundamental wavelength of 1064 nm, and a second harmonic (532 nm) and a third harmonic (355 nm) using a wavelength conversion adapter. ) The fourth harmonic wave (266 nm) was generated, and the wavelength of the laser beam 51 was set to four levels of 1064 nm, 532 nm, 355 nm, and 266 nm, and the drain electrode 11 was formed at each level. Then, to the intensity of the laser beam 51 and ^{200mJ / cm 2 ~1000mJ / cm 2} . When the resistance of the drain electrode 11 thus formed was measured, the result shown in FIG. 4 was obtained.

As shown in this figure, it can be seen that the resistance value of the laser beams having wavelengths of 1064 nm, 532 nm, 355 nm, and 266 nm decreases as the laser output increases. Here, it is known that the photon energy of light increases as the wavelength of light decreases. That is, the photon energy at a wavelength of 1064 nm (fundamental wave) is 1.16 eV, 532 nm (2 harmonic), 3 55 nm (3 harmonic), the photon energy of each wavelength of 266 nm (4 harmonic) are respectively It becomes 2.33 eV (2 times), 3.50 eV (3 times), 4.66 eV (4 times).

  The inventors paid attention to this photon energy, and illustrated the resistance value in FIG. 4 again with respect to the product of the photon energy and the laser output. FIG. 5 is a diagram showing the results.

As shown in this figure, it can be seen that the resistance values of the respective wavelengths overlap on the same curve. In particular, the photon energy and the product of the laser output could be obtained 1000eV · mJ / cm ² or more and ^{8000eV · mJ / cm 2 10 -3} Ω · cm -2 or less favorable ohmic electrode having a low resistance in the following. However, if the photon energy is too large, the surface of the back surface 1b of the n ⁺ -type substrate 1 may be ablated or melted by the heat of laser irradiation, so the product of the photon energy and the laser output is 8000 eV · mJ / cm. ² or less is preferable.

Therefore, as described above, and the conditions such as the photon energy and the product of the laser power of the LD pumped solid laser is 1000eV · mJ / cm ² or more and 8000eV · mJ / cm ² or less.

Furthermore, the present inventors formed the drain electrode 11 by the conventional method and the method according to the present embodiment, respectively, and performed Auger analysis for comparison. The conventional method is a process sequence in which the metal thin film 110 is formed after the back surface 1b of the n ⁺ type substrate 1 is irradiated with laser light.

That is, the metal thin film 110 was removed by carros cleaning for the samples obtained by the conventional method and the method according to the present embodiment, and then Auger analysis was performed on the back surface 1b of the n ⁺ type substrate 1. The result is shown in FIG.

FIG. 6A shows the results of Auger analysis when the drain electrode 11 is formed by a conventional method, and FIG. 6B shows the results of the method according to the present embodiment. The horizontal axis of each graph shown in FIG. 6 is the depth of the n ⁺ type substrate 1, and the vertical axis is the detected intensity. The larger the detection intensity, the more elements that are the detection targets are distributed.

As shown in FIG. 6A, when the drain electrode 11 was formed by the conventional method, the presence of carbon (C) and oxygen (O) constituting the n ⁺ type substrate 1 could be detected. Ni constituting the metal thin film 110 could not be detected. That is, it can be said that Ni does not exist in the n ⁺ type substrate 1 and Ni silicide is not formed.

However, as shown in FIG. 6B, when the drain electrode 11 is formed by the method of the present embodiment, the closer to the back surface 1b of the n ⁺ type substrate 1, the more Ni is detected, and the n ⁺ type substrate 1 The detection intensity of Ni decreases as the depth increases from the back surface 1b. That is, it can be said that Ni silicide is formed in the depth direction from the back surface 1b of the n ⁺ type substrate 1.

As described above, even if the drain electrode 11 is formed by the method according to the present embodiment, that is, after the metal thin film 110 is formed and the laser beam is irradiated and the high temperature treatment is not performed, the Ni silicide is formed on the n ⁺ type substrate 1. Can be formed.

Even after the back electrode of the n ⁺ type substrate 1, that is, the drain electrode 11 was formed as in this embodiment, no change was observed in the electrical characteristics of the element on the front surface side. Therefore, it is possible to form the n ⁺ -type substrate 1 to form a surface electrode, without giving thermal damage, particularly the surface side of the thinned n ⁺ -type substrate 1, an ohmic electrode on the back surface (drain electrode 11).

As described above, the process sequence of the present embodiment, that is, forming the fine irregularities on the back surface 1b of the n ⁺ type substrate 1 by polishing, providing the metal thin film 110 on the back surface 1b, and then irradiating the laser beam. By forming the drain electrode 11 as the back electrode, an ohmic electrode having a low resistance with respect to the back surface of SiC can be obtained.

As described above, in the present embodiment, n ⁺ after forming the element structure and the surface electrode on the surface side of the mold substrate 1, fine irregularities on the back surface 1b performs grinding process on the back surface 1b of the n ⁺ -type substrate 1 Form. After the metal thin film 110 is formed on the back surface 1b on which the unevenness is formed, the product of photon energy and laser output is 1000 eV · mJ / cm ² or more and 8000 eV · mJ / cm on the back surface 1b side of the n ⁺ type substrate 1. ^The drain electrode 11 including the silicide layer 111 is formed by irradiating with laser light under a condition of ² or less.

Thus, without performing high-temperature processing the n ⁺ -type substrate 1, it is possible to produce a silicide layer 111 on the drain electrode 11 to the n ⁺ -type substrate 1. That is, the drain electrode 11 can be ohmic-bonded to the back surface 1 b of the n substrate 1 without causing thermal damage to the element structure formed on the surface side of the n ⁺ type substrate 1. Therefore, it is possible to make the drain electrode 11 an ohmic electrode by using a low temperature process without using an ion implantation process.

  Furthermore, the surface roughness Ra is set to be 10 nm or more and 500 nm or less when forming fine irregularities. For this reason, a better ohmic junction can be obtained.

(Second Embodiment)
A second embodiment of the present invention will be described. In this embodiment, the laser beam used for forming the silicide layer 111 is changed with respect to the first embodiment, and the other parts are the same as those in the first embodiment. Only will be described.

In the first embodiment, an LD-excited solid laser is used. In this embodiment, a KrF excimer laser (248 nm) is used as the laser beam. Then, the silicide layer 111 was formed on the drain electrode 11 with the intensity of the laser beam of the KrF excimer laser set to 1300 mJ / cm ² . Since the photon energy of this laser beam is 5.00 eV, the product of the photon energy and the laser output is 6500 eV · mJ / cm ² . Even in such a case, a good ohmic electrode having a low resistance of 10 ⁻³ Ω · cm ⁻² or less could be obtained. Therefore, the same effect as in the first embodiment can be obtained even when a KrF excimer laser is used. Incidentally, even in the case of using a KrF excimer laser, with respect to the photon energy and the product of the laser output is irradiated with laser light at 1000eV · mJ / cm ² or more and 8000eV · mJ / cm ² or less and made such conditions This is the same as in the first embodiment, whereby the same effect as in the first embodiment can be obtained.

(Other embodiments)
In each of the above embodiments, the power MOSFET has been described as an example. However, this is merely an example, and the present invention can be applied to a device having another element structure such as a diode or an IGBT.

  In the process shown in FIG. 2A, a grinding method is employed as the polishing treatment, but other methods such as sand blasting and lapping can also be employed in addition to grinding. Sand blasting is a polishing method in which sand or granular abrasive is sprayed onto the surface to be processed (back surface 1b) with compressed air or centrifugal force. Lapping is a polishing method in which an abrasive in which loose abrasive grains are dispersed is rubbed between the surface to be processed and a tool (lap) in a state of being rubbed together. For the formation of irregularities on the back surface 1b, a polishing method other than grinding, sandblasting, and lapping may be employed.

  In the step shown in FIG. 2B, the metal thin film 110 is formed by a vapor deposition method, but the metal thin film 110 is formed by a chemical vapor deposition method (CVD method), a coating / coating method, an electroplating method, or the like. You can also.

  In the step shown in FIG. 2C, the laser beam of the LD-excited solid laser is used as the laser beam, but laser irradiation can also be performed using a laser beam such as a semiconductor laser, a YAG laser, or a gas laser.

  Further, as a material of the metal thin film 110, a metal such as Ti, Mo, or W that forms silicide in addition to Ni can be employed. For example, when Ti was used as the metal thin film 110 and the drain electrode 11 was formed by the process shown in FIG. 2, Auger analysis was performed, and generation of Ti silicide was confirmed. Thus, even if the metal thin film 110 is formed of a metal material that can generate the silicide layer 111 other than Ti, such as Ti, the resistance of the drain electrode 11 can be reduced.

It is sectional drawing of the vertical power MOSFET in one Embodiment of this invention. FIG. 2 is a diagram showing a manufacturing process of a drain electrode in the semiconductor device shown in FIG. 1. It is the figure which showed the result of having measured resistance about what formed the drain electrode by changing the surface roughness Ra of the back surface of an n ^<+> type | mold board | substrate. It is the figure which showed the result of having measured resistance about what formed the drain electrode by changing the wavelength of the laser beam to irradiate with respect to the laser output. It is the figure which showed resistance shown in FIG. 4 with respect to the product of the photon energy of the wavelength of a laser beam, and a laser output. It is the figure which showed the result of the Auger analysis, (a) is the figure which showed the result at the time of forming a drain electrode, respectively by the conventional method and (b) by the method which concerns on this embodiment.

Explanation of symbols

1 n ⁺ type substrate 1a main surface 1b back surface 10 source electrode 11 drain electrode 40 protective film 51 laser beam 110 metal thin film 111 silicide layer

Claims (6)

A method for manufacturing a semiconductor device comprising a semiconductor substrate (1) having a main surface (1a) and a back surface (1b) opposite to the main surface and made of single-crystal silicon carbide,
A polishing step of preparing the semiconductor substrate and forming irregularities on the back surface by polishing the back surface of the semiconductor substrate;
After the polishing step, a metal thin film forming step of forming a metal thin film (110) for forming silicide on the back surface of the semiconductor substrate;
An electrode forming step of forming the first electrode (11) by irradiating the metal thin film with a laser beam (50) after the metal thin film forming step;
In the electrode forming step, the laser beam (50) is irradiated with a solid-state laser, the wavelength of the laser beam (50) is set to 355 nm, the photon energy (eV) in the laser beam and the laser output (mJ / cm ^2). ) Product of 1000 (eV · mJ / cm ² ) or more and 8000 (eV · mJ / cm ² ) or less to form a silicide layer (111) on the metal thin film by irradiating the laser beam as a laser output. have time line, which is,
In the polishing step, the back surface is polished so that the roughness (Ra) of the back surface of the semiconductor substrate is not less than 10 nm and not more than 500 nm . 2. The method for manufacturing a silicon carbide semiconductor device according to claim 1 , wherein, in the metal thin film forming step, a metal containing any one or more of Ni, Ti, Mo, and W is formed as the metal thin film. 3. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the metal thin film forming step, the thickness of the metal thin film is set to 10 nm or more. In the electrode forming step, by scanning or masking, according to any one of claims 1 to 3, characterized in that irradiating the laser beam (50) only on the metal thin film portion on the back surface of the semiconductor substrate A method for manufacturing a silicon carbide semiconductor device. In the step of preparing the semiconductor substrate, an element structure is formed on the main surface side of the semiconductor substrate, a second electrode (10) is formed on the main surface, and the first electrode is formed on the back surface. Of the vertical semiconductor elements formed and made to pass current through the element structure between the second electrode and the first electrode, the element structure is formed on the semiconductor substrate, and the second after the electrode formation, the method for manufacturing the silicon carbide semiconductor device according to any one of claims 1 to 4, characterized in that polishing the back surface of the semiconductor substrate. In the step of preparing said semiconductor substrate, to claim 5, characterized in that to form a protective film covering the second said electrode after forming of the main surface side of the semiconductor substrate a second electrode (40) The manufacturing method of the silicon carbide semiconductor device of description.

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