JP2006268935A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device of which the connection test is facilitated. <P>SOLUTION: The semiconductor device is provided with a selection control circuit 13 which operates in response to command input and outputs selection signals SS1, SS2, SS3, ..., SSx, and switching circuits 14-1, ..., 14-x having first and second terminals IN1, IN2, IN3, .... INx, OUT1, OUT2, OUT3, ..., OUTx which are controlled by the selection signal output from the selection control circuit, connect the first and the second terminals when the selection signal is in a first level, and separate the first and the second terminals electrically when the selection signal is in a second level. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a connection test function. For example, a connection check of a bonding wire between an external terminal in a multichip package and a wiring or a signal extraction point (bonding pad) in the semiconductor chip, or an external terminal This is for facilitating checking of contact and connection between test and measurement devices or application devices (collectively referred to as connection test).

  Conventionally, a semiconductor device connection test is performed by measuring a forward current of a protective diode element provided corresponding to each bonding pad of a semiconductor chip in an environment where current can be measured (current monitoring method). ).

  However, in a multi-chip package (MCP) in which a plurality of semiconductor chips are sealed in one package, there are terminals that are commonly wired to the plurality of chips inside the package. It is impossible to find a connection failure called so-called drop-out, in which connection failure exists in part. Taking a NOR flash memory as an example, the terminals required for command input are limited to 15 terminals such as the address terminals A0 to A10, so that it is impossible to test the connection of the remaining terminals. Furthermore, there are various problems, such as a method of checking only leakage current measurement between terminals, for problems such as electrical shorts between adjacent terminals.

In order to solve such a problem, for example, Patent Document 1 discloses a technique for performing a connection test on all terminals using a function that outputs a calculation result of arbitrary input data. However, since the technique described in Patent Document 1 requires a conversion circuit and an arithmetic circuit, it has a considerable influence on the chip size. In addition, when the pass / fail judgment of the connection test is performed, the calculation result for the input value must be similarly calculated on the host side.
JP2001-1335098

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device capable of facilitating a connection test.

  According to one aspect of the present invention, a selection control circuit that operates in response to an input of a command and outputs a selection signal, and a selection signal output from the selection control circuit, the first and second terminals. When the selection signal is at the first level, the first and second terminals are directly connected, and when the selection signal is at the second level, the first and second terminals are electrically separated. A switching device is provided.

  According to one embodiment of the present invention, the semiconductor chip is provided in at least one of the plurality of semiconductor chips, the package for sealing the plurality of semiconductor chips, and the plurality of semiconductor chips, and operates in response to a command input. A selection control circuit for outputting a selection signal; and provided in at least one of the plurality of semiconductor chips, having first and second terminals, controlled by the selection signal output from the selection control circuit, A switching circuit for directly connecting the first and second terminals when the selection signal is at the first level and electrically separating the first and second terminals when the selection signal is at the second level; A semiconductor device is provided.

  According to the present invention, a semiconductor device that can facilitate a connection test is obtained.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram for explaining a semiconductor device according to an embodiment of the present invention. FIG. 1 is a block diagram showing a schematic configuration by extracting a main part related to the invention, taking a semiconductor memory device as an example. In the semiconductor chip 11, planes 12-1, 12-2, 12-3,..., 12-x of the memory unit 12 and a selection control circuit 13 are provided. , 12-x input terminals (input pads) IN1, IN2, IN3,..., INx and output terminals (output pads) OUT1, OUT2, OUT3,. Switching circuits 14-1,..., 14-x are respectively provided between OUTx. In this example, the combination of the input terminal and the output terminal is 1: 1.

  The operation of the selection control circuit 13 is controlled in response to an input of a command, and outputs selection signals SS1, SS2, SS3,. The selection signals SS1, SS2, SS3,..., SSx are single or a plurality of arbitrary signals according to the type of command, and are selective to the switching circuits 14-1,. To be supplied. These switching circuits 14-1,..., 14-x are respectively input terminals IN1, IN2, IN3,... When the selection signals SS1, SS2, SS3, ..., SSx are at "H" level (or "L" level). , INx and the output terminals OUT1, OUT2, OUT3,..., OUTx are substantially directly connected, and when the selection signals SS1, SS2, SS3,..., SSx are at “L” level (or “H” level), The input terminals IN1, IN2, IN3,..., INx and the output terminals OUT1, OUT2, OUT3,.

  The combination of the input terminal and the output terminal directly connected by the switching circuits 14-1,..., 14-x is not limited to 1: 1 but can be freely combined. For example, the same terminal can be allowed to be in different pairs, such as the input terminal IN2 and the output terminal OUT1, and the input terminal IN1 and the output terminal OUT2.

  Each switching circuit 14-1,..., 14-x (14) includes, for example, P channel type MOS transistors Q1, Q2, N channel type MOS transistors Q3, Q4 and inverters 21, 22 as shown in FIG. It is configured. The current paths of the MOS transistors Q1 to Q4 are connected in series between the power supplies Vcc and Vss. The gates of the MOS transistors Q1 and Q4 are connected to the input terminal IN. The output terminal of the inverter 21 is connected to the gate of the MOS transistor Q2. A selection signal SS is supplied from the selection control circuit 11 to the input terminal of the inverter 21 and the gate of the MOS transistor Q3. The input terminal of the inverter 22 is connected to the connection point of the current paths of the MOS transistors Q2 and Q3, and the output terminal is connected to the output terminal OUT.

  In the above configuration, when the selection signal SS is at “H” level, the MOS transistors Q2 and Q3 are turned on. As a result, the MOS transistors Q1 and Q4 operate as inverters. When the input terminal IN is at “H” level, the output terminal OUT is at “H” level, and when the input terminal IN is at “L” level, the output terminal OUT is at “L” level. The input / output relationship is established. That is, it is equivalent to a direct connection between the input terminal IN and the output terminal OUT.

  On the other hand, when the selection signal SS is at “L” level, the MOS transistors Q2 and Q3 are turned off, so that the input terminal IN and the output terminal OUT are electrically separated and have no influence on the operation of other circuits in the semiconductor chip. Don't give. This is the state during normal operation of the semiconductor chip.

  2 shows an example in which the input terminal IN and the output terminal OUT of the switching circuit 14 are connected to the external terminals 23 and 24 on a one-to-one basis by bonding wires 25 and 26. .., INx and the output terminals OUT1, OUT2, OUT3,..., OUTx may be selectively connected, or a plurality may be commonly connected.

  Next, in the semiconductor device configured as described above, connection is made with reference to the timing charts of FIGS. 3 to 5 and the input terminal (input buffer) -output terminal (output buffer) combination examples of FIGS. The test will be described.

  As shown in FIG. 3, when the chip enable signal / CE and the write enable signal / WE are at the “L” level, a command is input to generate the selection signal SS from the selection control circuit 13 (at this time, the output enable signal) Signal / OE is at “H” level. The state of the switching circuit 14 is controlled by the selection signal SS, the input terminal IN and the output terminal OUT of the selected switching circuit are substantially directly connected, and the input terminal IN and the output terminal OUT of the non-selected switching circuit are electrically connected. To separate. In this state, the expected value CMD1 is input from the input / output terminal DQ (OUTx).

  When the chip enable signal / CE and the output enable signal / OE are at "L" level (at this time, the write enable signal / WE is at "H" level), the address terminal ADD ( INx) and the input / output terminal DQ (OUTx) are fixed.

  The data DATA1, DATA2, and DATA3 output from the input / output terminal DQ (OUTx) are the contents of the signal INx input from the address terminal ADD, the input terminal (input buffer) and the output terminal (as illustrated in FIG. Output buffer) pair combination. In the case of this example, the input expected value requires expected values CMD1, CMD2, and CMD3 corresponding to combinations of data DATA1, DATA2, and DATA3.

  That is, when the expected value CMD1 is input from the input / output terminals DQ0 to DQ7, the same data DATA1 as the expected value CMD1 is output from the address terminals A17 to A24 if the connection is normal. When the expected value CMD2 is input from the input / output terminals DQ0 to DQ7, if the connection is normal, the same data DATA2 as the expected value CMD2 is output from the address terminals A9 to A16. When the expected value CMD3 is input from the input / output terminals DQ0 to DQ7, if the connection is normal, the same data DATA3 as the expected value CMD3 is output from the address terminals A1 to A8. In this way, the connection between the input / output terminals DQ0 to DQ7 and the address terminals A1 to A24 can be checked by switching the three combinations according to the command.

  Note that one cycle may be assigned to the command input, or a plurality of cycles may be assigned. The content of the expected value may be arbitrary, and other input terminals can be used instead of the address terminals. The combination of the terminal that inputs the expected value and the terminal that outputs the result is arbitrary.

  Also, as shown in FIG. 4, when the chip enable signal / CE and the write enable signal / WE are at the “L” level, a command is input to generate the selection signal SS from the selection control circuit 13 (at this time, the output signal). Enable signal / OE and reset signal / RESET are both at "H" level). The state of the switching circuit 14 is controlled by the selection signal SS, the input terminal IN and the output terminal OUT of the selected switching circuit are substantially directly connected, and the input terminal IN and the output terminal OUT of the non-selected switching circuit are electrically connected. To separate. In this state, the expected value CMD is input from the input / output terminal DQ (OUTx).

  When the chip enable signal / CE and the output enable signal / OE are both at the “L” level (at this time, the write enable signal / WE is at the “H” level), the address terminal ADD depends on the state of the switching circuit. (INx) and the input / output terminal DQ (OUTx) are fixed. Further, the data DATA1 and DATA2 output from the input / output terminal DQ (OUTx) include the contents of the signal INx input from the address terminal ADD, the input terminal (input buffer) and the output terminal (as illustrated in FIG. Output buffer) pair combination. In this example, 32 input terminals (ADD / CTRL) are combined with 16 output terminals (DQx), and divided into two groups, the “L” level / “H” level of the control input terminal such as the reset signal / RESET. The combination is switched by level. Therefore, one type of input expected value CMD is sufficient (the combination is switched by the reset signal / RESET).

  That is, when the reset signal / RESET is “L” level and the expected value CMD is input from the input / output terminals DQ0 to DQ15, the same data DATA1 as the expected value CMD is output from the address terminals A9 to A24 if the connection is normal. The On the other hand, when the reset signal / RESET is “H” level and the expected value CMD is input from the input / output terminals DQ0 to DQ15, the terminals CLK, ACC, / WP, / BYTE, / WE, / The same data DATA2 as the expected value CMD is output from OE, / CE, A8 to A0. In this manner, combinations divided into a plurality of groups can be switched according to the level of the reset signal / RESET (which may be a signal supplied to another control input terminal).

  Further, as shown in FIG. 5, when the chip enable signal / CE and the write enable signal / WE are at the “L” level, a command is input to generate the selection signal SS from the selection control circuit 13 (at this time, the output signal is output). Enable signal / OE is at “H” level). The state of the switching circuit 14 is controlled by the selection signal SS, the input terminal IN and the output terminal OUT of the selected switching circuit are substantially directly connected, and the input terminal IN and the output terminal OUT of the non-selected switching circuit are electrically connected. To separate. In this state, the expected value CMD is input from the input / output terminal DQ (OUTx).

  When the chip enable signal / CE and the output enable signal / OE are at "L" level (at this time, the write enable signal / WE is at "H" level), the address terminal ADD ( INx) and the input / output terminal DQ (OUTx) are fixed. Further, the data DATA1 and DATA2 output from the input / output terminal DQ (OUTx) include the contents of the signal INx input from the address terminal ADD, the input terminal (input buffer) and the output terminal (as illustrated in FIG. Output buffer) pair combination. In this example, 32 input (output) terminals are combined with 8 output terminals, and the address terminals A0 / A1 are divided into four groups in the state of “L” level / “H” level (“L / L”). , “H / L”, “L / H”, “H / H”). Therefore, one type of input expected value CMD is sufficient (the combination is switched by the address signal A1 / A0).

  That is, when the address terminal A0 / A1 is “L / L”, when the expected value CMD is input from the input / output terminals DQ0 to DQ7, if the connection is normal, the same data DATA1 as the expected value CMD is output from the address terminals A17 to A24. Is output. When the address terminal A0 / A1 is “H / L”, when the expected value CMD is input from the input / output terminals DQ0 to DQ7, the same data DATA2 as the expected value CMD is output from the address terminals A9 to A16 if the connection is normal. The When the address terminal A0 / A1 is “L / H”, when the expected value CMD is input from the input / output terminals DQ0 to DQ7, if the connection is normal, the same data DATA3 from the terminals R / B and A2 to A8 as the expected value CMD. Is output. When the address terminal A0 / A1 is “H / H”, when the expected value CMD is input from the input / output terminals DQ0 to DQ7, if the connection is normal, the same data DATA4 as the expected value CMD is output from the input / output terminals DQ8 to DQ15. Is done.

  In this way, various terminal pairs can be assembled, and all terminals can be covered and a connection test for all terminals can be performed.

  Note that only a one-to-one check between the input terminal and the output terminal can only confirm the presence / absence of connection, but by checking the combination of input / output data, it is possible to detect an abnormality such as a short circuit between the terminals. . Since input data can be input arbitrarily, in the case of a combination of 8 pairs of address terminal Ax and input / output terminal DQx, input data is input 8 times in order as shown in FIG. 9 and FIG. By checking the output data at the time, a defective portion due to a short circuit between the terminals can be detected.

  In addition, when there is a short circuit between the address terminals A1 and A2 (or between the input / output terminals DQ1 and DQ2), the input value 2 and the input value 3 become output data different from the input.

  In this way, by checking the relationship between input data and output data, not only short-circuits can be detected, but also short-circuit locations can be identified.

  Therefore, according to the configuration as described above, it is easy to determine pass / fail because it is possible to give any combination of parallel data to any terminal and output the parallel data as it is from the output terminal. Since input data can be set freely, the degree of freedom in testing on the host side is high. Further, the number of test cycles can be minimized (number of input terminals ÷ number of output terminals) times, and the test time can be shortened. Furthermore, since an arithmetic circuit dedicated to connection testing is not required and can be formed only by a switching circuit (switch), the influence on the chip area is small. In addition, it is not necessary to provide a dedicated test terminal, and the connection test can be performed using only terminals provided in advance. Furthermore, by repeatedly testing by changing the combination of input data, it is possible to identify a contact failure location, which can be used for the purpose of failure analysis.

  As described above, according to the embodiment of the present invention, the semiconductor memory device and the circuit board on which the semiconductor memory device is mounted, or the terminal is temporarily brought into contact with all terminals or arbitrary terminals of the semiconductor memory device. Connection test with test equipment is possible.

  In addition, it is possible to easily perform a connection test on an arbitrary terminal in a socket use state or a solder mounting state, or an arbitrary combination of terminals, in-house and / or outside the company.

  Furthermore, if the test is repeated by changing the combination of input data, it is possible to specify a contact failure location, which can be used for failure analysis purposes. As a result, it is possible to simplify the defect classification of the shipping test and improve the yield, and to expect a reduction in time and rationalization.

  Although the present invention has been described above using the embodiment, the present invention is not limited to the embodiment described above, and various modifications can be made without departing from the scope of the invention in the implementation stage. . The above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiment, at least one of the problems described in the column of the problem to be solved by the invention can be solved, and is described in the column of the effect of the invention. When at least one of the effects is obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram for explaining a semiconductor device according to an embodiment of the present invention and showing a schematic configuration by extracting a main part related to the invention by taking a semiconductor memory device as an example; FIG. 2 is a circuit diagram illustrating a configuration example of a switching circuit in the semiconductor device illustrated in FIG. 1. 3 is a timing chart for explaining a first operation example of the circuit shown in FIG. 2. 3 is a timing chart for explaining a second operation example of the circuit shown in FIG. 2. 3 is a timing chart for explaining a third operation example of the circuit shown in FIG. 2. The figure which shows the example of control of the combination of the input terminal-output terminal in the 1st operation example shown in FIG. The figure which shows the example of control of the combination of the input terminal-output terminal in the 2nd operation example shown in FIG. The figure which shows the example of control of the combination of the input terminal-output terminal in the 3rd operation example shown in FIG. The figure which shows the relationship between the input data and output data at the time of normal. The figure which shows the relationship between the input data at the time of abnormality, and output data.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Semiconductor chip (semiconductor memory device), 12 ... Memory part, 12-1, 12-2, 12-3, ..., 12-x ... Plane, 13 ... Selection control circuit, 14, 14-1, ..., 14 -X ... switching circuit, 21, 22 ... inverter, 23, 24 ... external terminal, 25, 26 ... bonding wire, IN1, IN2, IN3, ..., INx ... input terminal (input pad), OUT1, OUT2, OUT3, ... , OUTx ... output terminals (output pads), SS1, SS2, SS3, ..., SSx ... selection signals, Q1, Q2 ... P-channel MOS transistors, Q3, Q4 ... N-channel MOS transistors.

Claims (5)

A selection control circuit that operates in response to a command input and outputs a selection signal;
The first and second terminals are controlled by a selection signal output from the selection control circuit, and when the selection signal is at a first level, the first and second terminals are directly connected, and the selection is performed. And a switching circuit for electrically separating the first and second terminals when the signal is at the second level. A plurality of semiconductor chips;
A package for sealing the plurality of semiconductor chips;
A selection control circuit that is provided in at least one of the plurality of semiconductor chips, operates in response to an input of a command, and outputs a selection signal;
Provided in at least one of the plurality of semiconductor chips, having first and second terminals, controlled by a selection signal output from the selection control circuit, and when the selection signal is at a first level, A switching circuit that directly connects the first and second terminals and electrically isolates the first and second terminals when the selection signal is at a second level.   3. The semiconductor device according to claim 2, wherein the plurality of semiconductor chips have a common terminal, and the first or second terminal of the switching circuit is connected to the common terminal.   The switching circuit includes a first conductivity type first MOS transistor having one end of a current path connected to a first potential supply source and a gate connected to the first terminal, and one end of a current path having the first MOS transistor A first conductivity type second MOS transistor connected to the other end of the current path, a selection signal output from the selection control circuit supplied to the input terminal, and an output terminal connected to the gate of the second MOS transistor A first inverter; a third MOS transistor of a second conductivity type, wherein one end of a current path is connected to the other end of the current path of the second MOS transistor, and a selection signal output from the selection control circuit is supplied to a gate; One end of the current path is connected to the other end of the current path of the third MOS transistor, the other end of the current path is connected to the second potential supply source, and the gate is the first potential source. A second MOS transistor having a second conductivity type connected to a terminal, a second inverter having an input terminal connected to a connection point of current paths of the second and third MOS transistors, and an output terminal connected to the second terminal; The semiconductor device according to claim 1, further comprising:   5. The semiconductor device according to claim 1, wherein each of the first terminal and the second terminal is electrically connected to an external terminal.

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