JP2006262104A - D level amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To input an input signal whose level changes in positive and negative polarities around an OV without being restricted up to a supply voltage and to make an output almost OV at inputting nothing. <P>SOLUTION: A D level amplifier operated by a single power supply has a differential integrator and a PWM modulator. The differential integrator integrates a difference between a plus side input signal and a minus side input signal which make analog input signals. The PWM modulator outputs a pulse train signal with a pulse width according to the signal level in the positive term of the analog input signals from a first output terminal and outputs the pulse train signal with the pulse width according to the signal level in the negative term of the analog input signals from a second output terminal, based on the output of the differential integrator. The D level amplifier has a protection circuit to restrict an excessive input voltage. The differential integrator includes an operational amplifier where a voltage level of the analog input signals having the positive and negative polarities around the OV can operate near the OV. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a class D amplifier.

The class D amplifier amplifies power by subjecting an input signal to pulse width modulation, and is used for power amplification of an audio signal, for example. As a conventional class D amplifier, an integrator for integrating an analog input signal, a comparator (comparator) for comparing the output of the integrator with a predetermined triangular wave, and amplifying the output of the comparator to output a pulse signal Some have a buffer (pulse amplifier). The buffer output of the conventional class D amplifier is fed back to the input side of the integrator. The buffer output is an analog signal that drives a load such as a speaker through a low-pass filter including a coil and a capacitor.
Japanese Patent Publication No.56-27001

  A class D amplifier operating with a single power supply has been proposed. The configuration of this class D amplifier is shown in FIG. In the figure, a class D amplifier 70 includes diodes D1 and D2, resistors R1 and R3 that form a protection circuit that protects an internal circuit when an abnormal voltage is input, and an integration capacitor C1 that forms a differential integrator. , C2, resistors R2 and R4, a differential operational amplifier 500, and a PWM modulator 501.

The plus side input terminal + IN of the class D amplifier 70 is connected to a signal source 100 that outputs an analog signal via a capacitor C10 and a terminal 110.
The negative side input terminal -IN of the class D amplifier 70 is connected to the signal source 101 that outputs an analog signal obtained by inverting the analog signal output from the signal source 100 via the capacitor C11 and the terminal 111. Resistors R10 and R11 are input resistors.

  The negative output end -OUT of the PWM modulator 501 is connected to one end of a load 200 such as a speaker via a low pass filter including an inductance L1 and a capacitor C3, and the positive output end + OUT of the PWM modulator 501 is connected to an inductance L2 The other end of the load 200 is connected through a low-pass filter composed of a capacitor C4. VDD is a power supply voltage, and VSS is a ground potential.

  As a method of driving the class D amplifier having the above configuration, (1) since it is a single power supply, the input signal is a signal centered on VDD / 2 (reference), and the output signal has an input signal level with a duty of 50%. (2) In FIG. 6, without the capacitors C10 and C11, the input is a signal having a level up to ± 0.3V centered on 0V and output. Outputs a pulse signal (PWM signal) with a duty cycle of 50% and a pulse width corresponding to the input signal level. (3) The input signal is centered on VDD / 2 (reference), and the output signal is negative from 0V. For example, a PWM signal is output one by one from the output terminal -OUT and the positive output terminal + OUT.

In the driving methods (1) and (3) described above, there is a problem that capacitors (C10, C11) for cutting the DC component are required on the input side as shown in FIG.
In addition, the driving method (2) has a problem that the input signal level is limited.
In addition, the driving methods (1) and (2) have a problem that the load is biased to VDD / 2 even if there is no input signal.

  The present invention has been made in view of such circumstances, and an input signal that operates with a single power source and has a positive / negative polarity centered on 0 V is provided up to a power supply voltage without providing an input capacitor. An object of the present invention is to provide a class D amplifier that can be input without being limited and can output substantially 0 V when there is no input.

  In order to achieve the above object, the invention according to claim 1 is characterized in that a differential integrator that integrates a difference between a positive side input signal and a negative side input signal forming an analog input signal that changes in positive and negative polarities, and the difference Based on the output of the dynamic integrator, a pulse train signal having a pulse width corresponding to the signal level in the positive period of the analog input signal is output from the first output terminal, and in accordance with the signal level in the negative period of the analog signal A class D amplifier that operates with a single power supply having a PWM modulator that outputs a pulse train signal having a pulse width from the second output terminal, and includes a protection circuit that limits an excessive input voltage in the positive and negative directions, The differential integrator includes an operational amplifier that can operate when the voltage level of an analog input signal having positive and negative polarities centered on 0V is near 0V.

  According to a second aspect of the present invention, in the class D amplifier according to the first aspect, the operational amplifier is composed of a MOS transistor, and the two MOS transistors constituting the differential amplifier in the input stage are composed of PMOS transistors. The drain potential is fixed to a potential in the vicinity of 0 V at which the PMOS transistor can operate.

  As described above, according to the present invention, the differential integrator that integrates the difference between the positive side input signal and the negative side input signal that form an analog input signal that changes in positive and negative polarities, Based on the output, a pulse train signal having a pulse width corresponding to the signal level in the positive period of the analog input signal is output from the first output terminal, and having a pulse width corresponding to the signal level in the negative period of the analog signal In a class D amplifier operating with a single power supply having a PWM modulator that outputs a pulse train signal from a second output terminal, a protection circuit for limiting an excessive input voltage in the positive and negative directions is provided, and the differential integrator is set to 0 V Since it is configured to include an operational amplifier that can operate at a voltage level of an analog input signal having positive and negative polarities centered on 0V near 0V, it operates with a single power source and inputs Class D amplifier that can input an input signal whose level changes with positive and negative polarity around 0V without being limited to the power supply voltage without providing a capacitor, and can set the output to almost 0 V when there is no input. Can be realized.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows the configuration of a class D amplifier according to an embodiment of the present invention. The class D amplifier according to the embodiment of the present invention is different in configuration from the class D amplifier shown in FIG. 6 in that a protection circuit for limiting an excessive input voltage in the positive and negative directions is provided, and 0 V is applied to the differential integrator. The configuration is such that it is configured using an operational amplifier that can operate when the voltage level of an analog input signal having positive and negative polarities at the center is near 0 V, and the other configurations are the same.

  In FIG. 1, the class D amplifier 1 according to the embodiment of the present invention includes a series circuit of diodes D3 and D4 having anodes connected to each other, connected between a positive input terminal + IN and a ground potential VSS, and anodes connected to each other. A series circuit of the diodes D5 and D6 is provided with a protection circuit connected between the negative input terminal -IN and the ground potential VSS. This protection circuit has an excessive input voltage in the positive / negative direction at the positive input terminal + IN, the positive voltage is the breakdown voltage of the diode D3 and the negative voltage is the breakdown voltage of the diode D4, and the negative input terminal -IN is positive. In terms of voltage, it functions as a protection circuit that limits the breakdown voltage and negative voltage of the diode D5 within the range of the breakdown voltage of the diode D6. Each input terminal can accept positive and negative inputs.

The class D amplifier 1 includes diodes D1 and D2, resistors R1 and R3 that form a protection circuit that protects an internal circuit when an abnormal voltage is input, and integration capacitors C1 and C2 that form a differential integrator. , Resistors R 2 and R 4, a differential operational amplifier 10, and a PWM modulator 11. The differential operational amplifier 10 is an operational amplifier that can operate when the voltage level of an analog input signal having positive and negative polarities centered on 0V is around 0V. The input of the differential operational amplifier 10 is limited to the saturation voltage of each diode by the diodes D1 and D2.
A specific configuration of the differential operational amplifier 10 will be described later.
The positive side input terminal + IN of the class D amplifier 1 is connected to a signal source 100 that outputs an analog signal, and the negative side input terminal −IN of the class D amplifier 1 inverts an analog signal output from the signal source 100. Is connected to a signal source 101 that outputs the analog signal.

  The negative output end -OUT of the PWM modulator 11 is connected to one end of a load 4 such as a speaker via a low pass filter including an inductance L1 and a capacitor C3. The positive output end + OUT of the PWM modulator 11 is connected to an inductance L2 The other end of the load 4 is connected through a low-pass filter composed of a capacitor C4. VDD is a power supply voltage, and VSS is a ground potential.

  Next, FIG. 2 shows a configuration example of a protection circuit in the case where the class D amplifier 1 shown in FIG. In the figure, the drains of the diode-connected PMOS transistor M1 and NMOS transistor M2 are connected in common, and the source of the diode-connected PMOS transistor M1 corresponds to the input terminal 20 (corresponding to the plus-side input terminal + IN). The source of the NMOS transistor M2 is grounded. The series circuit of the diodes D3 and D4 constituting the protection circuit that limits the excessive input voltage in the positive and negative directions in FIG. 1 corresponds to a series circuit in which the drains of the diode-connected PMOS transistor M1 and NMOS transistor M2 are connected in common.

One end is connected to the input terminal 20, the other end of the resistor R1 is connected to the drain, and the source of the diode-connected NMOS transistor M3 is grounded. The NMOS transistor M3 corresponds to the diode D1 in FIG. MP1 is a PMOS transistor in the internal circuit 40 of the class D amplifier.
FIG. 2 shows only the protection circuit 30 connected to the plus-side input terminal + IN in FIG. 1, but the same applies to the protection circuit connected to the minus-side input terminal −IN.
The excessive voltage in the positive direction is clamped by the diode-connected PMOS transistor M1, and the excessive voltage in the negative direction is clamped by the NMOS transistor M2, so that the excessive input voltage is limited by the breakdown voltage (breakdown voltage) of the transistor. The

  The operation of the class D amplifier 1 having the above-described configuration according to the embodiment of the present invention will be described with reference to FIGS. In the above configuration, an analog signal (audio signal in the present embodiment) (FIG. 4A) is input from the signal source 100 to the positive side input terminal + IN of the class D amplifier 50, and to the negative side input terminal -IN. A signal (FIG. 4B) obtained by inverting the analog signal output from the signal source 100 and output from the signal source 101 is input.

Although the excessive input voltage is limited by the protection circuit composed of the diodes D3 and D4, an analog signal input from the plus side input terminal + IN and the minus side input terminal −IN is passed through the resistors R1 and R3 at a normal signal level. Is input to the differential integrator.
In the differential integrator, the differential operational amplifier 10 amplifies the difference between the analog signal input to the non-inverting input terminal from the positive input terminal + IN and the analog signal input to the inverting input terminal from the negative input terminal -IN. Then, an analog signal having the same phase as the analog input signal shown in FIG. 4A is output from the non-inverting output terminal, and the analog input signal shown in FIG. 4B is output from the inverting output terminal. Since each input terminal of the differential operational amplifier 10 is a virtual ground point and is approximately 0 V, it can operate even if the voltage is limited by the diodes D3 and D4. These output signals are input to the PWM modulator 11.

  In the PWM modulator 11, pulse signals having a pulse width corresponding to the signal level are alternately output to the plus side output terminal + OUT and the minus side output terminal −OUT in the positive section of each input signal having two 180 degrees and different phases. (FIGS. 4C and 4D). The pulse signal output from the minus-side output terminal -OUT is converted into an analog signal by a low-pass filter including an inductance L1 and a capacitor C3 and applied to one end of the load 4.

  The pulse signal output from the plus output terminal + OUT is converted into an analog signal by a low-pass filter including an inductance L2 and a capacitor C4 and applied to the other end of the load 4. As a result, an output signal obtained by amplifying a sine wave signal input from the signal source 100 which is an input signal of the class D amplifier 1 to the plus side input terminal + IN of the class D amplifier 1 is applied to both ends of the load 4.

  On the other hand, in the state where no signal is input to the plus side input terminal + IN and the minus side input terminal -IN (FIGS. 5A and 5B), the comparator in the PWM modulator 11 outputs the triangular wave and the differential integrator. With the comparison timing, pulses having a narrow pulse width are alternately output from the plus-side output terminal + OUT and the minus-side input terminal −IN (FIGS. 5C and 5D). This pulse output is removed by a low-pass filter consisting of an inductance L1 and a capacitor C3, and a low-pass filter consisting of an inductance L2 and a capacitor C4, and almost no signal is output to the load 4.

Although the specific configuration of the PWM modulator 11 is not shown in the circuit diagram of FIG. 1, the configuration of the class D amplifier of FIG. 1 including the specific configuration of the PWM modulator 11 is shown in FIG.
In FIG. 7, the class D amplifier includes resistors R1, R2, R3, and R4, capacitors C1, C2, and C100, an operational amplifier (operational amplifier) 10, comparators 112 and 113, inverters 121 and 122, and an AND circuit. 131 and 132 and a current source 140. Here, the capacitor C100 and the current source 140 constitute a triangular wave generation circuit, and output the triangular wave to the negative side input terminals of the comparators 112 and 113. The comparators 112 and 113, the inverters 121 and 122, the AND circuits 131 and 132, the current source 140 and the capacitor C100 constitute the PWM modulator 11 in FIG.

  One end of each of the resistors R1 and R3 is a differential input terminal for an analog input signal. One end of the resistor R1 is a plus side input end (+ IN), and one end of the resistor R3 is a minus side input end (−IN). The operational amplifier 10 and the capacitors C1 and C2 constitute a differential integrator. The analog input signal differentially input by the resistors R1 and R3 is integrated by the differential integrator and output to the comparators 112 and 113.

The negative output of the operational amplifier 10 is connected to the positive input terminal of the comparator 112 (first comparator). The plus output of the operational amplifier 11 is connected to the plus input terminal of the comparator 113 (second comparator). The negative side input ends of the comparators 112 and 113 are both connected to one end of a capacitor (capacitance) C100. One end of the current source 140 is connected to one end of the capacitor C100. The other end of the capacitor C100 is connected to the ground, and the other end of the current source 140 is also connected to the ground. Thus, the comparator 112 compares the negative output of the operational amplifier 11 with the output of the triangular wave generation circuit, and outputs the comparison result.
The comparator 113 compares the plus side output of the operational amplifier 10 with the output of the triangular wave generation circuit and outputs the comparison result.

The output of the comparator 112 is connected to the input terminal of the inverter 121 and one input terminal of the AND circuit 132 (second buffer). The output of the comparator 113 is connected to the input terminal of the inverter 122 and one input terminal of the AND circuit 131 (first buffer). The output of the inverter 121 is connected to the other input terminal of the AND circuit 131. The output of the inverter 122 is connected to the other input terminal of the AND circuit 132. Thus, the AND circuit 131 performs a logical product operation on the signal obtained by inverting the output of the comparator 112 and the output of the comparator 113, and outputs the operation result.
The AND circuit 132 performs an AND operation on the signal obtained by inverting the output of the comparator 113 and the output of the comparator 112, and outputs the operation result.

The output of the AND circuit 131 becomes the positive output + OUT of the class D amplifier. This positive output + OUT is fed back to the negative input of the operational amplifier by the resistor R4.
The output of the AND circuit 132 becomes the negative output -OUT of the class D amplifier. This negative output -OUT is fed back to the positive input of the operational amplifier by the resistor R2.

  As described above, according to the class D amplifier according to the embodiment of the present invention, an input signal that operates with a single power supply and that changes in level with positive and negative polarities centering on 0 V is provided without providing an input capacitor. The input can be performed without being limited to the voltage level, and the output can be set to almost 0 V when there is no input.

Next, FIG. 3 shows a configuration of the differential operational amplifier 10 constituting the differential integrator in FIG. In the figure, PMOS transistors MP1 and MP2 constitute an input stage differential amplifier circuit. The gate of the PMOS transistor MP1 is connected to the non-inverting input terminal INP and the gate of the PMOS transistor MP2 is connected to the inverting input terminal INN. ing.
The NMOS transistors MN1, MN2, and MN7 function as a circuit that sets operating points of the PMOS transistors MP1 and MP2 constituting the differential amplifier circuit in the input stage.

The PMOS transistors MP3 and MP4 constitute a constant current source, and supply a constant current to the PMOS transistors MP1 and MP2.
The NMOS transistors MN3, NM4, and NM9 have a function of determining the drain potentials of the PMOS transistors MP1 and MP2 constituting the input stage differential amplifier circuit.
The NMOS transistors MN5 and MN6 constitute an amplifier circuit in the output stage, and the drains of the NMOS transistors MN5 and MN6 are connected to the non-inverting output terminal OP and the inverting output terminal ON, respectively.

Similarly to the PMOS transistors MP3 and MP4, the PMOS transistors MP5 and MP7, the PMOS transistors MP6 and MP8, the PMOS transistors MP9 and MP11, the PMOS transistors MP10 and MP12, the PMOS transistors MP15 and MP16, and the PMOS transistors MP19 and MP20 are respectively constant. It constitutes a current source.
Reference numeral 50 denotes a current setting circuit that sets the output current of each current source. The current setting circuit 50 includes NMOS transistors MN10, MN11, MN12, MN17, and MN18. Here, the reference current Iref is supplied to the drain of the NMOS transistor MN12.

  Reference numeral 60 denotes an amplifier circuit for balancing the differential outputs output from the non-inverting output terminal OP and the inverting output terminal ON, and is composed of PMOS transistors MP13, 14, 15, 16 and an NMOS transistor MN8. Yes. A reference voltage Vref is input to the gate of the PMOS transistor MP14.

In addition, a parallel circuit composed of a capacitor C3 for waveform shaping and a resistor R3, and a parallel circuit composed of a capacitor C4 and a resistor R4 between the gate of the PMOS transistor MP13 and the non-inverting output terminal OP and the inverting output terminal ON, respectively, It is connected.
A series circuit of a capacitor C1 and a resistor R1 is connected between the drain of the NMOS transistor MN3 and the non-inverting output terminal OP, and a capacitor C1 and a resistor R1 are connected in series between the drain of the NMOS transistor MN4 and the inverting output terminal ON. Each circuit is connected. These series circuits are CR circuits for phase compensation.

  In the above configuration, when the reference current 1ref flows into the drain of the NMOS transistor MN12 of the current setting circuit 50, the NMOS transistors MN10 and 11 constituting the current mirror circuit with the NMOS transistor MN12 have a current corresponding to the ratio of these transistors. Flows. As a result, the current value of each current source is set via the PMOS transistors MP17 and MP18. As a result, the bias point of each MOS transistor is fixed.

  When the gate potentials of the NMOS transistors MN3 and MN4 are fixed by the NMOS transistor MN9, the drain potentials of the NMOS transistors MN3 and MN4 are set to the same level potential, and the PMOS transistors MP1 and MP2 constituting the differential amplifier circuit of the input stage Is also set to the same level as the drain potentials of the NMOS transistors MN3 and MN4. The drain potentials of the NMOS transistors MN3 and MN4 are set to about 0.2 to 0.3V, for example. This drain potential is a bias potential at which the analog voltage input to the gates of the NMOS transistors MN3 and MN4 can operate with an input voltage in the vicinity of 0V, specifically in the range of 0V to -0.1V.

  Therefore, even when 0 V is input to the non-inverting input terminal INP and the inverting input terminal INN, a voltage near the reference voltage Vref is output from the non-inverting output terminal OP and the inverting output terminal ON.

The circuit diagram which shows the structure of the class D amplifier which concerns on embodiment of this invention. The circuit diagram which shows the structural example at the time of comprising the protection circuit in the class D amplifier which concerns on embodiment of this invention shown in FIG. 1 with the MOS transistor. FIG. 2 is a circuit diagram showing a specific configuration of a differential operational amplifier constituting a differential integrator in the class D amplifier according to the embodiment of the present invention shown in FIG. 1. The wave form diagram which shows the operation | movement at the time of signal input to the class D amplifier which concerns on embodiment of this invention shown in FIG. The wave form diagram which shows the operation | movement at the time of no signal input to the class D amplifier which concerns on embodiment of this invention shown in FIG. The circuit diagram which shows the structure of the conventional class D amplifier. FIG. 2 is a circuit diagram showing a class D amplifier according to the embodiment of the present invention shown in FIG. 1 including a specific configuration of a PWM modulator.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,50 ... Class D amplifier 4,4200 ... Load 10,500 ... Differential operational amplifier 11,501 ... PWM modulator, 30 ... Protection circuit, 40 ... Internal circuit, 100,101 ... Signal source

Claims (2)

A differential integrator that integrates the difference between the positive side input signal and the negative side input signal that form an analog input signal that changes in positive and negative polarity;
Based on the output of the differential integrator, a pulse train signal having a pulse width corresponding to the signal level in the positive period of the analog input signal is output from the first output terminal, and the signal level in the negative period of the analog signal A class D amplifier that operates with a single power source having a PWM modulator that outputs a pulse train signal having a pulse width according to the second output terminal,
It has a protection circuit that limits excessive input voltage in the positive and negative directions,
The differential integrator is a class D amplifier comprising an operational amplifier which can operate when the voltage level of an analog input signal having positive and negative polarities centered on 0V is near 0V. The operational amplifier is composed of MOS transistors, the two MOS transistors constituting the differential amplifier of the input stage are composed of PMOS transistors, and the drain potential thereof is fixed at a potential around 0 V at which the PMOS transistor can operate. The class D amplifier according to claim 1.

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