JP2006258924A - Plasma display apparatus and driving method for the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma display apparatus capable of preventing contrast deterioration caused by background light emitting. <P>SOLUTION: A first display cell includes first and second display electrodes (Xo, Yi) and a second display cell includes the second display electrodes and third display electrodes (Yi, Xe). In a first address period (Ta1), discharge is generated between the first and the second display electrodes due to discharge between the second display electrode and an address electrode (Aj), while discharge is not generated between the second and the third display electrodes. Thereafter, in a first return period (Tt1), a return pulse is supplied to the second display electrode and the address electrode. In a second address period (Ta2), discharge is generated between the second and the third display electrodes due to discharge between the second display electrode and the address electrode, while discharge is not generated between the first and the second display electrodes. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a plasma display device and a driving method thereof.

  As a driving method of the common electrode type plasma display panel, there are Patent Documents 1 and 2 below. In FIG. 5 of Patent Document 1, the positive charges on the address electrodes are reduced by counter discharge due to blunt waves in all display cells before resetting. As a result, no discharge occurs in the display cell that is in a standby state in the subsequent address period. On the other hand, in a display cell that performs an address operation, a reset is performed with a combination of a positive blunt wave and a negative blunt wave, so that an address can be made.

JP 2003-5699 A JP 2002-108279 A

  In Patent Document 1, since reset by a combination of a positive blunt wave and a negative blunt wave is indispensable, there is a problem that a light-emitting display cell is discharged and the background light emission becomes bright at the time of this reset.

  An object of the present invention is to provide a plasma display device and a driving method thereof that can prevent a reduction in contrast due to background light emission by eliminating discharge of a light-off display cell at the time of reset.

  According to an aspect of the present invention, a first display cell including first and second display electrodes, a second display cell including the second display electrode and third display electrode, and the second An address electrode for discharging between the first display electrode, a first display electrode driving circuit for supplying a voltage to the first display electrode, and a voltage for supplying the voltage to the second display electrode Plasma having a second display electrode driving circuit, a third display electrode driving circuit for supplying a voltage to the third display electrode, and an address electrode driving circuit for supplying a voltage to the address electrode A display device is provided. In the first address period, a scan pulse is supplied to the second display electrode, and when an address pulse is supplied to the address electrode corresponding to the scan pulse, the interval between the second display electrode and the address electrode With this discharge, a discharge occurs between the first and second display electrodes, and no discharge occurs between the second and third display electrodes. In the subsequent first return period, a return pulse is supplied between the second display electrode and the address electrode, and a discharge is generated between the second display electrode and the address electrode in the first address period. Sometimes, a discharge in the opposite direction occurs between the second display electrode and the address electrode. In a subsequent second address period, a scan pulse is supplied to the second display electrode, and when an address pulse is supplied to the address electrode corresponding to the scan pulse, the second display electrode and the address Along with the discharge between the electrodes, a discharge occurs between the second and third display electrodes, and no discharge occurs between the first and second display electrodes.

  The first and second display cells share the second display electrode. When a discharge occurs between the second display electrode and the address electrode during the address selection of the first display cell in the first address period, a discharge in the opposite direction may be generated in the first return period. it can. Accordingly, the second display cell can be returned to the reset state, and appropriate address discharge can be performed in the second display cell in the second address period. At the time of resetting the first and second display cells, only the lit display cells can be erased and discharged, so that background light emission can be reduced and contrast can be improved.

(First embodiment)
FIG. 1 is a diagram illustrating a configuration example of a plasma display device according to a first embodiment of the present invention. The control circuit 20 controls the X drive circuit 17, the Y drive circuit 18, and the address drive circuit 19. The X drive circuit 17 supplies a predetermined voltage to the plurality of X electrodes X1, X2,. Hereinafter, each of the X electrodes X1, X2,... Or their generic name is referred to as an X electrode Xi, and i means a subscript. The Y drive circuit 18 supplies a predetermined voltage to a plurality of Y electrodes (scan electrodes) Y1, Y2,. Hereinafter, each of the Y electrodes Y1, Y2,... Or their generic name is referred to as a Y electrode Yi, and i means a subscript. The address drive circuit 19 supplies a predetermined voltage to the plurality of address electrodes A1, A2,. Hereinafter, each of the address electrodes A1, A2,... Or their generic name is referred to as an address electrode Aj, where j means a subscript.

  In the plasma display panel (display unit) 16, the Y electrode Yi and the X electrode Xi form a row extending in parallel in the horizontal direction, and the address electrode Aj forms a column extending in the vertical direction. The Y electrodes Yi and the X electrodes Xi are alternately arranged in the vertical direction. The Y electrode Yi and the address electrode Aj form a two-dimensional matrix with i rows and j columns. The display cell Cij is formed by the intersection of the Y electrode Yi and the address electrode Aj and the X electrode Xi adjacent thereto corresponding thereto. The display cell Cij corresponds to a pixel, and the panel 16 can display a two-dimensional image composed of a plurality of lines.

  FIG. 2A is a diagram illustrating a cross-sectional configuration example of the display cell Cij in FIG. X electrode Xi and Y electrode Yi are formed on front glass substrate 1211. A dielectric layer 1212 for insulating against the discharge space 1217 is deposited thereon, and an MgO (magnesium oxide) protective film 1213 is further deposited thereon.

  On the other hand, the address electrode Aj is formed on a rear glass substrate 1214 disposed to face the front glass substrate 1211, a dielectric layer 1215 is deposited thereon, and a phosphor is further deposited thereon. ing. Ne + Xe Penning gas or the like is sealed in the discharge space 1217 between the MgO protective film 1213 and the dielectric layer 1215.

  FIG. 2B is a diagram for explaining the capacitance Cp of the AC drive type plasma display. The capacity Ca is the capacity of the discharge space 1217 between the X electrode Xi and the Y electrode Yi. The capacitance Cb is the capacitance of the dielectric layer 1212 between the X electrode Xi and the Y electrode Yi. The capacitance Cc is the capacitance of the front glass substrate 1211 between the X electrode Xi and the Y electrode Yi. The total of these capacitances Ca, Cb, Cc determines the capacitance Cp between the electrodes Xi and Yi.

  FIG. 2C is a diagram for explaining light emission of the AC drive type plasma display. Red, blue, and green phosphors 1218 are arranged and applied in stripes on the inner surface of ribs (partitions) 1216 for each color, and pixels between the X electrode Xi and the Y electrode Yi (discharge electrode pair). The phosphor 1218 is excited by discharge for display to generate light 1221.

  FIG. 3 is a diagram illustrating a structure example of the X electrode 500x and the Y electrode 500y. The X electrode 500x corresponds to the X electrode Xi in FIGS. 1 and 2A to 2C, and includes a metal electrode (bus electrode) 501x and transparent electrodes (sustain electrodes) 502x connected to both sides thereof. The Y electrode 500y corresponds to the Y electrode Yi in FIGS. 1 and 2A to 2C, and includes a metal electrode (bus electrode) 501y and transparent electrodes (sustain electrodes) 502y connected to both sides thereof. The rib 503 corresponds to the rib 1216 in FIG. 2C and constitutes a box-type rib. Each display cell Cij is separated by a rib 503. A plurality of X electrodes 500x and Y electrodes 500y are alternately provided. A sustain discharge is performed between the transparent electrodes 502x and 502y. The Y electrode 502y constitutes two adjacent display cells between the X electrode 502x adjacent to both sides thereof. That is, the Y electrode 502y constitutes one display cell with the X electrode 502x adjacent to the upper side in the drawing, and constitutes another display cell with the X electrode 502x adjacent to the lower side thereof. To do. These two display cells constitute adjacent display cells.

  FIG. 4 is a diagram illustrating a schematic configuration example of an image frame FD. The two-dimensional image data is displayed on the panel 16 in units of frames. Each frame FD is formed by a first subframe SF1, a second subframe SF2,..., An nth subframe SFn. This n is, for example, 10, and corresponds to the number of gradation bits. Each of the subframes SF1, SF2, etc., or their generic name is hereinafter referred to as a subframe SF.

  Each subframe SF has a reset period Tr, an address period Ta, and a sustain (sustain discharge) period Ts. In the reset period Tr, the display cell is initialized. In the address period Ta, light emission or non-light emission of each display cell can be selected by address discharge between the address electrode Aj and the Y electrode Yi. Specifically, a scan pulse is sequentially applied to the Y electrodes Y1, Y2, Y3, Y4,..., And an address pulse is applied to the address electrode Aj corresponding to the scan pulse to thereby obtain a desired display cell. The light emission or non-light emission can be selected. In the sustain period Ts, a sustain discharge is performed between the X electrode Xi and the Y electrode Yi of the display cell in which light emission is selected, and light is emitted. In each subframe SF, the number of times of light emission (the length of the sustain period Ts) by the sustain pulse between the X electrode Xi and the Y electrode Yi is different. Thereby, the gradation value can be determined.

  FIG. 5 is a timing chart showing an example of driving waveforms of the plasma display apparatus according to the present embodiment. In order from the top of the figure, the voltage waveform of the address electrode Aj, the voltage waveform of the odd-numbered X electrode (first display electrode) Xo, the voltage waveform of the Y electrode (second display electrode) Yi, the even-numbered X electrode ( The voltage waveform of the third display electrode) Xe is shown.

  The X electrode Xo indicates a common voltage waveform of the odd-numbered X electrodes X1, X3, X5, etc. in FIG. The X electrode Xe shows a common voltage waveform of the even-numbered X electrodes X2, X4, X6, etc. in FIG. The Y electrode Yi shows a common voltage waveform of all the Y electrodes Yi, but only the timing of the scan pulse in the address periods Ta1 and Ta2 is different. That is, the Y drive circuit 18 sequentially supplies scan pulses to the plurality of Y electrodes Y1, Y2, Y3, Y4, etc. in the address periods Ta1 and Ta2. The address driving circuit 19 can select light emission (lighting) of each pixel of the panel 16 if an address pulse is applied to the address electrode Aj corresponding to the scan pulse, and non-light emission if no address pulse is applied. (Lights off) can be selected.

  The odd line Lo is composed of a display cell between the odd X electrode Xo and the Y electrode Yi below it. The even line Le is configured by a display cell between the Y electrode Yi and the even X electrode Xe below the Y electrode Yi. The odd line Lo can be address-selected in the first address period Ta1, and the even line Le can be address-selected in the second address period Ta2.

  In the odd line Lo, each subframe SF is in turn erased Te, first reset period Tr, first address period Ta1, sustain period Tb, second save period Tc2, second return period Tt2, and It has a sustain period Ts. In the even-numbered line Le, each subframe SF includes, in order, an erasing period Te, a first reset period Tr, a first save period Tc1, a first return period Tt1, a second reset period Td, and a second address period. It has Ta2 and a sustain period Ts.

  In the odd line Lo and the even line Le, the erase period Te, the first reset period Tr, and the sustain period Ts are common. The first address period Ta1 overlaps with the first save period Tc1, the sustain period Tb overlaps with the first return period Tt1, and the second save period Tc2 falls between the second reset period Td and the second address period Ta2. Overlap. The second return period Tt2 overlaps with the sustain period Ts of the even line Le.

  Hereinafter, the operation of the subframe SF will be described. In the erasing period Te, an erasing voltage (erasing pulse) is supplied between the X electrode Xo and the Y electrode Yi and between the Y electrode Yi and the X electrode Xe, so that the display cells of the odd line Lo and the even line Le are in the previous sub Erase discharge is performed only when address discharge occurs in the first and second address periods Ta1 and Ta2 of the frame SF, respectively. Details thereof will be described later.

  Next, in the first reset period Tr, a negative reset voltage is supplied to the Y electrode Yi. Only when the erasing discharge is performed in the erasing period Te, the discharging is performed in the first reset period Tr, and the display cell is reset. The reset voltage is a voltage whose voltage gradually changes. A negative blunt wave pulse is applied to the Y electrode Yi with respect to the electrodes Aj, Xo, and Xe. Since it is difficult to completely reset the display cell in the erasing period Te, the display cell is completely reset in the first reset period Tr.

  Next, in the first address period Ta1, when a scan pulse is supplied to the Y electrode Yi and an address pulse is supplied to the address electrode Aj corresponding to the scan pulse, the discharge between the Y electrode Yi and the address electrode Aj is performed. Accordingly, a discharge is generated between the Y electrode Yi and the X electrode Xo, and no discharge is generated between the Y electrode Yi and the X electrode Xe. Thereby, light emission or non-light emission of the display cell of the odd line Lo can be selected.

  In the first address period Ta1, by applying a scan pulse to the Y electrode Yi and applying an address pulse to the address electrode Aj in response to the scan pulse, a counter address discharge is generated between the Y electrode Yi and the address electrode Aj. The light emission or non-light emission of a desired display cell can be selected. If no address pulse is applied, non-light emission can be selected. In the first address period Ta1, the X electrode Xo has a positive potential and the Y electrode Yi has a negative potential. Therefore, discharge occurs between the X electrode Xo and the Y electrode Yi using the above-mentioned counter address discharge as a fire, and the X electrode Wall charges are generated on the Xo and Y electrodes Yi. On the other hand, in the first address period Ta1, the even-numbered X electrode Xe is 0V, so that no discharge is performed between the even-numbered X electrode Xe and the Y electrode Yi, and no light emission or non-light emission address selection is performed. In this way, while the odd line Lo is in the first address period Ta1, the even line Le is in the first save period Tc1 without performing address selection.

  Next, in the first return period Tt1, a return pulse is supplied between the Y electrode Yi and the address electrode Aj, and when a counter address discharge occurs between the Y electrode Yi and the address electrode Aj in the first address period Ta1, A discharge in the opposite direction occurs between the Y electrode Yi and the address electrode Aj.

  When the counter address discharge does not occur in the first address period Ta1, the display cells of the even line Le can maintain the reset state. However, when the counter address discharge occurs in the first address period Ta1, the display cell of the even line Le is destroyed in the reset state. Therefore, in the first return period Tt1, the display cells of the even lines Le are returned to the reset state.

  In the first return period Tt1, a voltage having a polarity opposite to that of the counter address discharge is applied between the Y electrode Yi and the address electrode Aj. That is, a return pulse that is positive with respect to the address electrode Aj is applied to the Y electrode Yi. Thereby, in the first return period Tt1, it is possible to cause a counter discharge in a direction opposite to the counter discharge in the first address period Ta1. Thereby, the display cell of the even line Le can be returned to the reset state, and the address can be selected in the next second address period Ta2. Note that, when the counter discharge is not performed in the first address period Ta1, the counter discharge does not occur in the first return period Tt1.

  In the sustain period Tb, since a sustain pulse is applied between the Y electrode Yi and the X electrode Xo, a sustain discharge is generated between the Y electrode Yi and the X electrode Xo when light emission is selected in the first address period Ta1. The display cells of the odd lines Lo emit light. At this time, since a positive potential is applied to the X electrode Xe, no discharge occurs between the X electrode Xe and the Y electrode Yi.

  Next, in the second reset period Td, a reset voltage is supplied to the Y electrode Yi. Only when the discharge is performed in the first return period Tt1, the discharge is performed in the second reset period Td, and the display cell is reset. The reset voltage is a voltage whose voltage gradually changes. The voltage in the second reset period Td is the same voltage as in the first reset period Tr. Since it is difficult to completely return the display cell to the reset state in the first return period Tt1, the display cell is completely returned to the reset state in the second reset period Td.

  Next, in the second address period Ta2, when a scan pulse is supplied to the Y electrode Yi and an address pulse is supplied to the address electrode Aj in response to the scan pulse, the discharge between the Y electrode Yi and the address electrode Aj is performed. Accordingly, a discharge is generated between the Y electrode Yi and the X electrode Xe, and no discharge is generated between the Y electrode Yi and the X electrode Xo. Thereby, it is possible to select light emission or non-light emission of the display cells of the even-numbered lines Le as in the first address period Ta1.

  In the second address period Ta2, by applying a scan pulse to the Y electrode Yi and applying an address pulse to the address electrode Aj corresponding to the scan pulse, a counter address discharge is generated between the Y electrode Yi and the address electrode Aj. The light emission or non-light emission of a desired display cell can be selected. If no address pulse is applied, non-light emission can be selected. In the second address period Ta2, the X electrode Xe is at a positive potential and the Y electrode Yi is at a negative potential. Therefore, discharge occurs between the X electrode Xe and the Y electrode Yi using the above-mentioned counter address discharge as a fire, and the X electrode Wall charges are generated at the Xe and Y electrodes Yi. On the other hand, in the second address period Ta2, since the X electrode Xo is 0 V, no discharge is performed between the X electrode Xo and the Y electrode Yi, and no light emission or no light emission address selection is performed. As described above, during the second address period Ta2 of the even line Le, the odd line Lo enters the second save period Tc2 without performing address selection.

  Next, in the second return period Tt2, a voltage having a polarity opposite to that of the counter address discharge in the second address period Ta2 is applied between the Y electrode Yi and the address electrode Aj. That is, a return pulse that is positive with respect to the address electrode Aj is applied to the Y electrode Yi. Thereby, in the second return period Tt2, the counter discharge in the direction opposite to the counter discharge in the second address period Ta2 can be performed. Thereby, the display cell of the odd line Lo can be returned to the address selected state. Note that, when the counter discharge is not performed in the second address period Ta2, the counter discharge does not occur in the second return period Tt2. In the Y electrode Yi, the return pulses in the return periods Tt1 and Tt2 have a higher potential than the sustain pulse in the sustain period Ts.

  The second return period Tt2 overlaps with the sustain period Ts of the even line Le. In the sustain period Ts, a sustain pulse is applied between the Y electrode Yi and the X electrode Xe. Therefore, when light emission is selected in the second address period Ta2, a sustain discharge is generated between the Y electrode Yi and the X electrode Xe. As a result, the display cell of the even line Le emits light. In the second return period Tt2, since a positive potential is applied to the X electrode Xo, no discharge occurs between the X electrode Xo and the Y electrode Yi.

  Next, in the sustain period Ts, a sustain pulse is supplied between the Y electrode Yi and the X electrode Xo and between the Y electrode Yi and the X electrode Xe. In the display cells of the odd lines Lo, when light emission is selected in the first address period Ta1, wall charges are generated in the Y electrode Yi and the X electrode Xo, and the Y electrode Yi and the X electrode are generated in the sustain period Ts. Sustain discharge occurs between Xo and emits light. In the display cells of the even lines Le, when light emission is selected in the second address period Ta2, wall charges are generated in the Y electrode Yi and the X electrode Xe, and in the sustain period Ts, the Y electrode Yi and Sustain discharge occurs between the X electrodes Xe to emit light.

  The above operation of the subframe SF is repeated. In the erasing period Te, an erasing voltage is supplied between the X electrode Xo and the Y electrode Yi and between the Y electrode Yi and the X electrode Xe. The erase voltage is a pulse voltage having a narrower pulse width than the sustain pulse in the sustain period Ts. Therefore, in the display cell of the odd line Lo, the erasing discharge is performed between the X electrode Xo and the Y electrode Yi only when the light emission is selected in the first address period Ta1 of the previous subframe SF and the counter address discharge is generated. , Wall charges are erased. When the counter address discharge is not generated, no erase discharge is performed between the X electrode Xo and the Y electrode Yi.

  In the display cell of the even line Le, the erasing discharge is performed between the X electrode Xe and the Y electrode Yi only when the light emission is selected in the second address period Ta2 of the previous subframe SF and the counter address discharge is generated. , Wall charges are erased. When the counter address discharge is not generated, no erase discharge is performed between the X electrode Xe and the Y electrode Yi.

  FIG. 7 is a timing chart showing an example of a drive waveform showing a subframe SF1 having a reset period Te1 in which all display cells are reset and discharged. For example, the subframes SF2 to SF10 have the same drive waveform as that of the subframe SF in FIG. The subframe SF1 is the same as the subframe SF of FIG. 5 in that a reset period Te1 is provided instead of the erasing period Te. In the erasing period Te, only the lit display cells are erased and discharged, and only the cells that are erased and discharged in the period Te are reset and discharged in the reset period Tr. On the other hand, in the reset period Te1, all display cells are reset and discharged, and in the subsequent reset period Tr, all cells are discharged.

  That is, in the reset period Te1, a reset voltage is supplied between the X electrode Xe and the Y electrode Yi and between the Y electrode Yi and the X electrode Xe, so that the display cells of the odd line Lo and the even line Le are in the previous subframe. The reset discharge is performed regardless of whether or not the counter address discharge has occurred in the first and second address periods Ta1 and Ta2. The reset voltage is a voltage whose voltage gradually changes, and has a high peak voltage (for example, 300 to 400 V).

  The drive waveform in FIG. 5 is designed so that the wall charge is substantially erased as the state of the non-lighting display cell. The normal subframe SF uses the waveform of FIG. 5, and at least one subframe SF in one frame FD is provided with a reset period Te1. In the reset period Te1, a positive obtuse wave voltage is applied to the Y electrode Yi, and in the subsequent first reset period Tr, a negative obtuse wave voltage is supplied, and a complete reset is performed for all display cells by the combination. In the present embodiment, a case where the all display cell reset is in the first subframe SF1 of the frame FD will be described as an example.

  First, in the first subframe SF1, all the display cells are reset to the non-lighting state in the reset period Te1 and the first reset period Tr. Here, the non-lighting state is a state where no discharge occurs even when a sustain pulse is applied. Now, the non-lighting state is a state in which the wall charges are substantially erased.

  In this state, the first address period Ta1 is entered. A display cell for selecting lighting / non-lighting is called an address side cell, and a display cell in a standby state is called a standby side cell. A pair of two display cells sharing the Y electrode Yi is formed. In the first address period Ta1, one of the display cells in the set is an address side cell, and the other is a standby side cell. The scan pulse is sequentially applied to the Y electrode Yi. When the potential of the address electrode Aj is high at the timing when the scan pulse is applied, an address discharge occurs in the address side cell. The address discharge is a discharge in which a counter discharge occurs between the address electrode Aj and the Y electrode Yi, and then a discharge occurs between the main electrodes (between the electrodes Xo and Yi). At this time, since the potential relationship between the address electrode Aj and the Y electrode Yi is the same in the standby cell, if the counter discharge occurs in the address side cell, the counter discharge also occurs in the standby cell. However, in the standby side cell, the voltage between the main electrodes is kept low so that no discharge occurs between the main electrodes (between the electrodes Xe and Yi).

  After the address selection of the odd lines Lo, which are half of all the lines, is completed in the first address period Ta1, the address selection of the remaining even lines Le is performed in the second address period Ta2. That is, the standby side cell and the address side cell are switched in the first and second address periods Ta1 and Ta2. Since the display cell in which the counter discharge has not occurred during the standby state in the first address period Ta1 holds the reset state, the display cell may enter the second address period Ta2 as it is. However, since the standby cell in which the counter discharge has occurred in the first address period Ta1 has changed from the reset state, it must be reset again before entering the second address period Ta2. For this purpose, the recovery is performed by the recovery pulse in the first recovery period Tt1, and the reset is performed by the negative blunt wave in the second reset period Td. The display cell in which the counter discharge has occurred causes another counter discharge by the return pulse, accumulates positive wall charges on the address electrode Aj side, and is reset by the subsequent negative blunt wave. The reset due to the obtuse wave is also characterized by a weak discharge opposite to the address electrode Aj and the Y electrode Yi. Then, address selection is performed in the second address period Ta2. The standby side cell that did not cause discharge in the first address period Ta1 does not cause discharge due to the return pulse and the negative blunt wave.

  The address side cell that has caused the address discharge in the first address period Ta1 causes the sustain discharge twice in the sustain period Tb corresponding to the first return period Tt1 of the return pulse, and the second reset period of the negative blunt wave No discharge occurs in the second evacuation period Tc2 corresponding to Td. In the second address period Ta2, positive charges are accumulated on the Y electrode Yi, so that no discharge occurs even when the scan pulse and the address pulse are applied simultaneously. On the other hand, the address side cell that did not cause an address discharge in the first address period Ta1 does not cause a discharge by a return pulse and a negative blunt wave, and remains in a reset state and becomes a standby side cell in the second address period Ta2. In this case, if an address discharge occurs in the address side cell, a counter discharge also occurs in the standby side cell. Since the wall charge is accumulated by this counter discharge, the wall charge is decreased by the return pulse of the second return period Tt2 immediately before the sustain period Ts so that the sustain discharge does not occur due to the wall charge.

  FIG. 6 is a diagram showing the presence / absence of discharge in each period in the subframe SF. A circle indicates that there is a discharge, and a cross indicates that there is no discharge. Hereinafter, eight patterns will be described.

  (1) No address discharge in the first address period Ta1 and no address discharge in the second address period Ta2. In that case, the display cells of the odd lines Lo are in the first address period Ta1, the first return period Tt1, the second reset period Td, the second address period Ta2, the second return period Tt2, and the sustain period Ts. Does not discharge at all.

  (2) The case where there is no address discharge in the first address period Ta1, and there is an address discharge in the second address period Ta2. In that case, the display cell of the odd line Lo has no discharge in the first address period Ta1, the first return period Tt1, and the second reset period Td, and in the second address period Ta2 and the second return period Tt2. There is discharge and there is no discharge in the sustain period Ts.

  (3) The case where there is an address discharge in the first address period Ta1, and there is no address discharge in the second address period Ta2. In that case, the display cells of the odd lines Lo are discharged in the first address period Ta1 and the first return period Tt1, and in the second reset period Td, the second address period Ta2 and the second return period Tt2. There is no discharge, and there is a discharge in the sustain period Ts.

  (4) This is a case where there is an address discharge in the first address period Ta1, and there is an address discharge in the second address period Ta2. In that case, the display cells of the odd lines Lo are discharged in the first address period Ta1 and the first return period Tt1, and are not discharged in the second reset period Td, the second address period Ta2 and the return period Tt2. There is a discharge in the sustain period Ts. In the display cells of the odd lines Lo, the address discharge is generated in the first address period Ta2 and the wall charges are generated. Therefore, the discharge is not generated in the second address period Ta2 and the second return period Tt2.

  (5) No address discharge in the first address period Ta1 and no address discharge in the second address period Ta2. In that case, the display cells of the even line Le are in the first address period Ta1, the first return period Tt1, the second reset period Td, the second address period Ta2, the second return period Tt2, and the sustain period Ts. Does not discharge at all.

  (6) This is a case where there is no address discharge in the first address period Ta1 and there is address discharge in the second address period Ta2. In that case, the display cell of the even line Le does not discharge in the first address period Ta1, the first return period Tt1 and the second reset period Td, and in the second address period Ta2 and the second return period Tt2. There is a discharge, and there is a discharge in the sustain period Ts.

  (7) This is a case where there is an address discharge in the first address period Ta1 and no address discharge in the second address period Ta2. In that case, the display cells of the even lines Le are discharged in the first address period Ta1, the first return period Tt1, and the second reset period Td, and in the second address period Ta2 and the second return period Tt2. There is no discharge and there is no discharge in the sustain period Ts.

  (8) This is a case where there is an address discharge in the first address period Ta1, and there is an address discharge in the second address period Ta2. In that case, the display cells of the even line Le are in the first address period Ta1, the first return period Tt1, the second reset period Td, the second address period Ta2, the second return period Tt2, and the sustain period Ts. Discharge all.

  Next, in FIG. 7, the discharge state in subframes SF2 to SF10 other than the first subframe SF1 will be described. Since the display cells that were not lit in the sustain period Ts of the previous subframe SF remain in the reset state, no discharge occurs in the first erase period Te and the first reset period Tr. On the other hand, the display cells that are in the lighting state in the sustain period Ts of the previous subframe SF cause reset discharge in the first reset period Ts after the wall charges are substantially erased by the erase pulse in the erase period Te. In any case, since all the cells are in the reset state after the first reset period Tr, the subsequent process is the same as that in the first subframe SF1, and the discharge state is the same as in FIG.

  In the present embodiment, two adjacent display cells share the same Y electrode Yi. When a discharge occurs between the Y electrode Yi and the address electrode Aj during the address selection of the display cell of the odd line Lo in the first address period Ta1, a discharge in the opposite direction is generated in the first return period Tt1. be able to. Thereby, the display cells of the even lines Le can be returned to the reset state, and appropriate address discharge can be performed in the display cells of the even lines Le in the second address period Ta2. In the erasing period Te, only the lit display cells of the previous subframe SF are erased and discharged, so that the background light emission is reduced and the contrast is improved as compared with the case where all the display cells are erased and discharged in all the subframes SF. it can.

(Second Embodiment)
FIG. 8 is a timing chart showing an example of a driving waveform of the plasma display device according to the second embodiment of the present invention, which differs from FIG. 5 in that an erasing period Te2 is provided instead of the erasing period Te. Is the same.

  In the erase period Te of FIG. 5, the wall charges are substantially erased by the narrow erase pulse, but in the erase period Te2 of FIG. 8, the wall charges are substantially erased by the obtuse wave erase voltage. The blunt wave erase voltage is a voltage whose voltage gradually changes. Also in this case, in the erasing period Te2, erasing discharge is performed only for the display cells that are lit in the sustain period Ts of the previous subframe SF.

  The blunt wave pulse in the erasing period Te2 in FIG. 8 is similar in shape to the blunt wave pulse in the reset period Te1 in FIG. 7, but has a different peak voltage value. The blunt wave pulse in the erasing period Te2 in FIG. 8 is a relatively low voltage having a peak voltage value of, for example, 150 to 200V, and therefore, only the lit display cells in the previous subframe SF can be erased and discharged. On the other hand, the blunt wave pulse in the reset period Te1 in FIG. 7 is a relatively high voltage with a peak voltage value of, for example, 300 to 400 V, so that it does not matter whether it is a lit display cell in the previous subframe SF. All display cells can be reset and discharged.

  As described above, in the plasma display devices of the first and second embodiments, if two adjacent display cells are the first and second display cells, the first display cell is an odd-numbered X electrode in FIG. (First display electrode) Xo and Y electrode (second display electrode) Yi below it, the second display cell is the same Y electrode Yi and even X electrode (third display electrode) Xe below it including. The first and second display cells share the same Y electrode Yi. The address electrode Aj is an electrode for performing address discharge with the Y electrode Yi.

  The Y electrodes Yi of two adjacent display cells arranged in the direction perpendicular to the direction in which the Y electrode Yi extends are electrically connected. Of the two adjacent display cells, when one of the display cells is selected, the other display cell is set in the standby state, and the counter discharge of the display cell is caused by the address discharge of the adjacent cell during the standby state. If it occurs, the wall charge state is returned to the original state by counter discharge in the first return period Tt1 after the standby state is completed.

  In order to reduce background light emission, the positive obtuse wave of reset in the above-mentioned Patent Document 1 is omitted, and only the display cells that have been lit in the previous subframe SF are reset. However, if the wall charge state is changed in all the display cells before the reset period, the positive obtuse wave and the negative obtuse wave are also applied to the display cells that are not lit to restore the original state. The reset by the combination of waves becomes indispensable, and the background light emission cannot be reduced.

  Even when two adjacent display cells share the Y electrode Yi, the wall charge on the address electrode Aj is not reduced in all the display cells before the reset period. Background light emission can be reduced if address selection is performed (or waits) without performing discharge in a period. However, if this is done, when the adjacent cells sharing the Y electrode Yi perform the address discharge during standby, the standby display cell also discharges oppositely. Therefore, after completion of the standby state, a return discharge may be caused to return the counter-discharged display cell to the original non-lit display cell state in the return period Tt1. In this return discharge, the state of the non-lighted display cell must not be moved, but the wall between the address electrode Aj and the Y electrode Yi is not used in the display cell in which the counter discharge has occurred in the standby state and the non-lighted display cell. Since there is a difference in voltage, it is desirable that the return discharge is performed by a counter discharge between the address electrode Aj and the Y electrode Yi. Thereby, background light emission can be reduced and the contrast can be improved.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

  The embodiment of the present invention can be applied in various ways as follows, for example.

(Appendix 1)
A first display cell including first and second display electrodes;
A second display cell including the second display electrode and the third display electrode;
An address electrode for discharging to and from the second display electrode;
A first display electrode driving circuit for supplying a voltage to the first display electrode;
A second display electrode driving circuit for supplying a voltage to the second display electrode;
A third display electrode driving circuit for supplying a voltage to the third display electrode;
An address electrode driving circuit for supplying a voltage to the address electrode,
In the first address period, a scan pulse is supplied to the second display electrode, and when an address pulse is supplied to the address electrode corresponding to the scan pulse, the interval between the second display electrode and the address electrode A discharge occurs between the first and second display electrodes along with the discharge, and no discharge occurs between the second and third display electrodes,
In the subsequent first return period, a return pulse is supplied between the second display electrode and the address electrode, and a discharge is generated between the second display electrode and the address electrode in the first address period. Sometimes, a discharge in the opposite direction occurs between the second display electrode and the address electrode,
In a subsequent second address period, a scan pulse is supplied to the second display electrode, and when an address pulse is supplied to the address electrode corresponding to the scan pulse, the second display electrode and the address A plasma display apparatus in which a discharge is generated between the second and third display electrodes along with a discharge between the electrodes, and no discharge is generated between the first and second display electrodes.
(Appendix 2)
Having a first reset period before the first address period;
The plasma display device according to appendix 1, wherein a reset voltage is supplied to the second display electrode in the first reset period.
(Appendix 3)
One frame has a plurality of subframes,
Each subframe has the first reset period, the first address period, the first return period, and the second address period,
An erasing period before the first reset period;
In the erasing period, an erasing voltage is supplied between the first and second display electrodes and between the second and third display electrodes, so that the first and second display cells are in the previous subframe. The plasma display apparatus according to appendix 2, wherein erasing discharge is performed only when the discharge is generated in each of the first and second address periods.
(Appendix 4)
A sustain period after the second address period;
In the sustain period, a sustain pulse is supplied between the first and second display electrodes and between the second and third display electrodes,
The plasma display apparatus according to claim 3, wherein the erase voltage is a pulse voltage having a narrower pulse width than the sustain pulse.
(Appendix 5)
The plasma display device according to appendix 4, wherein the reset voltage is a voltage whose voltage gradually changes.
(Appendix 6)
The plasma display apparatus according to appendix 3, wherein the erasing voltage is a voltage that gradually changes in voltage.
(Appendix 7)
One frame has a plurality of subframes,
Each subframe has the first reset period, the first address period, the first return period, and the second address period,
Having a reset period before the first reset period;
In the reset period, an erase voltage is supplied between the first and second display electrodes and between the second and third display electrodes, so that the first and second display cells are in the previous subframe. The plasma display apparatus according to claim 2, wherein reset discharge is performed regardless of whether or not the discharge has occurred in the first and second address periods.
(Appendix 8)
A second reset period after the first return period and before the second address period;
The plasma display apparatus according to appendix 2, wherein a reset voltage is supplied to the second display electrode in the second reset period.
(Appendix 9)
A second return period after the second address period;
In the second return period, a return pulse is supplied between the second display electrode and the address electrode, and when a discharge occurs between the second display electrode and the address electrode in the second address period. The plasma display device according to appendix 1, wherein a discharge in the opposite direction occurs between the second display electrode and the address electrode.
(Appendix 10)
A first display cell including first and second display electrodes;
A second display cell including the second display electrode and the third display electrode;
A driving method of a plasma display device having an address electrode for performing discharge with the second display electrode,
In the first address period, a scan pulse is supplied to the second display electrode, and when an address pulse is supplied to the address electrode corresponding to the scan pulse, the interval between the second display electrode and the address electrode A first address period step in which a discharge is generated between the first and second display electrodes and no discharge is generated between the second and third display electrodes.
In the first return period after the first address period, a return pulse is supplied between the second display electrode and the address electrode, and the second display electrode and the address electrode are supplied in the first address period. A first return period step in which a discharge in the opposite direction occurs between the second display electrode and the address electrode when a discharge occurs between the second display electrode and the address electrode;
In a second address period after the first return period, a scan pulse is supplied to the second display electrode, and when the address pulse is supplied to the address electrode in response to the scan pulse, the second address period A second address period step in which a discharge is generated between the second and third display electrodes in accordance with a discharge between the display electrode and the address electrode, and no discharge is generated between the first and second display electrodes. A method for driving a plasma display device.
(Appendix 11)
Having a first reset period before the first address period;
11. The driving method of the plasma display device according to appendix 10, wherein a reset voltage is supplied to the second display electrode in the first reset period.
(Appendix 12)
One frame has a plurality of subframes,
Each subframe has the first reset period, the first address period, the first return period, and the second address period,
An erasing period before the first reset period;
In the erasing period, an erasing voltage is supplied between the first and second display electrodes and between the second and third display electrodes, so that the first and second display cells are in the previous subframe. 12. The driving method of the plasma display device according to claim 11, wherein the erasing discharge is performed only when the discharge occurs in each of the first and second address periods.
(Appendix 13)
A sustain period after the second address period;
In the sustain period, a sustain pulse is supplied between the first and second display electrodes and between the second and third display electrodes,
The plasma display apparatus driving method according to claim 12, wherein the erase voltage is a pulse voltage having a narrower pulse width than the sustain pulse.
(Appendix 14)
14. The plasma display device driving method according to appendix 13, wherein the reset voltage is a voltage that gradually changes in voltage.
(Appendix 15)
The plasma display apparatus driving method according to appendix 12, wherein the erase voltage is a voltage whose voltage gradually changes.
(Appendix 16)
One frame has a plurality of subframes,
Each subframe has the first reset period, the first address period, the first return period, and the second address period,
Having a reset period before the first reset period;
In the reset period, an erase voltage is supplied between the first and second display electrodes and between the second and third display electrodes, so that the first and second display cells are in the previous subframe. 12. The driving method of the plasma display device according to claim 11, wherein reset discharge is performed regardless of whether or not the discharge has occurred in the first and second address periods.
(Appendix 17)
A second reset period after the first return period and before the second address period;
12. The driving method of the plasma display device according to appendix 11, wherein a reset voltage is supplied to the second display electrode in the second reset period.
(Appendix 18)
A second return period after the second address period;
In the second return period, a return pulse is supplied between the second display electrode and the address electrode, and when a discharge occurs between the second display electrode and the address electrode in the second address period. 11. The driving method of the plasma display device according to appendix 10, wherein a discharge in a direction opposite to that occurs between the second display electrode and the address electrode.

It is a figure which shows the structural example of the plasma display apparatus by the 1st Embodiment of this invention. 2A to 2C are diagrams showing an example of a cross-sectional configuration of the display cell of FIG. It is a figure which shows the structural example of X electrode and Y electrode. It is a figure which shows the schematic structural example of the frame of an image. It is a timing chart which shows the drive waveform example of the plasma display apparatus by 1st Embodiment. It is a figure which shows the presence or absence of the discharge in each period in a sub-frame. It is a timing chart which shows the example of a drive waveform which shows the sub-frame which has the erase period which erases and discharges all the display cells. 6 is a timing chart illustrating an example of a driving waveform of a plasma display device according to a second embodiment of the present invention.

Explanation of symbols

16 Plasma display panel 17 X drive circuit 18 Y drive circuit 19 Address drive circuit 20 Control circuit 1211 Front glass substrate 1212 Dielectric layer 1213 MgO protective film 1214 Rear glass substrate 1215 Dielectric layer 1216 Rib 1217 Discharge space 1221 Light

Claims (10)

A first display cell including first and second display electrodes;
A second display cell including the second display electrode and the third display electrode;
An address electrode for discharging to and from the second display electrode;
A first display electrode driving circuit for supplying a voltage to the first display electrode;
A second display electrode driving circuit for supplying a voltage to the second display electrode;
A third display electrode driving circuit for supplying a voltage to the third display electrode;
An address electrode driving circuit for supplying a voltage to the address electrode,
In the first address period, a scan pulse is supplied to the second display electrode, and when an address pulse is supplied to the address electrode corresponding to the scan pulse, the second display electrode and the address electrode are connected. A discharge occurs between the first and second display electrodes along with the discharge, and no discharge occurs between the second and third display electrodes,
In a subsequent first return period, a return pulse is supplied between the second display electrode and the address electrode, and a discharge is generated between the second display electrode and the address electrode in the first address period. Sometimes, a discharge in the opposite direction occurs between the second display electrode and the address electrode,
In a subsequent second address period, a scan pulse is supplied to the second display electrode, and when an address pulse is supplied to the address electrode corresponding to the scan pulse, the second display electrode and the address A plasma display apparatus in which a discharge is generated between the second and third display electrodes along with a discharge between the electrodes, and no discharge is generated between the first and second display electrodes. Having a first reset period before the first address period;
The plasma display apparatus according to claim 1, wherein a reset voltage is supplied to the second display electrode in the first reset period. One frame has a plurality of subframes,
Each subframe has the first reset period, the first address period, the first return period, and the second address period,
An erasing period before the first reset period;
In the erasing period, an erasing voltage is supplied between the first and second display electrodes and between the second and third display electrodes, so that the first and second display cells are in the previous subframe. 3. The plasma display apparatus according to claim 2, wherein the erasing discharge is performed only when the discharge is generated in each of the first and second address periods. A sustain period after the second address period;
In the sustain period, a sustain pulse is supplied between the first and second display electrodes and between the second and third display electrodes,
The plasma display apparatus of claim 3, wherein the erase voltage is a pulse voltage having a narrower pulse width than the sustain pulse.   The plasma display apparatus according to claim 4, wherein the reset voltage is a voltage whose voltage gradually changes.   4. The plasma display apparatus according to claim 3, wherein the erase voltage is a voltage whose voltage gradually changes. One frame has a plurality of subframes,
Each subframe has the first reset period, the first address period, the first return period, and the second address period,
Having a reset period before the first reset period;
In the reset period, a reset voltage is supplied between the first and second display electrodes and between the second and third display electrodes, so that the first and second display cells are in the previous subframe. The plasma display apparatus according to claim 2, wherein reset discharge is performed regardless of whether or not the discharge has occurred in the first and second address periods. A second reset period after the first return period and before the second address period;
The plasma display apparatus according to claim 2, wherein a reset voltage is supplied to the second display electrode in the second reset period. A second return period after the second address period;
In the second return period, a return pulse is supplied between the second display electrode and the address electrode, and when a discharge occurs between the second display electrode and the address electrode in the second address period. 2. The plasma display apparatus according to claim 1, wherein a discharge in the opposite direction occurs between the second display electrode and the address electrode. A first display cell including first and second display electrodes;
A second display cell including the second display electrode and the third display electrode;
A driving method of a plasma display device having an address electrode for performing discharge with the second display electrode,
In the first address period, a scan pulse is supplied to the second display electrode, and when an address pulse is supplied to the address electrode corresponding to the scan pulse, the interval between the second display electrode and the address electrode A first address period step in which a discharge is generated between the first and second display electrodes and no discharge is generated between the second and third display electrodes.
In the first return period after the first address period, a return pulse is supplied between the second display electrode and the address electrode, and the second display electrode and the address electrode are supplied in the first address period. A first return period step in which a discharge in the opposite direction occurs between the second display electrode and the address electrode when a discharge occurs between the second display electrode and the address electrode;
In a second address period after the first return period, a scan pulse is supplied to the second display electrode, and when the address pulse is supplied to the address electrode in response to the scan pulse, the second address period A second address period step in which a discharge is generated between the second and third display electrodes in accordance with a discharge between the display electrode and the address electrode, and no discharge is generated between the first and second display electrodes. A method for driving a plasma display device.

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