JP2008097045A - Driving method of plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such a problem that electric charges are distortedly accumulated in the conventional plasma display panel and abnormal electric discharge is generated in a certain usage. <P>SOLUTION: The driving method of a plasma display panel having a plurality of first electrodes X, a plurality of second electrodes Y disposed adjacent to and alternately with each other and a plurality of third electrodes A so as to cross the first and second electrodes comprises: a step of performing reset discharge between the first electrodes and the second electrodes; a step of performing address discharge between the second electrodes and the third electrodes; and a step of performing auxiliary discharge of a scale of at least the sustain discharge which is performed just precedently, after performing sustain discharge by alternately applying sustain pulses to the first and second electrodes and before performing the reset discharge in a subsequent field. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a plasma display panel driving technique, and more particularly to an ALIS plasma display panel and a driving method thereof.

  In recent years, an ALIS (Alternate Lighting of Surfaces Method) PDP has been provided as a plasma display panel (PDP) with high definition and a high aperture ratio. In such an ALIS PDP, for example, in order to avoid flicker, information such as characters may be displayed by repeating only one of the fields. In such a case, charges are unevenly accumulated on the display panel. There is a risk of abnormal discharge. Therefore, there is a demand for providing a PDP driving technique capable of preventing such abnormal discharge.

  FIG. 1 is a diagram showing an ALIS system plasma display panel (PDP) to which the present invention is applied in comparison with a conventional plasma display panel. FIG. 1 (a) shows a conventional PDP (for example, VGA: display line is a display line). 480) and FIG. 1B shows an ALIS PDP (for example, 1024 display lines).

  As shown in FIG. 1A, in the conventional PDP, two display electrodes are arranged in parallel, and display discharge is performed between the electrodes. For example, when the number of display lines is 480 (VGA), 480 × 2 = 960 display electrodes are necessary.

  On the other hand, the ALIS PDP is disclosed in, for example, Japanese Patent Publication No. 2801893 (Japanese Patent Laid-Open No. 9-160525) and discharges between all adjacent electrodes as shown in FIG. Therefore, when the number of display lines is +1, for example, when the number of display lines is 1024, 1024 + 1 = 1025 display electrodes are sufficient.

  In other words, the ALIS PDP can achieve double the definition with the same number of electrodes as the conventional one, and further, by using the discharge space without waste and minimizing light shielding by the electrodes, etc. An aperture ratio is possible, and high luminance can be realized.

  FIG. 2 is a diagram for explaining the display method of the ALIS PDP, and shows an example in which the character “A” is displayed. 2, X electrodes X1, X2,... And Y electrodes Y1, Y2,... Are display electrodes (sustain electrodes), and A1, A2,.

  As shown in FIG. 2, the ALIS system display method divides the image display into odd lines and even lines in terms of time. For example, an X electrode (X1, X2,...) And a Y electrode (Y1 below it) , Y2,...) Display of odd lines (display lines <1>, <3>, <5>,...) By discharge between them, and Y electrodes (Y1, Y2,. (X2, X3,...) Are combined with the display of even lines (display lines <2>, <4>, <6>,...) By discharge to display the entire image. It is similar to interlaced scanning.

  3A and 3B are diagrams for explaining the operation principle of the ALIS PDP. FIG. 3A shows the operation during discharge (display) of odd lines, and FIG. 3B shows the discharge of even lines. The operation during (display) is shown.

  As shown in FIG. 3A, for example, odd-numbered X electrodes X1, X3,... Are grounded in order to cause stable discharge in odd-numbered display lines (display lines <1>, <3>,...). (For example, 0 volt), the voltage Vs is applied to the odd-numbered Y electrodes Y1, (Y3),... And the voltage Vs is applied to the even-numbered X electrodes X2, (X4),. The Y electrodes Y2, (Y4),... Are grounded. As a result, discharge is generated on the odd display lines <1>, <3>,..., And no discharge is generated on the even display lines <2>, <4>,. That is, in the first display line <1>, a discharge occurs due to the voltage (Vs) between the grounded first X electrode X1 and the first Y electrode Y1 to which the voltage Vs is applied, In the third display line <3>, discharge is generated by the voltage (Vs) between the second X electrode X2 to which the voltage Vs is applied and the second Y electrode Y2 that is grounded. At this time, in the second display line <2>, there is no potential difference between the first Y electrode Y1 to which the voltage Vs is applied and the second X electrode X2 to which the voltage Vs is applied. In the fourth display line <4>, no potential difference is generated between the grounded second Y electrode Y2 and the grounded third X electrode X3, so that no discharge occurs.

  On the other hand, as shown in FIG. 3B, in order to cause stable discharge in even-numbered display lines (display lines <2>, <4>,...), For example, odd-numbered X electrodes X1, X3,. The voltage Vs is applied to the odd-numbered Y electrodes Y1, (Y3), ..., and the even-numbered X electrodes X2, (X4), ... and the even-numbered Y electrodes Y2, (Y4), ... are grounded. As a result, a discharge is generated in the even display lines <2>, <4>,..., And a discharge is not generated in the odd display lines <1>, <3>,. That is, in the second display line <2>, a discharge occurs due to the voltage (Vs) between the first Y electrode Y1 to which the voltage Vs is applied and the second X electrode X2 that is grounded, In the fourth display line <4>, discharge is generated by the voltage (Vs) between the grounded second Y electrode Y2 and the third X electrode X3 to which the voltage Vs is applied. At this time, in the first display line <1>, there is no potential difference between the first X electrode X1 to which the voltage Vs is applied and the first Y electrode Y1 to which the voltage Vs is applied. Also, no discharge occurs in the third display line <3> because there is no potential difference between the grounded second X electrode X2 and the grounded second Y electrode Y2.

  By alternately repeating the odd line discharge shown in FIG. 3A and the even line discharge shown in FIG. 3B, the odd line discharge and the even line discharge are combined to display the entire image. It will be.

  FIG. 4 is a diagram showing an example of a display sequence of the ALIS PDP.

  As described above, in the ALIS system PDP, the display of the entire screen is divided into the display of odd lines (discharge) and the display of even lines. Therefore, as shown in FIG. Divided into fields and even fields. Each of these odd and even fields is further divided into a plurality (n) of subfields (1SF to nSF). Here, dividing each field into a plurality of subfields is necessary for gradation display, but usually, about 8 to 12 subfields (in order to realize about 50 to 300 gradations). SF).

  Each subfield (1SF to nSF) has a reset period (not shown in FIG. 4: before the address period) for initializing the state of the discharge cell, and performs writing to the lighted cell according to display data. It is divided into an address period and a display period (sustain period) for performing display by the cell selected in the address period. Note that repeated discharge (sustain discharge) is performed in the display period, and the luminance weight of each subfield is determined depending on the number of times.

  FIG. 5 is a diagram (part 1: odd field) showing an example of an ALIS drive waveform, and FIG. 6 is a diagram (part 2: even field) showing an example of an ALIS drive waveform, one subfield each. The drive waveform is shown.

  As shown in FIG. 5, in the drive waveform of one subfield in the odd field, a voltage pulse is applied between all adjacent X electrodes X1, X2,... And Y electrodes Y1, Y2,. Then, initialization discharge (reset discharge) is performed, and in the address period, selection pulses (scan pulses) are sequentially applied to the Y electrodes Y1, Y2,..., And address electrodes (A1, A2) corresponding to the selected cells ,...), An address pulse is applied to perform an address discharge (address discharge). After the reset discharge and the write discharge are executed over all the screens, a sustain pulse is alternately applied to the X electrode and the Y electrode to perform a sustain discharge (sustain discharge). FIG. 5 shows an odd field drive waveform for displaying odd lines (odd display lines <1>, <3>,...), In which address discharge and sustain discharge are generated only in the odd display lines. Ingenuity has been made.

  FIG. 6 shows the drive waveform of the even field for displaying the even lines (even display lines <2>, <4>,...), And corresponds to the drive waveform in the odd field shown in FIG. In FIG. 6, a device is devised such that address discharge and sustain discharge are generated only in even-numbered display lines.

  FIG. 7 is a block circuit diagram showing an example of an ALIS PDP (PDP apparatus) to which the present invention is applied. In FIG. 7, reference numeral 101 is a control circuit, 121 is an odd X electrode sustain circuit (PX1), 122 is an even X electrode sustain circuit (PX2), 131 is an odd Y electrode sustain circuit (PY1), and 132 is an even number. Y electrode sustain circuit (PY2), 104 is an address circuit (address driver), 105 is a scanning circuit (scan driver), and 106 is a display panel (PDP).

  The control circuit 101 converts display data DATA supplied from the outside into data for the display panel 106 and supplies the data to the address circuit 104. Furthermore, the control circuit 101 supplies the clock CLK, the vertical synchronization signal VSYNC, and the horizontal synchronization signal HSYNC supplied from the outside. Various control signals are generated according to the above, and various circuits (121, 122, 131, 132, 104, 105) are controlled. In order to apply the voltage waveforms as shown in FIG. 5 and FIG. 6 to the respective electrodes, the power supply circuit (not shown) supplies the odd-numbered X electrode sustain circuit 121, the even-numbered X electrode sustain circuit 122, and the odd-numbered Y. A predetermined voltage is supplied to each of the electrode sustain circuit 131, the even-numbered Y electrode sustain circuit 132, the address circuit 104, and the scanning circuit 105.

  FIG. 8 is a diagram showing an example of a panel structure in an ALIS PDP. Although the display panel 106 may be either color or monochrome, FIG. 8 shows a color display panel.

  As shown in FIG. 8, the front glass substrate 161 has an X electrode and a Y electrode constituted by transparent electrodes 1631, 1632, 1633,..., Such as an IT0 film, and metal electrodes 1641, 1642, 1643,. X1, Y1, X2,... Are alternately formed in parallel. Here, for example, in the X electrode X1, the metal electrode 1641 is provided along the longitudinal direction of the transparent electrode 1631 in order to reduce the voltage drop due to the transparent electrode 1631. The transparent electrodes 1631, 1632, 1633,... And the metal electrodes 1641, 1642, 1643,... Constituting the X electrode and the Y electrodes X1, Y1, X2,. A dielectric for retaining wall charges and a protective film (not shown) such as MgO are provided throughout.

  In the rear glass substrate 162, on the surface facing the MgO protective film of the front glass substrate 161, the address electrodes A1, A2, A3,... In the direction orthogonal to the X electrodes and Y electrodes X1, Y1, X2,. A partition wall 1650 is formed surrounding each address electrode. The phosphors 1651, 1652, 1653 that emit ultraviolet light generated by the discharge and emit colors (red R, green G, blue B) on the address electrodes A1, A2, A3,. , ... are attached. Note that, for example, a Ne + Xe Penning mixed gas is sealed in a discharge space between the MgO protective film (inner surface) of the front glass substrate 161 and the phosphor (inner surface) of the rear glass substrate 162.

  Here, the odd-numbered X electrodes X1 (X3, X5,...) On the front glass substrate 161 are connected to the odd-numbered X-electrode sustain circuit 121 shown in FIG. 7, and the even-numbered X electrodes X2 (X4, X6,. The odd-numbered Y electrodes Y1 (Y3, Y5,...) Are connected to the odd-numbered Y-electrode sustain circuit 131 via the scanning circuit (scanning driving IC) 105, and The even-numbered Y electrodes (Y2, Y4, Y6,...) Are connected to the even-numbered Y-electrode sustain circuit 132 via the scanning circuit 105, and the above-described ALIS driving is performed.

  FIG. 9 is a diagram showing a state in which fixed display is performed by one field (odd field), and FIG. 10 is a diagram showing an example of a fixed display lighting sequence by only one field shown in FIG.

  As described above, for example, the ALIS PDP is driven by lighting the odd lines and the even lines in different fields as shown in FIG. That is, the display sequence in the ALIS PDP has a display form similar to interlaced display, and therefore, when one line is lit, for example, 30 Hz flicker occurs. Usually, video display is not so much a problem as a cathode ray tube, but when PDP is used for displaying information such as characters, it is preferable that there is no flicker. In such applications, the line to be displayed is fixed. In other words, display is always performed by repeating odd or even fields.

  That is, in the ALIS PDP, when there is a request that the resolution may be half but flicker is avoided (for example, in the case of displaying information such as characters), for example, as shown in FIG. Only (for example, an odd field) is repeatedly displayed. In this case, as is clear from FIG. 9, the number of lines that can be displayed is half of the total number of lines.

  FIGS. 11 to 15 are diagrams for explaining the problem of fixed display in the ALIS PDP. 11 to 15, reference numeral 161 indicates a front glass substrate, and 162 indicates a rear glass substrate.

  As described above, for example, when displaying (for example, displaying information such as characters) using only one field (for example, odd field) in the ALIS PDP, as shown in FIG. Since the direction of discharge is always the same direction, by repeating such driving (display), a charge bias as shown in FIG. 12A occurs on the display panel.

  That is, FIG. 11 shows the state of the address discharge. For example, the discharge in the address period is between the address electrode (A) provided on the rear glass substrate 162 and the Y electrode provided on the front glass substrate 161. Using the discharge as a trigger, a discharge occurs between the X electrode and the Y electrode of the front glass substrate 161. At this time, a pulse of about 50 to 80 V is applied to the address electrode according to display data, and a scan pulse of about −150 V to −200 V is applied to the Y electrode. As a result, the voltage between the address electrode and the Y electrode exceeds the discharge start voltage, and discharge starts. In addition, by applying a voltage of about 50 to 100 V to the X electrode, the discharge generated between the address electrode and the Y electrode spreads between the X electrode and the Y electrode, and the discharge converges due to the accumulation of wall charges. To do. Electrons and ions generated by the discharge are moved by an electric field in the discharge space, and electrons move to the X electrode side which is an anode, and ions move to the Y electrode side which is a cathode. In the sustain discharge after the address discharge, the discharge is performed with the reverse polarity, but the sustain discharge is performed with a voltage of about 150 to 180 V lower than about 200 V that is the potential difference between the X electrode and the Y electrode at the time of addressing. The charge that has moved at the time of addressing cannot be completely returned.

  By repeating the above operation, for example, electrons move to the left side (upper side of the display panel) in FIG. 12A, and the right side (lower side of the display panel) from which electrons have been removed has ions on the right side. Excessive state. Although the details of such a phenomenon have not been fully elucidated, it is thought that the mobility of electrons is larger than that of ions.

  Then, if the amount of charge accumulated by the above display operation is repeated to a certain level or more, as shown in FIG. 12B, a large-scale abnormality occurs at a considerable distance beyond the pair of the X electrode and the Y electrode. Discharge may occur. Such abnormal discharge may hinder subsequent normal operation or damage the circuit by breaking the insulating film with a large current.

  Further, as shown in FIG. 13, when the biased charge is accumulated on the address electrode (A) side of the rear glass substrate 162 or on the sustain electrode (X electrode, Y electrode) side of the front glass substrate 161. Sometimes it accumulates. For example, in the case of the driving waveform shown in FIG. 5 described above, the address electrode is always 0 V in the sustain period, so that the address electrode is at the end of the sustain period. A positive charge biased to the side is held. In this case, when the address discharge is executed (implemented) in the next subfield, the wall discharge acts in a form superimposed on the applied voltage on the address electrode side, so that the address discharge may become enormous. In the case of a large discharge compared to a normal address discharge, a display abnormality such as writing to an adjacent cell may be caused.

  Furthermore, as shown in FIG. 14, if there is a defect in a barrier (partition wall) for partitioning adjacent cells, abnormal discharge may be caused. In FIG. 14, reference numeral 165 indicates a phosphor (R1651, G1652, B1653), and 1650 indicates a partition wall. FIG. 15A and FIG. 15B show how this abnormal discharge occurs.

  In the case where address discharge is performed in the center cell CE2 in FIG. 14 and the cells CE1 and CE3 adjacent to both sides thereof are off (that is, no address discharge is performed), if the partition wall 1650 has a defect F, for example, the address Since the space between the discharged cell CE2 and the cell CE3 on the right side of the cell CE2 is coupled, the charge generated by the address discharge of the cell CE2 may move to the adjacent cell CE3 and be discharged. This phenomenon may occur, for example, even when the defect F of the partition wall 1650 is a gap of about 5 μm. When the address discharge becomes huge due to the accumulation of the biased charges as described above, the gap becomes smaller. Even if it exists, it causes discharge of adjacent cells. The gap between the front glass substrate 161 and the rear glass substrate 162 is, for example, about 100 to 150 μm.

  As a result, for example, after performing a normal address discharge in the selected cell as shown in FIG. 15A, an erroneous discharge due to a charge leak from an adjacent cell as shown in FIG. Will continue to occur. Here, FIG. 15A shows a cell CE2 composed of the address electrode A2 and the sustain electrode (X electrode X2, Y electrode Y2), and FIG. 15B shows the address electrode A3 and the sustain electrode (X2, X2). A cell CE3 constituted by Y2) is shown.

  An object of the present invention is to prevent abnormal discharge by eliminating the accumulation of biased charges on a display panel in view of the problems of the above-described conventional plasma display panel driving technology. It is another object of the present invention to prevent a miss address in which discharge is started only by an erase pulse even if an address pulse is not applied in an address period.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  According to the first aspect of the present invention, a plasma in which a plurality of first electrodes and second electrodes are alternately arranged adjacent to each other, and a third electrode is formed so as to cross the first and second electrodes. A display panel driving method, wherein a reset discharge is performed between the first electrode and the second electrode, and an address discharge is performed between the second electrode and the third electrode. After the sustain discharge is performed by alternately applying the sustain pulse to the first and second electrodes, and before the reset discharge in the next field, the sustain discharge more than that performed immediately before is performed. A method of driving a plasma display panel, characterized by performing auxiliary discharge of a scale, is provided.

  According to the second aspect of the present invention, a plurality of first electrodes and second electrodes are alternately arranged adjacent to each other, and a third electrode is formed so as to cross the first and second electrodes, A method for driving a plasma display panel, wherein an erase pulse having a gentle slope is applied to a second electrode to which a scan pulse is applied at a reset time, and is set to a voltage equivalent to the scan pulse at the final stage of the erase pulse. There is provided a method for driving a plasma display panel, characterized in that the pulse voltage is sharply changed until

  According to the third aspect of the present invention, a plurality of first electrodes, a plurality of second electrodes arranged alternately adjacent to the first electrodes, and the first and second electrodes A plurality of third electrodes arranged so as to cross each other, and a reset discharge is performed between the first electrode and the second electrode, and between the second electrode and the third electrode, A control circuit for performing an address discharge between the first and second electrodes, the control circuit performing a sustain discharge by alternately applying a sustain pulse to the first and second electrodes. Provided is a plasma display panel characterized in that an auxiliary discharge having a magnitude larger than the sustain discharge performed immediately before is performed before the reset discharge.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, abnormal charge accumulation on the display panel can be eliminated and abnormal discharge can be prevented. Furthermore, according to the present invention, it is possible to prevent a misaddress in which discharge is started only by an erase pulse even if an address pulse is not applied in the address period.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  Hereinafter, embodiments of a method for driving a plasma display panel (PDP) according to the present invention will be described in detail with reference to the drawings.

  First, the driving waveform in the first embodiment of the PDP driving method of the present invention will be described in comparison with the driving waveform in the conventional PDP driving method.

  FIG. 16 is a diagram showing an example of a driving waveform in a conventional PDP driving method, and FIG. 17 is a diagram showing a driving waveform in the first embodiment of the PDP driving method according to the present invention. 16 and 17, reference symbol A indicates a waveform applied to the address electrode (A2), X indicates a waveform applied to the X electrode (X2), and Y indicates a waveform applied to the Y electrode (Y2). Is shown.

  As is clear from the comparison between FIG. 16 and FIG. 17, in the first embodiment, the address electrode (A: A2) and the X electrode (before the sustain discharge is started after the address period ends (before the sustain period)). The additional pulses P1 and P2 are applied to X: X2), and the wall charges of the cells in which the erroneous discharge has occurred are extinguished by the auxiliary discharge.

  That is, as shown in FIG. 17, in the first embodiment, a pulse having a positive polarity with respect to the address electrode in an additional pulse period between the address period (address discharge period) and the sustain period (sustain discharge period). P1 (here, the same voltage as the address pulse (for example, 50V) is applied for simplification of the circuit), and a negative pulse (for example, −50V) is applied to the X electrode. By applying such a pulse (additional pulse), it is possible to cause auxiliary discharge only in cells that have been erroneously discharged.

  FIG. 18 is a diagram for explaining the operation of the PDP driving method shown in FIG. Here, FIG. 18A shows a state immediately after applying the additional pulse shown in FIG. 17 after performing the normal address discharge of FIG. 15A described above, and FIG. 18B shows the application of the additional pulse. It is a figure for demonstrating the operation | movement by.

  As shown in FIG. 18A, the cell (CE2) that has performed normal address discharge causes discharge because negative wall charges are formed on the address electrode (A2) side by the address discharge. There is no. On the other hand, as shown in FIG. 15B described above, in the cell (CE3) that has been discharged in the address period due to the influence of the adjacent cell (CE2), the address electrode at the time of discharge has a non-selection potential. Since the voltage is 0 V, even if a discharge is generated between the X electrode (X2) and the Y electrode (Y2), relatively no charge is formed.

  Therefore, in the first embodiment, as shown in FIGS. 17 and 18B, a positive pulse P1 (for example, 50V) is applied to the address electrode (A2) and the X electrode (X2) is applied. ) Is applied with a positive pulse P2 (for example, −50 V), and discharge is started between the address electrode (A2) and the X electrode (X2). After the start of discharge, the discharge converges as the formation of wall charges proceeds. However, since the potential difference between the X electrode (X2) and the Y electrode (Y2) is about 50 V, this discharge is compared with a normal sustain discharge. The wall charges that are immediately converged and the amount of wall charges that are formed are very small.

  With this small amount of wall charges, the sustain discharge is not started even when the sustain pulse is applied next, so that the extinction state can be realized. It should be noted that if the voltage value of the negative pulse P2 applied to the X electrode is too large, it may cause a discharge even in a cell in which a normal address discharge has been performed and erase the charge. In the first embodiment, about -50V was the limit. Further, the minimum value of the negative pulse P2 in which the effect of the first embodiment appears is about −30V.

  FIG. 19 is a diagram showing drive waveforms in the second embodiment of the PDP drive method according to the present invention.

  In the first embodiment shown in FIG. 17 described above, the voltage of the Y electrode (Y2) is 0V, but as shown in FIGS. 18 (a) and 18 (b), a positive voltage is present on the Y electrode (Y2). When a negative voltage is applied to the X electrode (X2) in the normally addressed cell (CE2), discharge starts between the X electrode (X2) and the Y electrode (Y2). Then, the case where the wall charges formed by the address discharge are eliminated can be considered. Therefore, in the second embodiment, in order to prevent the disappearance of such wall charges, the negative pulse P3 is also applied to the Y electrode (Y2). Even when a large negative polarity pulse was applied to the X electrode, the adverse effect on the cell that performed normal address discharge was avoided, and the effects of the present invention could be further enhanced. In the experiment, the voltage of the negative pulse (P3) applied to the Y electrode was set to be equal to the non-selection potential of the Y electrode during the address period (for example, −50 V).

  In the first and second embodiments described above, the occurrence of erroneous discharge cannot be prevented in the address period, but excessive lighting is prevented by eliminating the wall charges of the erroneously discharged cells before entering the sustain period. be able to.

  Next, an embodiment relating to a method for preventing excessive lighting in the address period will be described.

  As shown in FIGS. 11 to 14 described above, enormous address discharge is a phenomenon that occurs when the address discharge is always performed in a certain direction, and the charge is formed in a certain direction. As shown in FIGS. 13 and 14, it is likely to occur when a positive charge is formed on the address electrode side. There is a phosphor 165 on the address electrode (A) side, and unlike the MgO film (protective film) on the sustain electrode (X electrode and Y electrode) side, the phosphor 165 has several μm of various shapes depending on the material. Particles. That is, since the phosphor 165 is a film of around 10 microns with several μm particles overlapped, cavities are present everywhere, and the total surface area is larger than that of the MgO surface. ing. Then, when charged particles such as electrons and ions sink into and adhere to the fluorescent substance 165 where cavities exist everywhere, the charged particles cannot be removed due to the influence of weak reset discharge or sustain discharge, and are deposited. As a result, a huge discharge is caused.

  An embodiment in which the above charged particles are removed will now be described.

  FIG. 20 is a diagram showing drive waveforms in the third embodiment of the PDP drive method according to the present invention.

  As apparent from the comparison between FIG. 20 and FIG. 16, in the third embodiment, after the normal sustain discharge period (sustain period) is completed, the voltage (equivalent to the scan pulse) is applied to the Y electrode (Y2). For example, a negative pulse P5 of about −150 V is applied, and a positive pulse P4 of a voltage equivalent to the address pulse (for example, about 50 V) is applied to the address electrode (A2). Since these additional pulses P4 and P5 are inserted after the discharge with the positive sustain pulse of the Y electrode, the discharge between the address electrode and the Y electrode is generated together with the discharge between the X electrode and the Y electrode. Thus, a large discharge (auxiliary discharge) occurs, and the positive charge accumulated on the address electrode side can be removed.

  FIG. 21 is a diagram showing drive waveforms in the fourth embodiment of the PDP drive method according to the present invention.

  As is clear from the comparison between FIG. 21 and FIG. 20, the fourth embodiment is different from the third embodiment described above with respect to the X electrode (X2) in the additional pulse period after the end of the sustain period. Also, a positive pulse P6 is applied. As a result, a larger discharge (auxiliary discharge) is caused in the additional pulse period, and charges accumulated on the address electrode side are more effectively removed. The voltage of the additional pulse P6 applied to the X electrode can be, for example, the same voltage (for example, about 50 V) as the voltage of the X electrode applied during the address period.

  FIG. 22 is a diagram showing drive waveforms in the fifth embodiment of the PDP drive method according to the present invention.

  In the third embodiment of FIG. 20 and the fourth embodiment of FIG. 21 described above, the additional pulse P4 is applied to the address electrode (A2), so the address electrode (A2) and the Y electrode (Y2) at that time Depending on the voltage between them, discharge may occur in all cells that have been extinguished.

  By the way, the additional pulse P4 applied to the address electrode is set to the same voltage (for example, about 50 V) as the address pulse in the address period, and the additional pulse P5 applied to the Y electrode (Y2) is set to the same voltage (for example, − In the case of about 150 V), discharge is surely generated in all cells. That is, even if the screen is turned off (black display), since all cells are discharged, the luminance of black is increased and the contrast is decreased.

  Therefore, in the fifth embodiment, as shown in FIG. 22, the additional pulse P6 and the X electrode (X2) and the Y electrode (Y2) are not applied without applying the additional pulse P4 to the address electrode (A2). P5 is applied, and strong discharge is performed only between the X electrode and the Y electrode. Even in the case of the fifth embodiment, for example, although not as in the fourth embodiment, the effect of preventing the abnormal discharge by removing the charge accumulated on the address electrode side by the auxiliary discharge in the additional pulse period is can get.

  The driving methods (additional pulses) of the third to fifth embodiments of the present invention described above may be performed in all subfields. However, as described above, since the contrast is lowered, for example, 1 Even if it is performed only once in the field, it is effective.

  In the above description, the application of the present invention has been described mainly using the ALIS system PDP (particularly, display of odd lines) as an example, but the present invention is not limited to the ALIS system PDP, and discharge is performed. The present invention can also be widely applied to PDPs in which the cell pitch is short and charge transfer is likely to occur between adjacent cells (for example, vertically adjacent).

  FIG. 23 is a diagram showing another example of a driving waveform in a conventional PDP driving method, and shows a conventional example corresponding to an example described later with reference to FIG.

  A characteristic point in the conventional example shown in FIG. 23 is the reset pulse shape. In other words, a pulse having a gentle slope is applied as a reset pulse, write discharge is performed over all cells, and then an erase pulse having a gentle slope is applied to erase wall charges. This feature is because the pulse intensity is gentle and the discharge intensity is very low and the amount of light emitted is small. Therefore, even if reset (write / erase) discharge is performed in all subfields in all cells, the luminance is As a result, the dark room contrast is not lowered, and as a result, stable operation and high display quality can be obtained. The details of this driving technique are disclosed in, for example, Japanese Patent Application Laid-Open No. 10-170825.

  However, since the erasing waveform has a gentle slope, the scale of the discharge becomes small, so that there is a problem that the erasing of the wall charges is insufficient throughout the cell. That is, even if the X electrode (X), the Y electrode (Y), and the phosphor portion directly above the address electrode (A) can be sufficiently erased, the phosphor portion on the side surface of the barrier (partition wall) And the like cannot be sufficiently erased even when wall charges are attached, and as a result, there is a problem in that the discharge is started only by the erase pulse even if the address pulse is not applied in the address period.

  FIG. 24 is a diagram showing drive waveforms in the sixth embodiment of the PDP drive method according to the present invention.

  In the sixth embodiment, as shown in FIG. 24, an additional pulse P7 having the same voltage as the scan pulse (for example, about −150 V) is applied for a short period of several microseconds at the end of the erase pulse. As a result, a large-scale discharge is generated to neutralize wall charges, and misaddressing can be avoided.

  Specifically, for example, the voltage change amount of the additional pulse P7 applied steeply at the end of the erase pulse is about 5 to 10 V, for example, and the time for applying the additional pulse P7 is, for example, 1 to The effect was confirmed even at about 5 μs.

  The condition of the additional pulse P7 applied at the end of the above-described erase pulse varies depending on the cell structure, the method of applying a voltage in the address period and the sustain period, and can be changed variously accordingly.

  As described above, according to the sixth embodiment, the reset operation (erase discharge) is surely performed, so that the misaddress in which the discharge is started only by the erase pulse even if the address pulse is not applied in the address period. Can be prevented.

  FIG. 25 is a diagram showing drive waveforms in the seventh embodiment of the PDP drive method according to the present invention, and FIG. 26 is a diagram for explaining the operation of the PDP drive method shown in FIG.

  In the seventh embodiment, in order to suppress the applied voltage of the scan pulse from about −150 V to 100 V or less (for example, about −80 V), a high reset voltage (Vw) is applied to complete the reset discharge, that is, in the address period. This is an embodiment in which the wall charges superimposed on the address pulse and scan pulse remain before starting.

  FIG. 26A shows the state of wall charges at the end of the reset period. Positive wall charges remain on the X electrode (X1, X2, X3) side and the address electrode (A2) side, and the Y electrode (Y1 , Y2, Y3), negative wall charges remain. Therefore, address discharge can be performed at a voltage lower than that of the driving method described with reference to FIGS. 5 and 6 described above.

  Specifically, for example, the address pulse voltage is 50 V, the X electrode voltage is 130 V, the scan pulse voltage applied to the Y electrode is −80 V, and the applied voltage that is required to be 200 V or more between the address electrode and the Y electrode is It is designed to suppress to about 130V. FIG. 26B shows a state after the cells of the electrodes X1-Y1 and X3-Y3 have performed address discharge. If the cell of the electrode X2-Y2 is in the off state (address discharge is not performed), FIG. As shown in (b), the wall charges formed during the reset discharge remain as they are. If the sustain discharge is entered as it is, there is a case where a certain amount of wall charge exists even in the extinguished cell, so that the discharge may be started due to the seeding effect (priming effect) from the adjacent lighting cell.

  Therefore, in the seventh embodiment, as shown in FIG. 25, in the additional pulse period before entering the sustain discharge period, a pulse having the same voltage (for example, 50 V) as the address pulse is applied to the address electrode and the Y electrode A pulse having the same voltage as the scan pulse (for example, −80 V) is applied to discharge between the address electrode and the Y electrode, and the wall charge of the extinguished cell is erased as shown in FIG. This measure can prevent the extinguished cell from being lit during the sustain discharge period, as shown in FIG.

  Here, the additional pulse period may be, for example, a period of about 10 to 20 μs. In the additional pulse period in FIG. 25, since the voltage of the X electrode is set to 0 V, even if a discharge occurs between the address electrode and the Y electrode, the wall charge between the X electrode and the Y electrode becomes small. Furthermore, the voltage applied in the additional pulse period need not be the same as the voltage of the address pulse and the scan pulse as long as the above purpose can be achieved.

  FIG. 27 is a diagram showing drive waveforms in the eighth embodiment of the PDP drive method according to the present invention.

  In the seventh embodiment of FIG. 25 described above, the wall charge of the extinguished cell after the end of the address period is processed (reduced) by the discharge between the address electrode and the Y electrode. In the eighth embodiment, the X electrode and the Y electrode are processed. It is designed to be processed by electric discharge.

  That is, as shown in FIG. 27, in the eighth embodiment, in the additional pulse period between the address period and the sustain discharge period, a voltage (for example, higher than the applied voltage of the X electrode in the address period with respect to the X electrode) Apply the same voltage as the sustain discharge pulse (150V), and apply a pulse with the same voltage as the scan pulse (eg, -80V) and a gentle slope (eg, a pulse with a slope of -1V / μsec.) To the Y electrode. To do.

  This weak discharge by applying a pulse with a gentle slope eliminates the wall charge between the X electrode and the Y electrode electrode of the extinguished cell and prevents the light from being turned on accidentally during the sustain discharge period. Here, the additional pulse period is, for example, a period of about 80 to 90 μs. Also, in the eighth embodiment, similarly to the seventh embodiment described above, the voltage applied in the additional pulse period is the same as the sustain discharge pulse and scan pulse voltages as long as the above purpose can be achieved. Not necessary.

  FIG. 28 is a diagram showing drive waveforms in the ninth embodiment of the PDP drive method according to the present invention.

  As apparent from the comparison between FIGS. 25 and 27 and FIG. 28, in the ninth embodiment, an additional pulse period is newly provided and the wall charge of the extinguished cell is not erased by a dedicated pulse but maintained. The wall charge of the extinguished cell is extinguished while performing the sustain discharge during the discharge period. In the ninth embodiment (FIG. 28), the voltage required for the sustain discharge pulse is alternately applied by 1/2 from the X electrode and the Y electrode, that is, for example, 0 V with respect to the X electrode and the Y electrode. In this example, driving is performed by applying 80 V and -80 V instead of applying 160 V and 160 V. Also in the ninth embodiment, as in the seventh and eighth embodiments described above, reset processing is performed to leave wall charges for reducing the applied voltage required for address discharge.

  In FIG. 28, in periods T1 and T2, discharge is performed by applying positive and negative ½ voltages (−80 V and 80 V) between the electrodes X1 and Y1. Next, in the period T3, the cell between the electrodes X2 and Y2 performs a sustain discharge. At that time, the voltage of the electrode X1 is V1 lower than + 1/2 · Vs (for example, 50 to 50 V lower by about 20 to 30 V than 80 V). 60V). Similarly, the voltage is low in the periods T4, T5, and T7.

  The basic idea of the ninth embodiment is that the discharge timings of the cell of the electrode X1-Y1 and the cell of the electrode X2-Y2 are separated in the initial stage (pretreatment period) of the sustain discharge period, and both are turned on. In this case, when one is discharging, the other voltage is reduced to make it less susceptible to influence. If one cell is lit and the other cell is lit, a part of the other lit cell is discharged when one lit cell is discharged, and the lit cell is lit after that. It is to create a state that does not occur.

  The above situation will be described along the time axis of FIG. First, in the period T1 and the period T2, the cell between the electrodes X1 and Y1 is discharged, but the cell between the electrodes X2 and Y2 is in a standby state without being discharged even if it is a lit cell. At this time, since the discharge immediately after the address discharge is small-scale and does not diffuse to the adjacent cells, it is not necessary to create an escape voltage on the electrodes X2 and Y2.

  In the period T3, the cell between the electrodes X2 and Y2 starts a sustain discharge. At this time, when the cell between the electrodes X1 and Y1 is an extinguished cell, the positive polarity formed at the time of reset is formed on the X electrode side. There are wall charges. Therefore, when the voltage of the electrode X1 is high, the electrode Y2 and the electrode X1 adjacent to the electrode X2 appear to be large anodes, the electrode X1 is also involved and discharged, and a large amount of negative charges (electrons) are also applied to the electrode X1. The sustain discharge is caused by the subsequent sustain discharge pulse. In FIG. 28, only four XY electrodes are illustrated, but an electrode X3 that moves in the same manner as the electrode X1 exists below the electrode Y2.

  For this reason, in the ninth embodiment, the voltage of the electrode X1 is set low (V1: for example, 50 to 60 V), so that no large-scale discharge involving the electrode X1 occurs. Rather, the positive negative wall charges on the electrode X1 are annihilated by the arrival of moderate negative charges (electrons).

  Next, in the period T4, the cell between the electrodes X1 and Y1 performs the third sustain discharge. At that time, the voltage of the electrode X2 is lowered in the plus direction (V3: for example, −50 to −60 V) to avoid discharge between the electrodes Y1 and X2.

  In the period T5, the voltage of the electrode Y1 is lowered, and in the period T7, the voltage of the electrode Y2 is lowered (V2, V4: for example, 50 to 60 V). This is because when the cell of the electrode Y1 or Y2 is an extinguished cell, there is a negative wall charge formed on the Y electrode in the reset period, so that it is erased. Specifically, when the cell between the electrodes X1 and Y1 is in the extinguished state for the period T5 and the negative wall charge formed in the reset period exists on the electrode Y1, the voltage of the electrode Y1 is decreased in the negative direction ( V2), a weak discharge is generated between the electrodes X2 and Y1. At this time, a weak positive wall charge is formed on the electrode Y1 side, but the value is such that the subsequent discharge does not start. Note that the same applies to the operation in the period T7.

  As described above, in the ninth embodiment, the voltages V1 to V4 use appropriate output voltages generated by the power supply circuit. However, these voltages V1 to V4 are not outputs of the dedicated voltage generation circuit, and are shown in FIG. It is also possible to use a voltage obtained by putting the output circuit as shown in a high impedance state.

  FIG. 29 is a diagram showing a configuration example of the voltage generation circuit in the method for driving the PDP shown in FIG. 28, and pays attention to the voltage V1 in the period T3 in FIG.

  First, in the period T2 in FIG. 28, the switches SW1 and SW4 are turned on, the switches SW2 and SW3 are turned off, the voltage Vs is applied to the electrode X1, and −Vs is applied to the electrode Y1, so that between the electrodes X1 and Y1 A second sustain discharge is performed on the cell. Thereafter, in a period T2 in FIG. 28, the switch SW1 is turned off and the output circuit on the electrode X1 side is set in a high impedance state. Here, the cell between the electrodes X1 and Y1 has a capacitance Cp, the switches SW1 and SW2 also have the capacitances C1 and C2, and the capacitance C5 is also conceivable between the electrode X1 and the ground (GND). . Due to these capacitances Cp, C1, C2, and C3, the voltage (V1) of the electrode X1 becomes a voltage that is lower (by about 20 to 30 V) by a predetermined voltage than the voltage Vs (for example, 80 V). The same applies to the other voltages V2 to V4. That is, the voltages V2 and V4 are set to about 50 to 60 V, for example, and the voltage V3 is set to about -50 to -60 V, for example.

  That is, an appropriate voltage (about 50 to 60 V) can be applied to the electrode X1 as the voltage V1 without providing a dedicated power supply circuit for outputting the voltage V1 applied to the electrode X1. Since the sizes of the capacitors Cp, C1, C2, and C5 differ depending on the configuration of the panel, for example, an appropriate voltage V1 is applied to the electrode X1 by adjusting the size of the capacitor C5 as necessary. It becomes possible to do.

  In this way, by setting the output circuit in a high impedance state, if a large amount of current flows through the high impedance electrode, the voltage fluctuates in the direction of suppressing the discharge, so that the effect of suppressing the discharge growth is obtained. Will be.

  FIG. 30 is a diagram showing drive waveforms in the tenth embodiment of the PDP drive method according to the present invention. FIG. 30 also shows a further form of the present invention.

  First, in the tenth embodiment of the PDP driving method, the wall charges of the cells that have not been subjected to the address discharge at the end of the first half address period are erased. Specifically, for example, the address electrode is fixed at 0 V, and a pulse (V6: for example, the voltage is set to −100 V) having a voltage or pulse width larger than the Y scan pulse is applied to the Y electrode. Since the pulse V6 has a pulse width or voltage larger than that of the scan pulse, discharge is started even in a cell in which address discharge has not been performed. At that time, since the voltage of the X electrode is substantially the same value as the scan pulse, a large amount of wall charge between the X electrode and the Y electrode is not formed, and the light is not turned on thereafter.

  Here, the pulse (V6) applied in the intermediate processing period between the first half address period and the second half address period can be applied for each subfield, but for each predetermined number of subfields (for example, for each field). You may comprise so that it may apply.

  Next, as a further form of the present invention, in the second half address period, the voltage of the electrode Y1 that has performed the first half address is set lower than 0V (V5: for example, −20V). That is, there is positive wall charge on the Y electrode of the cell that has performed address discharge in the first half, and the voltage is lowered so that this positive wall charge does not disappear due to the discharge of the adjacent cell in the second half address period. ing. However, if the voltage V5 is lowered too much, there is a possibility of starting discharge with the address pulse, so it is important not to reduce it too much.

(Supplementary Note 1) A driving method of a plasma display panel in which a plurality of first electrodes and second electrodes are alternately arranged adjacent to each other, and a third electrode is formed so as to cross the first and second electrodes. And
A sustain discharge after performing an address discharge between the second electrode and the third electrode, and before performing a sustain discharge by alternately applying a sustain pulse to the first and second electrodes. A method for driving a plasma display panel, comprising: performing auxiliary discharge for reducing wall charges accumulated in display cells not intended to be sustained to an amount that does not cause sustain discharge.

(Supplementary Note 2) In the method for driving a plasma display panel according to Supplementary Note 1, in addition,
A discharge is caused in the selected cell by applying a voltage pulse with the third electrode side as the first polarity and the second electrode side as the second polarity,
The first electrode side has a first polarity with respect to the second electrode, at least the second electrode forms a wall charge of the first polarity, and the first electrode side Performing an address discharge to form a wall charge of the second polarity;
By applying a voltage pulse to the first electrode or the third electrode or both of them so that the third electrode side has the first polarity and the first electrode side has the second polarity. A method of driving a plasma display panel, wherein discharge is caused in a discharge cell that has started discharge without applying a voltage pulse that causes address discharge to the third electrode.

  (Supplementary note 3) In the plasma display panel driving method according to supplementary note 1, the voltage applied to the third electrode when the auxiliary discharge is performed is equivalent to an address pulse for performing the address discharge. A plasma display panel driving method characterized by the above.

  (Supplementary note 4) In the plasma display panel driving method according to supplementary note 1, a voltage applied to the second electrode when the auxiliary discharge is performed is set to a voltage of an additional pulse applied to the first electrode. A method for driving a plasma display panel, wherein the voltage is such that the potential difference between the electrodes is small.

  (Supplementary Note 5) In the method for driving a plasma display panel according to supplementary note 4, a voltage applied to the second electrode when the auxiliary discharge is performed is a voltage of the second electrode that is not selected in an address period. A method for driving a plasma display panel, which is equivalent.

(Supplementary Note 6) A method of driving a plasma display panel in which a plurality of first electrodes and second electrodes are alternately arranged adjacent to each other, and a third electrode is formed so as to cross the first and second electrodes. And
Performing an address discharge between the second electrode and the third electrode;
Driving a plasma display panel, wherein a sustain pulse is alternately applied to the first and second electrodes to perform a sustain discharge, and then an auxiliary discharge having a magnitude larger than the sustain discharge performed immediately before is performed. Method.

(Supplementary note 7) In the plasma display panel driving method according to supplementary note 6, further,
A discharge is caused in the selected cell by applying a voltage pulse with the third electrode side as the first polarity and the second electrode side as the second polarity,
The first electrode side has a first polarity with respect to the second electrode, at least the second electrode forms a wall charge of the first polarity, and the first electrode side Forming a wall charge of the second polarity,
Applying a voltage pulse to the third electrode or the second electrode or both of them so that the third electrode side has the first polarity and the second electrode side has the second polarity. A plasma display panel driving method characterized by the above.

  (Supplementary note 8) In the plasma display panel driving method according to supplementary note 6, when the auxiliary discharge is performed, the voltage applied to the third electrode is the third voltage for performing the address discharge in the address period. A method for driving a plasma display panel, characterized by being equivalent to a voltage pulse applied to an electrode.

  (Supplementary note 9) In the method for driving a plasma display panel according to supplementary note 6, when the auxiliary discharge is performed, the voltage applied to the third electrode is a potential of the second and third electrodes in the sustain discharge period. A plasma display panel driving method characterized by having a polarity opposite to that of the plasma display panel.

  (Supplementary Note 10) In the method for driving a plasma display panel according to supplementary note 6, a voltage applied to the second electrode when the auxiliary discharge is performed is selected for the second electrode when the address discharge is performed. A method for driving a plasma display panel, characterized in that the voltage is equivalent to an applied voltage.

  (Supplementary note 11) In the plasma display panel driving method according to supplementary note 6, the voltage applied to the first electrode when the auxiliary discharge is performed is a voltage having a polarity opposite to that of the second electrode. A method for driving a plasma display panel.

  (Supplementary Note 12) In the method for driving a plasma display panel according to supplementary note 11, the voltage applied to the first electrode when the auxiliary discharge is performed is applied to the first electrode when the address discharge is performed. A driving method of a plasma display panel, characterized by being equivalent to a voltage to be applied.

  (Supplementary note 13) The plasma display panel driving method according to supplementary note 6, wherein the auxiliary discharge is performed once for a plurality of subfields.

  (Supplementary note 14) The plasma display panel driving method according to supplementary note 13, wherein the auxiliary discharge is performed once in one frame or one field.

(Supplementary Note 15) The first electrode and the second electrode are alternately arranged adjacent to each other, a third electrode is formed so as to intersect the first electrode and the second electrode, and a scan pulse is applied. A plasma display panel driving method in which an erasing pulse having a gentle inclination with respect to two electrodes is applied at the time of resetting,
A method for driving a plasma display panel, characterized in that, at the final stage of the erasing pulse, the pulse voltage is changed abruptly until it reaches a voltage equivalent to the scan pulse.

  (Supplementary Note 16) In the method for driving a plasma display panel according to any one of supplementary notes 1, 6, and 15, the first electrodes and the second electrodes are alternately arranged in parallel, and The method for driving a plasma display panel, wherein the third electrode is orthogonal to the first and second electrodes.

(Supplementary Note 17) A plurality of first electrodes;
A plurality of second electrodes arranged alternately adjacent to each of the first electrodes;
A plurality of third electrodes arranged to intersect the first and second electrodes;
A control circuit for performing an address discharge between the second electrode and the third electrode;
The plasma display panel according to claim 1, wherein the control circuit performs auxiliary discharge for reducing wall charges accumulated in display cells not intended for sustain discharge to an amount that does not cause sustain discharge.

(Supplementary note 18) a plurality of first electrodes;
A plurality of second electrodes arranged alternately adjacent to each of the first electrodes;
A plurality of third electrodes arranged to intersect the first and second electrodes;
A control circuit for performing an address discharge between the second electrode and the third electrode;
The plasma display panel according to claim 1, wherein the control circuit causes an auxiliary discharge having a magnitude larger than the sustain discharge performed immediately before.

  (Supplementary note 19) In the plasma display panel according to any one of supplementary notes 17 and 18, the first electrode and the second electrode are alternately arranged in parallel, and the third electrode is A plasma display panel orthogonal to the first and second electrodes.

(Supplementary note 20) In the plasma display panel driving method according to supplementary note 1, in addition,
In a display cell in which a voltage pulse having the same polarity as the voltage pulse applied when performing address discharge is applied between the second electrode and the third electrode, and sustain discharge is not intended without performing address discharge. A method of driving a plasma display panel, wherein a further auxiliary discharge is performed to reduce wall charges.

(Supplementary note 21) In the plasma display panel driving method according to supplementary note 20,
The voltage between the first electrode and the second electrode has the same polarity as the voltage pulse applied when performing the address discharge between the first electrode and the second electrode, and the voltage between the first electrode and the second electrode is Finally, a voltage waveform that is equal to or higher than the voltage between the first electrode and the second electrode at the time of addressing is applied to reduce wall charges in a display cell that is not intended for sustain discharge without performing address discharge. A method for driving a plasma display panel, comprising performing further auxiliary discharge.

(Supplementary note 22) In the method for driving a plasma display panel according to supplementary note 21,
The method for driving a plasma display panel, wherein a voltage waveform applied between the first electrode and the second electrode for performing the further auxiliary discharge is a voltage waveform having a gentle slope.

(Supplementary note 23) In the plasma display panel driving method according to supplementary note 1, in addition,
The second electrode is driven in time divided into an odd electrode group and an even electrode group, and after the address period of either the odd electrode group or the even electrode group ends,
A wall in a display cell that has the same polarity as the voltage pulse applied when address discharge is performed on the second electrode and that is higher than the scan pulse voltage and does not intend to perform sustain discharge without performing address discharge. A method for driving a plasma display panel, comprising performing further auxiliary discharge for reducing electric charge.

(Supplementary Note 24) In the plasma display panel driving method according to supplementary note 23,
The voltage between the second electrode that performs the further auxiliary discharge and the first electrode that forms the display line is equal to the voltage applied to the second electrode that performs the auxiliary discharge. A method for driving a plasma display panel.

(Supplementary Note 25) A plasma display panel driving method in which a plurality of first electrodes and second electrodes are alternately arranged adjacent to each other, and a third electrode is formed so as to intersect the first and second electrodes. And
The second electrode is driven by being divided into an odd-numbered electrode group and an even-numbered electrode group in time, and in the latter half address period after the address period of either the odd-numbered electrode group or the even-numbered electrode group is ended.
A method for driving a plasma display panel, wherein the voltage of any one of the second electrodes that have finished address processing is made lower than the non-selection voltage of the second electrode during addressing.

(Supplementary Note 26) A driving method of a plasma display panel in which a plurality of first electrodes and second electrodes are alternately arranged adjacent to each other, and a third electrode is formed so as to cross the first and second electrodes. And
The first electrode and the second electrode are separated into an odd-numbered electrode group and an even-numbered electrode group, and a display cell is formed between the adjacent odd-numbered electrode groups and between the adjacent even-numbered electrode groups, or the adjacent electrodes A display cell is configured between the odd electrode group and the even electrode group, and
A plurality of initial discharges in the sustain discharge period are performed with time separation at each odd electrode or each even electrode,
A method for driving a plasma display panel, wherein one or both of the voltages of the first electrode and the second electrode on the side where the sustain discharge is not performed is set low.

(Supplementary note 27) In the driving method of the plasma display panel according to supplementary note 26,
A method for driving a plasma display panel, wherein an electrode that does not perform discharge is set to a low applied voltage to an electrode that does not perform discharge by setting a drive circuit for the electrode in a high impedance state.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

FIG. 2 is a diagram showing an ALIS plasma display panel (PDP) to which the present invention is applied in comparison with a conventional plasma display panel. It is a figure for demonstrating the display method of ALIS system PDP. It is a figure for demonstrating the principle of operation of PDP of an ALIS system. It is a figure which shows an example of the display sequence of PDP of an ALIS system. It is a figure which shows an example of the drive waveform of an ALIS system (the 1: odd field). It is a figure (example 2: even field) which shows an example of the drive waveform of an ALIS system. 1 is a block circuit diagram illustrating an example of an ALIS PDP to which the present invention is applied. It is a figure which shows an example of the panel structure in PDP of ALIS system. It is a figure which shows a mode that the fixed display is performed by one field (odd field). It is a figure which shows an example of the lighting sequence of the fixed display only by the one field shown in FIG. It is FIG. (1) for demonstrating the subject of the fixed display in ALIS system PDP. It is FIG. (2) for demonstrating the subject of the fixed display in PDP of an ALIS system. FIG. 11 is a diagram (part 3) for describing a problem of fixed display in an ALIS PDP. FIG. 6 is a diagram (part 4) for explaining a problem of fixed display in an ALIS PDP. FIG. 10 is a diagram (No. 5) for describing a problem of fixed display in an ALIS PDP. It is a figure which shows an example of the drive waveform in the drive method of the conventional PDP. It is a figure which shows the drive waveform in 1st Example of the drive method of the plasma display panel (PDP) based on this invention. FIG. 18 is a diagram for explaining the operation of the method for driving the PDP shown in FIG. 17. It is a figure which shows the drive waveform in 2nd Example of the drive method of PDP which concerns on this invention. It is a figure which shows the drive waveform in 3rd Example of the drive method of PDP which concerns on this invention. It is a figure which shows the drive waveform in 4th Example of the drive method of PDP which concerns on this invention. It is a figure which shows the drive waveform in 5th Example of the drive method of PDP which concerns on this invention. It is a figure which shows the other example of the drive waveform in the drive method of the conventional PDP. It is a figure which shows the drive waveform in 6th Example of the drive method of PDP which concerns on this invention. It is a figure which shows the drive waveform in 7th Example of the drive method of PDP which concerns on this invention. FIG. 26 is a diagram for explaining the operation of the PDP driving method shown in FIG. 25. It is a figure which shows the drive waveform in 8th Example of the drive method of PDP which concerns on this invention. It is a figure which shows the drive waveform in 9th Example of the drive method of PDP which concerns on this invention. FIG. 29 is a diagram illustrating a configuration example of a voltage generation circuit in the method for driving the PDP illustrated in FIG. 28. It is a figure which shows the drive waveform in 10th Example of the drive method of PDP which concerns on this invention.

Explanation of symbols

101 control circuit 104 address circuit (address driver)
105 Scanning circuit (scan driver)
106 Display panel (PDP)
121 Sustain circuit for odd X electrode (PX1)
122 Even X electrode sustain circuit (PX2)
131 Sustain circuit for odd-numbered Y electrodes (PY1)
132 Even Y electrode sustain circuit (PY2)
161 Front glass substrate 162 Rear glass substrate 165; 1651, 1652, 1653 Phosphor 1631, 1632, 1633 Transparent electrode 1641, 1642, 1643 Metal electrode 1650 Partition A1, A2, A3 Address electrode CLK Clock DATA Display data HSYNC Horizontal sync signal VSYNC Vertical synchronization signal X1, X2, X3, X4 X electrode Y1, Y2, Y3, Y4 Y electrode

Claims (11)

A driving method of a plasma display panel in which a plurality of first electrodes and second electrodes are alternately arranged adjacent to each other, and a third electrode is formed so as to intersect the first and second electrodes, Performing a reset discharge between one electrode and the second electrode;
Performing an address discharge between the second electrode and the third electrode;
After the sustain discharge is performed by alternately applying the sustain pulse to the first and second electrodes, and before the reset discharge in the next field, the scale is larger than the sustain discharge performed immediately before A method for driving a plasma display panel, comprising performing auxiliary discharge. 2. The method of driving a plasma display panel according to claim 1, further comprising applying a voltage pulse with the third electrode side as a first polarity and the second electrode side as a second polarity, and applying a voltage pulse. Causes a discharge,
The first electrode side has a first polarity with respect to the second electrode, at least the second electrode forms a wall charge of the first polarity, and the first electrode side Forming a wall charge of the second polarity,
Applying a voltage pulse to the third electrode or the second electrode or both of them so that the third electrode side has the first polarity and the second electrode side has the second polarity. A plasma display panel driving method characterized by the above.   2. The method of driving a plasma display panel according to claim 1, wherein a voltage applied to the third electrode when the auxiliary discharge is performed is applied to the third electrode in order to perform an address discharge in an address period. A plasma display panel driving method characterized by being equivalent to a voltage pulse.   2. The method of driving a plasma display panel according to claim 1, wherein a voltage applied to the third electrode when the auxiliary discharge is performed is opposite to a potential of the second and third electrodes during a sustain discharge period. A driving method of a plasma display panel characterized by being polar.   2. The method of driving a plasma display panel according to claim 1, wherein the voltage applied to the second electrode when the auxiliary discharge is performed is selectively applied to the second electrode when the address discharge is performed. A driving method of a plasma display panel, characterized by being equivalent to a voltage to be generated.   2. The method of driving a plasma display panel according to claim 1, wherein a voltage applied to the first electrode when the auxiliary discharge is performed is a voltage having a polarity opposite to that of the second electrode. To drive a plasma display panel.   7. The method of driving a plasma display panel according to claim 6, wherein a voltage applied to the first electrode when the auxiliary discharge is performed is a voltage applied to the first electrode when an address discharge is performed. A method for driving a plasma display panel, which is equivalent.   2. The method for driving a plasma display panel according to claim 1, wherein the auxiliary discharge is performed once for a plurality of subfields.   9. The method for driving a plasma display panel according to claim 8, wherein the auxiliary discharge is performed once in one frame or one field. A plurality of first electrodes and second electrodes are alternately arranged adjacent to each other, a third electrode is formed so as to intersect the first electrode and the second electrode, and a scan pulse is applied to the second electrode. On the other hand, a plasma display panel driving method for applying an erasing pulse having a gentle inclination at the time of resetting,
A method for driving a plasma display panel, characterized in that, at the final stage of the erasing pulse, the pulse voltage is changed abruptly until it reaches a voltage equivalent to the scan pulse. A plurality of first electrodes;
A plurality of second electrodes arranged alternately adjacent to each first electrode;
A plurality of third electrodes arranged to intersect the first and second electrodes;
A control circuit for performing a reset discharge between the first electrode and the second electrode and for performing an address discharge between the second electrode and the third electrode;
The control circuit was performed immediately after the sustain discharge was applied by alternately applying the sustain pulse to the first and second electrodes and before the reset discharge in the next field. A plasma display panel characterized in that an auxiliary discharge having a magnitude larger than a sustain discharge is performed.

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