JP2006253488A - Three-dimensional packaging module and its manufacturing method - Google Patents
Three-dimensional packaging module and its manufacturing method Download PDFInfo
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Abstract
Description
本発明は、半導体モジュールの実装構造およびその製造方法に関し、特に、三次元的に半導体チップを積み重ねる高密度なスタック型のモジュールにおいて、半導体チップの放熱性の良い構造およびその製造方法に関するものである。 The present invention relates to a semiconductor module mounting structure and a method for manufacturing the same, and more particularly, to a high-density stack type module in which semiconductor chips are stacked three-dimensionally and a structure for manufacturing the semiconductor chip with good heat dissipation. .
従来技術として、スタック型でないＩＣパッケージではその上面（冷却したいＩＣチップの上面）にヒートシンクを実装して放熱することが一般的であった。しかしながら、三次元実装したモジュールの場合、モジュールの下面あるいは中間に配置されるチップを冷却することは困難であり、様々な設計的な工夫や提案が行われている。例えば、消費電力が大きく発熱量の大きい半導体チップは、空気の対流による冷却効果を期待して最上面に配置したりする場合もあるが、全てこの方法で対応できるものでも無い。 As a conventional technique, in a non-stacked IC package, it is common to dissipate heat by mounting a heat sink on the upper surface (the upper surface of an IC chip to be cooled). However, in the case of a three-dimensionally mounted module, it is difficult to cool a chip disposed on the lower surface or in the middle of the module, and various design ideas and proposals have been made. For example, a semiconductor chip that consumes a large amount of power and generates a large amount of heat may be placed on the top surface in anticipation of a cooling effect due to air convection, but it is not all that can be handled by this method.
構造的な工夫の提案では、例えば、下記特許文献１がある。図８に示すように多段に積層された半導体チップ１０２の裏側に放熱板１０３をはりつけ、中間の半導体チップから発生する熱を放熱板を利用することで放熱効果を高めている。１０４はハンダボールである。このとき、放熱板１０３を長くすれば放熱効果をより向上させることができる。しかしながら、放熱構造を高めるために放熱板１０３を長くすることは、モジュールのサイズが大きくなるために、高密度に電子部品を行う妨げになってしまうと言う問題がある。 For example, there is the following Patent Document 1 as a proposal of a structural device. As shown in FIG. 8, a heat radiating plate 103 is attached to the back side of the multi-layered semiconductor chips 102, and the heat radiating effect is enhanced by using the heat radiating plate for heat generated from the intermediate semiconductor chip. Reference numeral 104 denotes a solder ball. At this time, if the heat radiating plate 103 is lengthened, the heat radiating effect can be further improved. However, increasing the length of the heat dissipation plate 103 in order to enhance the heat dissipation structure increases the size of the module, which hinders high density electronic components.
近年、電子機器の高機能化により高集積化と回路の動作周波数が加速度的に進歩しており、ますます発熱の問題が顕在化している。一方では、電子機器の小型化、薄型化の要求も強く、より高密度に実装することが求められており、半導体チップの温度上昇の問題が難しくなっている。 In recent years, with higher functionality of electronic devices, higher integration and operational frequency of circuits have been accelerated, and the problem of heat generation has become more and more obvious. On the other hand, there is a strong demand for miniaturization and thinning of electronic devices, and there is a demand for mounting with higher density, which makes it difficult to raise the temperature of semiconductor chips.
この発熱と小型化の課題を同時に改善するために、例えば、特許文献２は、キャリア基板に搭載される半導体チップから放出される熱をチップ外部へ伝達するための水平伝熱部、さらに放熱部に伝導するための垂直伝熱部に伝え、最終的に最上層および／または最下層のキャリア基板上に設けられる放熱部から放熱する構造を提案している。この方法では、放熱部が最上層のキャリア基板または最下層のキャリア基板に設けられるため、部品の横方向に対してはサイズがそれほど大きくならなく、部品実装密度の低下を防ぎつつ放熱性も高めることができると言うものであった。 In order to improve the problem of heat generation and miniaturization at the same time, for example, Patent Document 2 discloses a horizontal heat transfer unit for transferring heat released from a semiconductor chip mounted on a carrier substrate to the outside of the chip, and a heat dissipation unit. A structure has been proposed in which heat is transferred to a vertical heat transfer portion for conducting heat to the heat and finally radiated from a heat radiating portion provided on the uppermost layer and / or the lowermost carrier substrate. In this method, since the heat radiating portion is provided on the uppermost carrier substrate or the lowermost carrier substrate, the size is not so large in the lateral direction of the component, and the heat dissipation is improved while preventing the component mounting density from being lowered. It was something that could be done.
しかしながら、垂直方向の伝熱部をもつことは、垂直方向の伝熱部の分だけ横方向に対してサイズが大きくなってしまうと言う課題があった。さらに、熱を伝えるための専用部材を使用することで構造が複雑になり製造コストが高くなる欠点も有している。 However, having the vertical heat transfer section has a problem that the size of the vertical heat transfer section is increased in the lateral direction. Further, the use of a dedicated member for transferring heat has a drawback that the structure becomes complicated and the manufacturing cost increases.
また製造コストをおさえ、高密度に実装できる三次元実装モジュールを安価に作ることも重要な課題である。 It is also an important issue to reduce the manufacturing cost and to make a three-dimensional mounting module that can be mounted at high density at low cost.
この安価に製造すると言う課題に対しては、例えば特許文献３では、一例として図７に示すような構造と製造方法が記載されている。すなわち、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）型の半導体パッケージを複数段積層して構成した構造である。ＢＧＡ２０１は、半導体チップ２０５をキャリア基板２０３に実装した後、保護膜２０６で覆われた構造である。そして半導体チップ２０５が実装されるキヤリア基板の裏側にはハンダボール２０７が接合されている。同様にＢＧＡ２０２は、半導体チップ２０９をキャリア基板２０８に実装した後、保護膜２１０で覆われた構造であり、裏側にはハンダボール２１１が接合されている。ＢＧＡ２０１には接続パターン２０４が形成されており、ＢＧＡ２０２のハンダボール２１１がこの接続パターン２０４と、リフロー方式で接続されて三次元モジュールを形成する。 For example, Patent Document 3 describes a structure and a manufacturing method as shown in FIG. 7 as an example for the problem of manufacturing at low cost. That is, it is a structure in which a plurality of BGA (Ball Grid Array) type semiconductor packages are stacked. The BGA 201 has a structure in which a semiconductor chip 205 is mounted on a carrier substrate 203 and then covered with a protective film 206. A solder ball 207 is bonded to the back side of the carrier substrate on which the semiconductor chip 205 is mounted. Similarly, the BGA 202 has a structure in which a semiconductor chip 209 is mounted on a carrier substrate 208 and then covered with a protective film 210, and a solder ball 211 is bonded to the back side. A connection pattern 204 is formed on the BGA 201, and the solder balls 211 of the BGA 202 are connected to the connection pattern 204 by a reflow method to form a three-dimensional module.
このように一般的なリフロー方式で接合する方法で製造すれば安価に作ることができるが、半導体チップの発熱量が多い場合に発生する熱を放熱させて温度上昇を防ぐことは困難である。通常キャリア基板は熱伝導性の良い金属配線を含んでいるため空気よりは熱伝導性が良い物質である。したがって図７（Ｃ）の構造で半導体チップ２０５の上面とキャリア基板２０８の下面を密着させるか、熱伝導性の良い物質で接続すれば大幅な放熱効果が期待できる。
しかしながら、安価に製造するために一般的な製造方法であるリフロー方式を用いるためには、ハンダが熔融した状態の表面張力を利用して位置を正しい位置に修正するセルフアライメントの性質を利用するため、あらかじめ半導体チップとキャリア基板を接触固定して接合することができない。 However, in order to use the reflow method, which is a general manufacturing method for manufacturing at low cost, the property of self-alignment that corrects the position to the correct position using the surface tension in the state where the solder is melted is used. The semiconductor chip and the carrier substrate cannot be bonded and fixed in advance.
すなわち、リフローでハンダが熔融している状態の時にはＢＧＡ２０２は自由に動ける状態にしておく必要があり、あらかじめ熱伝導性の物質で接合しておくことはできなないため半導体チップとその上面のキャリア基板には隙間ができることになる。また、この隙間をキャリア基板通しを接合した後で熱伝導性の良い物質で充填したくても、ハンダボール２１１があるためうまく注入することができない構造となってしまっている。 That is, when the solder is melted by reflow, the BGA 202 needs to be able to move freely, and since it cannot be bonded in advance with a thermally conductive substance, the semiconductor chip and the carrier on the upper surface thereof There will be a gap in the substrate. Further, even if it is desired to fill this gap with a material having good thermal conductivity after joining the carrier substrate through, there is a structure in which the solder balls 211 cannot be injected well.
本発明は、以上の課題を解決して、安価な製造方法であるリフロー方式を採用して、かつチップから発生する熱を効率よくキャリア基板とマザー基板に伝えることができる三次元実装モジュールの構造およびその製造方法を提供することを目的とするものである。 The present invention solves the above-described problems, adopts a reflow method that is an inexpensive manufacturing method, and can efficiently transfer heat generated from a chip to a carrier substrate and a mother substrate. And an object of the present invention is to provide a manufacturing method thereof.
本発明は、上述の目的を達成するために以下の構成を備える。 The present invention has the following configuration in order to achieve the above-described object.
（１）半導体チップを実装したキャリア基板が、複数段積み重ねられた三次元実装モジュール形態であり、前記半導体チップの上面に金属膜を備え、前記キャリア基板には少なくとも１層のプレーン形状のグラウンドとなる金属膜を備え、この半導体チップの上面の金属膜とキャリア基板内のプレーン形状の金属膜とを直接に／またはプレーン形状の金属膜に接続しているランドとを、金属材料で接続した構造を備えることを特徴としている。 (1) A carrier substrate on which a semiconductor chip is mounted is a three-dimensional mounting module in which a plurality of stages are stacked, a metal film is provided on the upper surface of the semiconductor chip, and the carrier substrate has at least one plane-shaped ground. A structure in which a metal film on the upper surface of the semiconductor chip and a land in which the plane-shaped metal film in the carrier substrate is directly / or connected to the land in the plane-shaped metal film are connected with a metal material. It is characterized by having.
（２）半導体チップを実装したキャリア基板が、複数段積み重ねられた三次元実装構造を有するモジュールの製造方法において、前記半導体チップはその上面に金属膜を備え、前記キャリア基板には少なくとも１層のプレーン形状のグラウンドとなる金属膜を備え、この半導体チップが実装されたキャリア基板と、別のキャリア基板を接合する工程で、前記半導体チップ上面の金属膜とキャリア基板内のプレーン形状の金属膜とを直接に／またはプレーン形状の金属膜に接続しているランドとを、金属材料で同時に接合することを特徴とする。 (2) In a method for manufacturing a module having a three-dimensional mounting structure in which a plurality of carrier substrates on which semiconductor chips are mounted are stacked, the semiconductor chip comprises a metal film on the upper surface, and the carrier substrate has at least one layer. In the process of bonding a carrier substrate on which the semiconductor chip is mounted and a metal substrate serving as a plane-shaped ground to another carrier substrate, the metal film on the upper surface of the semiconductor chip and the plane-shaped metal film in the carrier substrate The land directly connected to the metal film having a plane shape is bonded simultaneously with a metal material.
（３）半導体チップを実装したキャリア基板が、複数段積み重ねられた三次元構造を有する実装モジュールの製造方法において、前記キャリア基板には少なくとも１層のプレーン形状のグラウンドとなる金属膜を備え、この半導体チップが実装されたキャリア基板と、別のキャリア基板を接合する工程で、前記半導体チップ上面とキャリア基板内のプレーン形状の金属膜とを直接に／またはプレーン形状の金属膜に接続しているランドとを、熱伝導性材料で同時に接合することを特徴とする。 (3) In the method of manufacturing a mounting module having a three-dimensional structure in which a carrier substrate on which a semiconductor chip is mounted is stacked in a plurality of stages, the carrier substrate is provided with a metal film serving as at least one plane of ground, In the process of bonding the carrier substrate on which the semiconductor chip is mounted and another carrier substrate, the upper surface of the semiconductor chip and the plain-shaped metal film in the carrier substrate are directly connected to the plain-shaped metal film. The land is simultaneously bonded with a heat conductive material.
本発明によれば、半導体チップが実装されたキャリア基板が、複数段積み重ねられた三次元実装構造を有するモジュールにおいて、従来、安価なリフロー方式で製造した場合キャリア基板の間に位置する半導体チップから発生する熱を伝熱する構造が取れなかったが、リフロー工程で同時に半導体チップとその上面に位置するキャリア基板のグラウンドパターンを熱伝導性の良い物質で接合することで、安価な方法で熱伝導性の良い三次元実装モジュールを形成することができた。 According to the present invention, in a module having a three-dimensional mounting structure in which a plurality of stacked semiconductor substrates are mounted on a semiconductor substrate, a conventional semiconductor chip positioned between carrier substrates when manufactured by an inexpensive reflow method. Although the structure to transfer the generated heat could not be obtained, the semiconductor chip and the carrier substrate ground pattern located on the upper surface of the semiconductor chip and the upper surface of the carrier board were joined together with a material with good thermal conductivity in the reflow process. A good three-dimensional mounting module could be formed.
さらに、熱伝導のために使用する部材の一部を電気的接続のために使用されているキャリア基板内のグラウンドプレーンやハンダボールと兼用させることで、モジュールのサイズを特別に大きくすることなく実現できた。 In addition, a part of the member used for heat conduction is also used as a ground plane and solder ball in the carrier board used for electrical connection, so that the module size is not increased specially. did it.
以下に、本発明の実施形態について図面を参照して説明する。 Embodiments of the present invention will be described below with reference to the drawings.
図１は側断面図であり、本発明の第１の実施例を示している。キャリア基板１にはフリップチップ実装方式で半導体チップ５が実装されている。半導体チップ５の上面には３５μｍ厚の銅箔３が熱伝導性耐熱接着剤で貼り付けられており、側面にはフリップチップ実装部を保護するためにアンダーフィル６が形成されている。また、キャリア基板１の下側にはハンダボール９が所定のランドに接合されている。 FIG. 1 is a side sectional view showing a first embodiment of the present invention. A semiconductor chip 5 is mounted on the carrier substrate 1 by a flip chip mounting method. A copper foil 3 having a thickness of 35 μm is attached to the upper surface of the semiconductor chip 5 with a heat conductive heat-resistant adhesive, and an underfill 6 is formed on the side surface to protect the flip chip mounting portion. A solder ball 9 is bonded to a predetermined land below the carrier substrate 1.
キャリア基板２には同様にフリップチップ実装方式で半導体チップ７が実装されており、その側面にはアンダーフィル８が形成されている。キャリア基板１とキャリア基板２はハンダボール１０で接合されており、電気的にも接続されている。 Similarly, a semiconductor chip 7 is mounted on the carrier substrate 2 by a flip chip mounting method, and an underfill 8 is formed on a side surface thereof. The carrier substrate 1 and the carrier substrate 2 are joined by solder balls 10 and are also electrically connected.
ハンダ部材４は、半導体チップ５の上面に形成された銅箔とキャリア基板２のグラウンドパターンを接続するためのものである。 The solder member 4 is for connecting the copper foil formed on the upper surface of the semiconductor chip 5 and the ground pattern of the carrier substrate 2.
図１で示される三次元実装モジュールはプリント配線板に実装されて使用されるが、その動作状態で発生する半導体チップ５の熱は、半導体チップ５の下面→キャリア基板１→ハンダボール９→プリント配線板（図では省略）のルートと、半導体チップ５の上面→銅箔３→ハンダ部材４→キャリア基板２のグラウンドパターン（図では省略）→グラウンドパターンに接続されているハンダボール１０→キャリア基板１→ハンダボール９→プリント配線板（図では省略）の二つのルートから伝熱するので半導体チップ５の温度上昇をおさえることができる。 The three-dimensional mounting module shown in FIG. 1 is used by being mounted on a printed wiring board. The heat of the semiconductor chip 5 generated in the operation state is from the lower surface of the semiconductor chip 5 → the carrier substrate 1 → the solder ball 9 → printed. Route of wiring board (not shown) and upper surface of semiconductor chip 5 → copper foil 3 → solder member 4 → ground pattern of carrier substrate 2 (not shown) → solder ball 10 connected to the ground pattern → carrier substrate Since heat is transferred from two routes of 1 → solder ball 9 → printed wiring board (not shown), the temperature rise of the semiconductor chip 5 can be suppressed.
図４は、図１で示した構造の三次元実装モジュールの製造方法について説明するためのものである。図４（ａ）はキャリア基板１の上面図であり、図４（ｂ）はキャリア基板２の下面を示す透視図である。図４（ａ）において、キャリア基板１の上面には半導体チップが実装され、そのチップの上面には銅箔３がはりつけられ側面にはアンダーフィル６が形成されている。１１はキャリア基板の上面に形成されたランドであり、ここにキャリア基板２の下面に形成されたハンダボール１０がリフローによって接合される。図４（ｂ）において、キャリア基板２の下面にはハンダボール１１があらかじめ接続されている。キャリア基板２の内層にはプレーン状のグラウンドが形成されておりランド１２とはスルーホール等の所定の方法で電気的な接続が取れており当然熱伝導性も良好な状態になっている。このランド１２の上にディスペンサーでクリームハンダ１３を供給し、ハンダボール１０とランド１１をリフローで接続すると同時に、ランド１２と銅箔３が接合される（図４（ｃ））。 FIG. 4 is for explaining a method of manufacturing the three-dimensional mounting module having the structure shown in FIG. FIG. 4A is a top view of the carrier substrate 1, and FIG. 4B is a perspective view showing the bottom surface of the carrier substrate 2. In FIG. 4A, a semiconductor chip is mounted on the upper surface of the carrier substrate 1, a copper foil 3 is attached to the upper surface of the chip, and an underfill 6 is formed on the side surface. Reference numeral 11 denotes a land formed on the upper surface of the carrier substrate, and a solder ball 10 formed on the lower surface of the carrier substrate 2 is bonded thereto by reflow. In FIG. 4B, a solder ball 11 is connected to the lower surface of the carrier substrate 2 in advance. A plain ground is formed on the inner layer of the carrier substrate 2 and is electrically connected to the land 12 by a predetermined method such as a through-hole, and naturally the thermal conductivity is also good. The cream solder 13 is supplied onto the land 12 with a dispenser, and the solder ball 10 and the land 11 are connected by reflow, and at the same time, the land 12 and the copper foil 3 are joined (FIG. 4C).
図５は第２の実施例を示すための図である。図１および図４で示した第１の実施例との違いを説明する。図５（ａ）はキャリア基板１の上面図であり、図５（ｂ）はキャリア基板２の下面を示す透視図、図５（ｃ）は側断面図である。 FIG. 5 is a diagram for illustrating the second embodiment. Differences from the first embodiment shown in FIGS. 1 and 4 will be described. 5A is a top view of the carrier substrate 1, FIG. 5B is a perspective view showing the bottom surface of the carrier substrate 2, and FIG. 5C is a side sectional view.
図５（ａ）は図４（ａ）と全く同じ構造である。 FIG. 5 (a) has the same structure as FIG. 4 (a).
図５（ｂ）において、キャリア基板２の下面にはハンダボール１０があらかじめ接続されている。キャリア基板２の内層にはプレーン状のグラウンドが形成されておりキャリア基板下面のグラウンドプレーン１４とはスルーホール等の所定の方法で電気的な接続が取れており当然熱伝導性も良好な状態になっている。このグラウンドプレーン１４はソルダーレジストで覆われているが、所定の部分１５では覆われていない構造となっている。このソルダーレジストで覆われていない部分１５の上にディスペンサーでクリームハンダ１３を供給し、ハンダボール１０とランド１１をリフローで接続すると同時に、ソルダーレジストで覆われていない部分１５と銅箔３を接合して製造したものである（図５（ｃ））。 In FIG. 5B, a solder ball 10 is connected to the lower surface of the carrier substrate 2 in advance. A plain ground is formed on the inner layer of the carrier substrate 2 and is electrically connected to the ground plane 14 on the lower surface of the carrier substrate by a predetermined method such as a through hole. It has become. The ground plane 14 is covered with a solder resist, but is not covered with a predetermined portion 15. The cream solder 13 is supplied by a dispenser onto the portion 15 not covered with the solder resist, and the solder ball 10 and the land 11 are connected by reflow, and at the same time, the portion 15 not covered with the solder resist and the copper foil 3 are joined. (Fig. 5 (c)).
図６は第３の実施例を示すための図である。図１および図４で示した第１の実施例との違いを説明する。図６（ａ）はキャリア基板１の上面図であり、図６（ｂ）はキャリア基板２の下面を示す透視図、図６（ｃ）は側断面図である。 FIG. 6 is a diagram for illustrating a third embodiment. Differences from the first embodiment shown in FIGS. 1 and 4 will be described. 6A is a top view of the carrier substrate 1, FIG. 6B is a perspective view showing the bottom surface of the carrier substrate 2, and FIG. 6C is a side sectional view.
図６（ａ）は図４（ａ）とほとんど同じ構造であるが半導体チップ５の上面には銅箔がないむき出しの状態である。さらにキャリア基板１には上面にもハンダボール１０があらかじめ接続している。 FIG. 6A has almost the same structure as FIG. 4A, but the upper surface of the semiconductor chip 5 is not exposed with copper foil. Further, a solder ball 10 is connected to the carrier substrate 1 on the upper surface in advance.
図６（ｂ）において、キャリア基板２の下面にはハンダボール１０と接続するためのランド１７が形成されている。キャリア基板２の内層にはプレーン状のグラウンドが形成されておりキャリア基板下面のグラウンドプレーン１４とはスルーホール等の所定の方法で電気的な接続が取れており当然熱伝導性も良好な状態になっている。このグラウンドプレーン１４はソルダーレジストで覆われているが、所定の部分１６では覆われていない構造となっている。前記半導体チップ５の上にディスペンサーで熱伝導性の接着剤１８を供給し、ハンダボール１０とランド１７をリフローで接続すると同時に、ソルダーレジストで覆われていない部分１６と半導体チップを接合して製造する（図６（ｃ））。この熱伝導性の接着剤は、初期には粘度が低く、リフローの加熱工程で徐々に硬化するように調整されている。 In FIG. 6B, lands 17 for connecting to the solder balls 10 are formed on the lower surface of the carrier substrate 2. A plain ground is formed on the inner layer of the carrier substrate 2 and is electrically connected to the ground plane 14 on the lower surface of the carrier substrate by a predetermined method such as a through hole. It has become. The ground plane 14 is covered with a solder resist, but is not covered with a predetermined portion 16. A heat conductive adhesive 18 is supplied onto the semiconductor chip 5 by a dispenser, and the solder ball 10 and the land 17 are connected by reflow, and at the same time, the portion 16 not covered with the solder resist and the semiconductor chip are joined. (FIG. 6C). This heat conductive adhesive has an initially low viscosity and is adjusted so as to be gradually cured in the reflow heating process.
図２は側断面図であり、本発明の第４の実施例を示している。キャリア基板が三段重ねになっている以外は、第一の実施例と同じである。 FIG. 2 is a side sectional view showing a fourth embodiment of the present invention. The carrier substrate is the same as the first embodiment except that the carrier substrate is stacked in three stages.
図３は側断面図であり、本発明の第５の実施例を示している。キャリア基板が三段重ねになっているのは第４の実施例と同じだが、一段しか本発明の構造をとっていない。このように一部に実施しても良い。 FIG. 3 is a side sectional view showing a fifth embodiment of the present invention. The carrier substrates are stacked in three stages, which is the same as in the fourth embodiment, but only one stage has the structure of the present invention. Thus, you may implement in part.
１、２、２１、２２、２３ キャリア基板
３ 銅箔
４ ハンダ部材
５、７ 半導体チップ
６、８ アンダーフィル
９、１０ ハンダボール
１１、１７ ハンダボール接続ランド
１２ ランド
１３ クリームハンダ
１４ グラウンドプレーン
１５、１６ ソルダーレジストで覆われていない部分
１０１ キャリア基板
１０２ 半導体チップ
１０３ 放熱板
１０４ ハンダボール
２０１、２０２ ボールグリッドアレイ型の半導体パッケージ（ＢＧＡ）
２０３、２０８ キャリア基板
２０４ 接続パターン
２０５、２０９ 半導体チップ
２０６、２１０ 保護膜
２０７、２１１ ハンダボール
1, 2, 21, 22, 23 Carrier substrate 3 Copper foil 4 Solder member 5, 7 Semiconductor chip 6, 8 Underfill 9, 10 Solder ball 11, 17 Solder ball connection land 12 Land 13 Cream solder 14 Ground plane 15, 16 Portion 101 not covered with solder resist Carrier substrate 102 Semiconductor chip 103 Heat sink 104 Solder balls 201, 202 Ball grid array type semiconductor package (BGA)
203, 208 Carrier substrate 204 Connection pattern 205, 209 Semiconductor chip 206, 210 Protective film 207, 211 Solder ball
Claims (4)
前記半導体チップの上面に金属膜を備え、前記キャリア基板には少なくとも１層のプレーン形状のグラウンドとなる金属膜を備え、この半導体チップの上面の金属膜とキャリア基板内のプレーン形状の金属膜とを直接に／またはプレーン形状の金属膜に接続しているランドとを、金属材料で接続した構造を備えたことを特徴とする三次元実装モジュール。 A carrier substrate on which a semiconductor chip is mounted is a three-dimensional mounting module having a three-dimensional structure in which a plurality of stages are stacked,
A metal film is provided on the upper surface of the semiconductor chip, and the carrier substrate is provided with a metal film serving as at least one layer of a plane-shaped ground. The metal film on the upper surface of the semiconductor chip and the plane-shaped metal film in the carrier substrate; A three-dimensional mounting module comprising a structure in which a land connected directly to a metal film having a plane shape is connected with a metal material.
前記半導体チップはその上面に金属膜を備え、前記キャリア基板には少なくとも１層のプレーン形状のグラウンドとなる金属膜を備え、この半導体チップが実装されたキャリア基板と、別の配線基板を接合する工程で、前記半導体チップ上面の金属膜とキャリア基板内のプレーン形状の金属膜とを直接に／またはプレーン形状の金属膜に接続しているランドとを、金属材料で同時に接合することを特徴とする三次元実装モジュールの製造方法。 A carrier substrate on which a semiconductor chip is mounted is a method for manufacturing a three-dimensional mounting module having a three-dimensional structure in which a plurality of stages are stacked,
The semiconductor chip is provided with a metal film on the upper surface thereof, and the carrier substrate is provided with a metal film serving as at least one plane of ground, and the carrier substrate on which the semiconductor chip is mounted and another wiring substrate are joined. In the step, the metal film on the upper surface of the semiconductor chip and the plain-shaped metal film in the carrier substrate are bonded together directly / or with a land connecting the plain-shaped metal film with a metal material. To manufacture a three-dimensional mounting module.
前記キャリア基板には少なくても１層のプレーン形状のグラウンドとなる金属膜が備えられ、この半導体チップが実装されたキャリア基板と、別のキャリア基板を接合する工程で、前記半導体チップ上面とキャリア基板内のプレーン形状の金属膜とを直接に／またはプレーン形状の金属膜に接続しているランドとを、熱伝導性材料で同時に接合することを特徴とする三次元実装モジュールの製造方法。 A carrier substrate on which a semiconductor chip is mounted is a method for manufacturing a three-dimensional mounting module having a three-dimensional structure in which a plurality of stages are stacked,
The carrier substrate is provided with at least one layer of a ground-shaped metal film as a ground, and in the step of joining the carrier substrate on which the semiconductor chip is mounted to another carrier substrate, the upper surface of the semiconductor chip and the carrier A method for manufacturing a three-dimensional mounting module, wherein a land that is directly connected to a plain-shaped metal film in a substrate and / or a land that is connected to the plain-shaped metal film is simultaneously bonded with a heat conductive material.
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