JP2007049154A - Chip embedded package structure and manufacturing method therefor - Google Patents

Chip embedded package structure and manufacturing method therefor Download PDF

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JP2007049154A
JP2007049154A JP2006215062A JP2006215062A JP2007049154A JP 2007049154 A JP2007049154 A JP 2007049154A JP 2006215062 A JP2006215062 A JP 2006215062A JP 2006215062 A JP2006215062 A JP 2006215062A JP 2007049154 A JP2007049154 A JP 2007049154A
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chip
support plate
circuit
semiconductor chip
package structure
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Shih-Ping Hsu
詩 濱 許
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Phoenix Precision Technology Corp
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a chip embedded package structure and a manufacturing method therefor. <P>SOLUTION: A support plate having at least one opening is prepared, a heat conduction block is formed at the opening of the support plate, a semiconductor chip is adhered to the heat conduction block, a dielectric layer and a circuit layer are sequentially formed on the support plate and semiconductor chip, and the circuit layer is electrically connected to the semiconductor chip, thus forming the chip embedded package structure. A heat dissipation layer is formed by providing the support plate with the heat conduction block. A combination of the support plate, heat conduction block and dielectric layer enables the avoidance of the warpage occurring in the subsequent manufacturing process, and the enhancement of the package structure quality. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、チップ埋め込み型パッケージ構造およびその製造方法に関し、特に半導体チップを埋め込んで外部へ直接電気的に接続させるパッケージ構造およびその製造方法に関するものである。   The present invention relates to a chip embedded package structure and a manufacturing method thereof, and more particularly to a package structure in which a semiconductor chip is embedded and directly electrically connected to the outside and a manufacturing method thereof.

半導体パッケージ技術の発展にしたがって、半導体装置（Ｓｅｍｉｃｏｎｄｕｃｔｏｒ
ｄｅｖｉｃｅ）では様々なパッケージ形態が開発されている。例えば、先端の半導体パッケージ技術としてボールグリッドアレイ（Ｂａｌｌ ｇｒｉｄ ａｒｒａｙ，ＢＧＡ）が知られ、その特徴としては、半導体チップを基板に載せ、該基板の裏面に格子状に配列された複数の半田ボール（Ｓｏｌｄｅｒ ｂａｌｌ）をセルフアラインメント（Ｓｅｌｆ−ａｌｉｇｎｍｅｎｔ）技術により配置することにより、同一の単位面積である半導体チップキャリアに入力／出力端子（Ｉ／Ｏ Ｃｏｎｎｅｃｔｉｏｎ）がより多く収容され、高度集積化（Ｉｎｔｅｇｒａｔｉｏｎ）の半導体チップの需要に応え、これらの半田ボールによりパッケージユニットの全体が半田付けされ、外部の印刷回路板に電気的に接続されるようになっている。 With the development of semiconductor packaging technology, semiconductor devices (Semiconductor)
In the device), various package forms have been developed. For example, a ball grid array (BGA) is known as a leading-edge semiconductor packaging technology, and is characterized in that a plurality of solder balls (with a semiconductor chip mounted on a substrate and arranged in a grid pattern on the back surface of the substrate) By arranging Solder ball by self-alignment technology, more input / output terminals (I / O Connections) are accommodated in a semiconductor chip carrier having the same unit area, and highly integrated (Integration). In response to the demand for semiconductor chips, the entire package unit is soldered by these solder balls and electrically connected to an external printed circuit board.

１９６０年初期にＩＢＭが採用したフリップチップパッケージ（Ｆｌｉｐ Ｃｈｉｐ Ｐａｃｋａｇｅ）技術は、ワイヤボンディング（Ｗｉｒｅ ｂｏｎｄｉｎｇ）技術と比較して、半導体チップと基板とが一般の金線ではなく半田バンプによって電気的に接続されていることを特徴としている。このフリップチップ技術には、パッケージの密度を向上し、パッケージ素子のサイズを抑えることができる利点があり、また、長さの比較的長い金属リードを使用する必要がないため、電気的性能が向上し、高密度、高速度の半導体装置の需要に応えることが可能となっている。   The flip chip package technology adopted by IBM in the early 1960's is electrically connected to the semiconductor chip and the substrate by solder bumps rather than a general gold wire, as compared to wire bonding technology. It is characterized by being. This flip chip technology has the advantage of increasing the density of the package and reducing the size of the package element, and also improves electrical performance by eliminating the need for relatively long metal leads. However, it is possible to meet the demand for high-density, high-speed semiconductor devices.

現行のフリップチップ技術では、半導体チップの表面に電極パッド（Ｅｌｅｃｔｒｏｄｅ ｐａｄｓ）が配置され、チップが搭載された回路板にもそれに対応する接触パッドが設けられ、該チップと回路板との間に半田バンプまたはその他の導電性接着材料が適宜配置されることにより、該チップがフェースダウンで該回路板に載置される。ここで、該半田バンプまたは導電性接着材料は該チップと回路板との電気的入力／出力（Ｉ／Ｏ）および機械的接続として用いられる。   In the current flip chip technology, electrode pads (Electrode pads) are arranged on the surface of a semiconductor chip, and a corresponding contact pad is provided on a circuit board on which the chip is mounted, and solder is provided between the chip and the circuit board. By suitably arranging bumps or other conductive adhesive materials, the chip is placed face down on the circuit board. Here, the solder bump or conductive adhesive material is used as an electrical input / output (I / O) and mechanical connection between the chip and the circuit board.

図１は、従来のフリップチップ型半導体素子を示す。該図１に示すように、チップ１１の電極パッド１１０に金属バンプ１２が形成され、回路板１３の接触パッド１３０に半田材料によって作成されたプリ半田バンプ１５が形成されることにより、プリ半田バンプ１５がそれに対応する金属バンプ１２にリフローされ半田付けが形成される。さらに、該チップ１１と該回路板１３との間隙に有機アンダーフィル（ｕｎｄｅｒｆｉｌｌ）１４が充填されることにより、該チップ１１と該回路板１３との間の熱膨張差が抑制され、該半田付け部分への応力が緩和される。   FIG. 1 shows a conventional flip chip type semiconductor device. As shown in FIG. 1, metal bumps 12 are formed on the electrode pads 110 of the chip 11, and pre-solder bumps 15 made of a solder material are formed on the contact pads 130 of the circuit board 13. 15 is reflowed to the corresponding metal bumps 12 to form soldering. Further, the gap between the chip 11 and the circuit board 13 is filled with an organic underfill 14, so that a difference in thermal expansion between the chip 11 and the circuit board 13 is suppressed, and the soldering is performed. The stress on the part is relieved.

ただし、上記の従来のフリップチップパッケージ技術は、バンプ工程、リフロー工程および樹脂充填工程を経て初めて該半導体チップと該回路板との電気的接続が完了するため、製造工程の手順やコストが増加するのみならず、製造工程での信頼性のリスクもそれにしたがって増大する。また、製造工程において、半田材料の使用して該半導体チップと該回路板とが電気的に接続されるための半田付け構造を形成しなければならないため、環境保護が課題となり、しかも該半田材料が高温のリフロー工程を経た後、形成された半田付け構造の品質の信頼性の低下を招き、ひいては最終製品の電気的接続の品質が低下するこ
とがあった。 However, in the above conventional flip chip packaging technology, the electrical connection between the semiconductor chip and the circuit board is completed only after the bump process, the reflow process, and the resin filling process, so that the procedure and cost of the manufacturing process increase. Not only that, the risk of reliability in the manufacturing process increases accordingly. In addition, since a soldering structure for electrically connecting the semiconductor chip and the circuit board must be formed using a solder material in the manufacturing process, environmental protection becomes a problem, and the solder material However, after a high temperature reflow process, the reliability of the quality of the formed soldering structure is lowered, and the quality of electrical connection of the final product may be lowered.

また、従来のパッケージ技術では、半導体素子を１つずつ回路板の頂面に接着し、さらにワイヤボンディング（ｗｉｒｅ ｂｏｎｄｉｎｇ）またはフリップチップ（ｆｌｉｐ ｃｈｉｐ）接合パッケージを行うとともに、基板の裏面に半田ボールを搭載する。このように多ピン数化の目的は達成することができるが、しかし、半導体素子の面積や体積の制限により回路板の表面における配線の困難度が増加し、それらの半導体素子が全て回路板の表面に配置されているため、半導体素子のパッケージ構造のサイズの縮小や性能の向上を妨げることがあった。   In the conventional packaging technology, semiconductor elements are bonded to the top surface of the circuit board one by one, and wire bonding or flip chip bonding package is performed, and solder balls are attached to the back surface of the substrate. Mount. Although the purpose of increasing the number of pins can be achieved in this way, however, the difficulty of wiring on the surface of the circuit board increases due to restrictions on the area and volume of the semiconductor element, and all these semiconductor elements are included in the circuit board. Since it is disposed on the surface, it may prevent the reduction of the size of the package structure of the semiconductor element and the improvement of the performance.

さらに、半導体素子の製造工程としては、一般に、まず、チップキャリア製造業者が基板やリードフレームなどの半導体素子に適用されるチップキャリアを生産し、その後、それらのチップキャリアに半導体パッケージメーカーがチップ実装、モールドプレスおよび半田ボールマウンティングなどの製造工程を行うことで、最終的にクライアントが必要とする電子機能を具えた半導体素子が完成する。この製造工程においては異なる製造業者（即ちチップキャリア製造業者および半導体パッケージメーカーを含む）が関わっているため、実際の製造工程において手順が煩雑となるのみならず、インタフェースの統合が容易ではなく、幅広い需要や経済的な効果と利益に対する要求に応えることが難しい。   Furthermore, as a manufacturing process of semiconductor elements, generally, a chip carrier manufacturer first produces chip carriers that are applied to semiconductor elements such as substrates and lead frames, and then a semiconductor package manufacturer mounts chips on those chip carriers. By performing manufacturing processes such as mold pressing and solder ball mounting, a semiconductor element having an electronic function required by the client is finally completed. Since this manufacturing process involves different manufacturers (that is, including chip carrier manufacturers and semiconductor package manufacturers), not only is the procedure complicated in the actual manufacturing process, but interface integration is not easy, and a wide range Difficult to meet demands, demands for economic effects and profits.

さらにまた、電子産業のめざましい発展に伴い、電子製品の研究開発も多機能、高性能を目指すようになりつつある。半導体パッケージ構造の高集積化（ｉｎｔｅｇｒａｔｉｏｎ）および微細化（ｍｉｎｉａｔｕｒｉｚａｔｉｏｎ）のパッケージ需要を満たすためには、半導体チップの動作時に生じた熱量が著しく増加した場合に、半導体チップによる熱量を速やかに効率よく放散できなければならず、さもなければ半導体チップの性能や寿命が大幅に後退することとなる。   In addition, with the remarkable development of the electronics industry, research and development of electronic products are also aiming for multi-function and high performance. In order to meet the package demand for integration and miniaturization of the semiconductor package structure, when the amount of heat generated during the operation of the semiconductor chip is significantly increased, the amount of heat generated by the semiconductor chip is quickly and efficiently dissipated. It must be possible, otherwise the performance and life of the semiconductor chip will be significantly reduced.

このため、半導体チップを基板に埋め込む方法が考えられた。例えば図２に示すように、この方法を採用したアメリカ特許第６，８４１，４１３号（特許文献１）が知られている。   For this reason, a method of embedding a semiconductor chip in the substrate has been considered. For example, as shown in FIG. 2, US Pat. No. 6,841,413 (Patent Document 1) employing this method is known.

図２は特許文献２に開示された発明の断面を模式的に示す図である。
ここでは、放熱板２１（ｈｅａｔ ｓｐｒｅａｄｅｒ）に半導体チップ２２（ｓｅｍｉｃｏｎｄｕｃｔｏｒ ｄｉｅ）を接着し、該半導体チップ２２のアクティブ面に電極パッド２２１（ｅｌｅｃｔｒｉｃａｌ ｃｏｎｎｅｃｔｅｄ）が設けられ、該放熱板２１の上表面および半導体チップ２２のアクティブ面に誘電層２３（ｄｉｅｌｅｃｔｒｉｃ ｌａｙｅｒ）が形成され、該誘電層２３にパターニング工程により貫通孔２３０が形成されることで半導体チップ２２の電極パッド２２１が露出され、該誘電層２３の表面および貫通孔２３０に回路層２４（ｃｏｎｄｕｃｔｉｖｅ ｔｒａｃｅ）が形成され、さらに該誘電層２３および回路層２４の表面に他の誘電層２５が形成され、且つ該誘電層２５にパターニング工程により貫通孔２５０が形成されることで回路層２４の接続パッドの一部が露出され、その後さらに該誘電層２５の表面およびその貫通孔２５０に他の回路層２６が形成され、該誘電層２５および回路層２６の表面に絶縁保護層２７（ｓｏｌｄｅｒ ｍａｓｋ
ｍａｔｅｒｉａｌ）が形成され、且つ該絶縁保護層２７にパターニング工程により貫通孔２７０が形成されることで該回路層２６の電気接続パッド２６１が露出され、最後に該露出された電気接続パッド２６１の表面に例えば半田ボールといった導電素子２８が形成される。 FIG. 2 is a diagram schematically showing a cross section of the invention disclosed in Patent Document 2. As shown in FIG.
Here, a semiconductor chip 22 (semiconductor die) is bonded to the heat sink 21 (heat spreader), and an electrode pad 221 (electrically connected) is provided on the active surface of the semiconductor chip 22, and the upper surface of the heat sink 21 and the semiconductor A dielectric layer 23 is formed on the active surface of the chip 22, and through holes 230 are formed in the dielectric layer 23 by a patterning process, so that the electrode pads 221 of the semiconductor chip 22 are exposed. A circuit layer 24 (conductive trace) is formed on the surface and the through-hole 230, and another dielectric layer 25 is formed on the surface of the dielectric layer 23 and the circuit layer 24. The through-hole 250 is formed in the dielectric layer 25 by a patterning process. Formed As a result, a part of the connection pad of the circuit layer 24 is exposed, and then another circuit layer 26 is further formed on the surface of the dielectric layer 25 and its through hole 250, and on the surfaces of the dielectric layer 25 and the circuit layer 26. Insulating protective layer 27 (solder mask)
material) and through holes 270 are formed in the insulating protective layer 27 by a patterning process, so that the electrical connection pads 261 of the circuit layer 26 are exposed, and finally the exposed surface of the electrical connection pads 261 In addition, a conductive element 28 such as a solder ball is formed.

半導体チップ２２が放熱板２１の表面に接着されることで、該半導体チップ２２は放熱板２１により直接放熱され、これにより、上記の従来技術の欠点を解決することができる。ただし、放熱板２１、誘電層２３の熱膨張係数（Ｃｏｅｆｆｉｃｉｅｎｔ ｏｆ Ｔｈ
ｅｒｍａｌ Ｅｘｐａｎｓｉｏｎ， ＣＴＥ）の差異が大きいため、このようなパッケージ構造では製造工程における温度変化において、例えばベーキング（ｂａｋｉｎｇ）、後続の温度サイクル（ｔｈｅｒｍａｌ ｃｙｃｌｅ）の環境下において、各組成素子にそれぞれ異なる熱応力が発生し、構造の反り（ｗａｒｐａｇｅ）を引き起こしやすくなり、甚だしくは構造層間の剥離が生じ、ひいては半導体チップが押圧され、チップの破裂を招くおそれがある。放熱板の厚さを増加させることにより、温度変化時にパッケージ構造が熱の影響で変形することを抑え、基板の反りを抑制することはできるが、放熱板の厚さを増加させればパッケージ構造製品の体積および厚さが増加するため、製造コストの増大を引き起こす。 Since the semiconductor chip 22 is bonded to the surface of the heat sink 21, the semiconductor chip 22 is directly radiated by the heat sink 21, thereby solving the above-described drawbacks of the prior art. However, the coefficient of thermal expansion of the heat sink 21 and the dielectric layer 23 (Coefficient of Th
Since there is a large difference in the thermal expansion (CTE), in such a package structure, each component element has a different heat in a temperature change in the manufacturing process, for example, in a baking or subsequent temperature cycle environment. Stress is generated, and it is easy to cause warpage of the structure. Excessive peeling between the structural layers may occur, and the semiconductor chip may be pressed and the chip may be ruptured. By increasing the thickness of the heat sink, it is possible to suppress the deformation of the package structure due to the effect of heat at the time of temperature change and suppress the warping of the board, but if the thickness of the heat sink is increased, the package structure Increased product volume and thickness causes increased manufacturing costs.

従って、従来の半導体パッケージ構造の製造工程において生じる反り、パッケージ構造の厚さや重量ないしコストの増加、インタフェースの統合の困難さ、製造工程の手順の煩雑さ、製品の電気的品質の低下、放熱を効率よくできない等の問題を克服することのできる、チップ埋め込み型パッケージ構造を提供することは、業界において解決すべき極めて重要な課題である。
アメリカ特許第６，８４１，４１３号 Therefore, warpage that occurs in the manufacturing process of the conventional semiconductor package structure, increase in thickness, weight or cost of the package structure, difficulty in integration of the interface, complicated manufacturing process procedure, reduction in electrical quality of the product, heat dissipation. Providing a chip embedded package structure that can overcome problems such as inefficiency is a very important issue to be solved in the industry.
US Patent No. 6,841,413

以上のような事情に鑑み、本発明は、半導体パッケージ製造工程における構造の反りを回避することができるチップ埋め込み型パッケージ構造およびその製造方法を提供することを課題とする。   In view of the circumstances as described above, it is an object of the present invention to provide a chip embedded type package structure and a method for manufacturing the same that can avoid warping of the structure in a semiconductor package manufacturing process.

また、本発明は、半導体パッケージの厚さ、重量および製造コストを低減させることができるチップ埋め込み型パッケージ構造およびその製造方法を提供することを課題とする。
また、本発明は、チップキャリアおよびチップパッケージの製造工程を統合することにより、より幅広いクライアントの需要にも対応ができ、製造工程の手順、コストおよびインタフェースの統合が簡素化される、チップ埋め込み型パッケージ構造およびその製造方法を提供することを課題とする。 Another object of the present invention is to provide a chip-embedded package structure that can reduce the thickness, weight, and manufacturing cost of a semiconductor package, and a manufacturing method thereof.
In addition, the present invention integrates chip carrier and chip package manufacturing processes to meet a wider range of client demands, and simplifies integration of manufacturing process procedures, costs, and interfaces. It is an object of the present invention to provide a package structure and a manufacturing method thereof.

さらにまた、本発明は、半導体チップが動作時に生じた熱量を効率よく放散することができる、チップ埋め込み型パッケージ構造およびその製造方法を提供することを課題とする。   Still another object of the present invention is to provide a chip-embedded package structure and a method for manufacturing the same that can efficiently dissipate the amount of heat generated during operation of the semiconductor chip.

上記の課題を解決するために、本発明に係るチップ埋め込み型パッケージ構造の製造方法の1つの態様では、少なくとも１つの開口が形成され、前記開口に熱伝導ブロックが形
成されている支持板を準備する工程と、複数の電極パッドを有する半導体チップを前記熱伝導ブロックに接着する工程と、前記半導体チップの電極パッドを露出させるための貫通孔が形成されている誘電層を、前記支持板および前記半導体チップに形成する工程と、前記半導体チップの電極パッドに電気的に接続されている回路層を、前記誘電層に形成する工程と、を備える。また後続の工程において、該回路層に回路ビルドアップ構造がさらに形成され、該回路ビルドアップ構造が該回路層に電気的に接続され、該回路ビルドアップ構造の外表面に複数の導電素子が設けられ、該半導体チップが外部の電子装置に電気的に接続されてもよい。 In order to solve the above problems, in one aspect of the method for manufacturing a chip-embedded package structure according to the present invention, a support plate in which at least one opening is formed and a heat conduction block is formed in the opening is prepared. A step of adhering a semiconductor chip having a plurality of electrode pads to the heat conducting block, and a dielectric layer having a through hole for exposing the electrode pads of the semiconductor chip, the support plate and the Forming on a semiconductor chip, and forming a circuit layer electrically connected to an electrode pad of the semiconductor chip on the dielectric layer. In a subsequent process, a circuit buildup structure is further formed in the circuit layer, the circuit buildup structure is electrically connected to the circuit layer, and a plurality of conductive elements are provided on the outer surface of the circuit buildup structure. The semiconductor chip may be electrically connected to an external electronic device.

また、本発明に係るチップ埋め込み型パッケージ構造の製造方法の他の態様では、少なくとも１つの開口が形成される第１の支持板および第２の支持板を準備し、前記第１の支持板の開口に熱伝導ブロックを形成することにより第１の支持構造を形成し、複数の電極
パッドを有する半導体チップを前記第２の支持板の開口に収容することにより、第２の支持構造を形成する工程と、前記半導体チップが前記熱伝導ブロックの位置に対応して接着されるように、前記第１の支持構造に第２の支持構造を接着し、前記第２の支持構造が誘電層、回路層および回路ビルドアップ構造を有し、前記回路ビルドアップ構造を前記誘電層を貫通する導電構造を介して前記半導体チップの電極パッドに電気的に接続させる工程と、を備える。また後続の工程において、該回路層に回路ビルドアップ構造がさらに形成され、該回路ビルドアップ構造が該回路層に電気的に接続され、該回路ビルドアップ構造の外表面に複数の導電素子が設けられ、該半導体チップが外部の電子装置に電気的に接続される。 In another aspect of the method for manufacturing a chip embedded package structure according to the present invention, a first support plate and a second support plate in which at least one opening is formed are prepared, and the first support plate A first support structure is formed by forming a heat conduction block in the opening, and a second support structure is formed by accommodating a semiconductor chip having a plurality of electrode pads in the opening of the second support plate. A second support structure is bonded to the first support structure so that the semiconductor chip is bonded in correspondence with the position of the heat conduction block, and the second support structure is a dielectric layer, a circuit And a step of electrically connecting the circuit buildup structure to an electrode pad of the semiconductor chip through a conductive structure penetrating the dielectric layer. In a subsequent process, a circuit buildup structure is further formed in the circuit layer, the circuit buildup structure is electrically connected to the circuit layer, and a plurality of conductive elements are provided on the outer surface of the circuit buildup structure. The semiconductor chip is electrically connected to an external electronic device.

さらにまた、本発明に係るチップ埋め込み型パッケージ構造の製造方法のさらに他の態様は、上記の製造方法とほぼ同様であるが、相違点は、まず第２の支持構造に誘電層および回路層を形成し、その後回路層が形成された第２の支持構造を該第１の支持構造に接着する点である。そのほかに、先に前記第２の支持構造を前記第１の支持構造に接着し、その後誘電層、回路層及び回路ビルドアップ構造を前記第２の支持構造に形成させてもよい。   Furthermore, still another aspect of the manufacturing method of the chip embedded type package structure according to the present invention is substantially the same as the manufacturing method described above, except that a dielectric layer and a circuit layer are first added to the second support structure. The second support structure formed and then the circuit layer is bonded to the first support structure. In addition, the second support structure may be first bonded to the first support structure, and then a dielectric layer, a circuit layer, and a circuit build-up structure may be formed on the second support structure.

上記の1つの態様の製造工程によって形成される、本発明に係るチップ埋め込み型パッ
ケージ構造は、少なくとも１つの開口を有し、該開口に熱伝導ブロックが形成されている支持板と、複数の電極パッドを有し、該熱伝導ブロックに接着されている少なくとも１つの半導体チップと、該支持板および該半導体チップに形成され、該半導体チップの電極パッドが露出されている誘電層と、該誘電層に形成され該半導体チップの電極パッドに電気的に接続されている回路層と、を備えており、該チップ埋め込み型パッケージ構造は、該回路層に形成され該回路層に電気的に接続される回路ビルドアップ構造をさらに備える。 The chip-embedded package structure according to the present invention, which is formed by the manufacturing process of one aspect described above, has a support plate having at least one opening, and a heat conduction block formed in the opening, and a plurality of electrodes At least one semiconductor chip having a pad and bonded to the heat conductive block; a dielectric layer formed on the support plate and the semiconductor chip, the electrode pad of the semiconductor chip being exposed; and the dielectric layer And a circuit layer electrically connected to the electrode pad of the semiconductor chip, and the chip embedded package structure is formed in the circuit layer and electrically connected to the circuit layer A circuit build-up structure is further provided.

上記の他の態様の製造工程によって形成される、本発明に係るチップ埋め込み型パッケージ構造は、少なくとも１つの開口を有し、該開口に熱伝導ブロックが形成されている第１の支持板と、該第１の支持板に形成され、該熱伝導ブロックが露出される少なくとも１つの開口を有する第２の支持板と、該熱伝導ブロックに接着され、該第２の支持板の開口に収容され、電極パッドを有する少なくとも１つの半導体チップと、該第２の支持板および半導体チップに形成され、該半導体チップの電極パッドが露出されている誘電層と、該誘電層に形成され、該半導体チップの電極パッドに電気的に接続されている回路層と、を備えており、該チップ埋め込み型パッケージ構造は、該回路層に形成され該回路層に電気的に接続される回路ビルドアップ構造と、該回路ビルドアップ構造の表面に形成される導電素子と、をさらに備える。   The chip embedded type package structure according to the present invention, which is formed by the manufacturing process of the other aspect described above, has a first support plate having at least one opening, and a heat conduction block is formed in the opening. A second support plate formed on the first support plate and having at least one opening through which the heat conduction block is exposed; and is bonded to the heat conduction block and accommodated in the opening of the second support plate. At least one semiconductor chip having an electrode pad, a dielectric layer formed on the second support plate and the semiconductor chip, the electrode pad of the semiconductor chip being exposed, and formed on the dielectric layer, the semiconductor chip And a circuit layer electrically connected to the electrode pad, and the chip embedded package structure is formed in the circuit layer and electrically connected to the circuit layer. Further comprising a structure, a conductive element formed on the surface of the 該回Ro buildup structure.

従来の技術と比較して、本発明に係るチップ埋め込み型パッケージ構造及びその製造方法は、半導体チップを支持板の開口に形成された熱伝導ブロックに接着し、該支持板、熱伝導ブロックおよび誘電層の組み合わせにより、製造工程の温度変化によってパッケージ構造の反りが生じることを回避することができるとともに、従来技術のように、放熱板の厚さを増加することによって製造工程での温度変化のプロセスにおけるパッケージ構造の反りを抑制した結果、パッケージ構造の厚さ、重量および製造工程コストの増加が生じるという欠点を回避することができる。   Compared with the prior art, the chip-embedded package structure and the manufacturing method thereof according to the present invention adheres a semiconductor chip to a heat conduction block formed in an opening of a support plate, and the support plate, the heat conduction block, and the dielectric By combining the layers, it is possible to avoid the warpage of the package structure due to the temperature change of the manufacturing process, and the process of temperature change in the manufacturing process by increasing the thickness of the heat sink as in the prior art As a result of suppressing the warpage of the package structure, the disadvantage that the thickness, weight and manufacturing process cost of the package structure are increased can be avoided.

また、本発明に係るチップ埋め込み型パッケージ構造では、誘電層および回路層に回路ビルドアップ製造工程がさらに行われることにより、該半導体チップが内蔵された支持板に高密度化および細線化された多層回路構造が形成されるとともに、回路構造の外表面に複数の導電素子が設けられることにより、支持板に内蔵された半導体チップが外部の装置に直接電気的に接続されているため、チップキャリアの製造およびチップパッケージの製造工程を統合することができ、より幅広いクライアントの需要にも対応ができ、半導体業
者の製造工程およびインタフェースの統合の問題が簡素化され、最終的なパッケージ製品の電気的品質が向上するようになる。 Further, in the chip embedded type package structure according to the present invention, the circuit build-up manufacturing process is further performed on the dielectric layer and the circuit layer, so that the multi-layered high-density and thin lines are formed on the support plate incorporating the semiconductor chip. Since the circuit structure is formed and a plurality of conductive elements are provided on the outer surface of the circuit structure, the semiconductor chip built in the support plate is directly electrically connected to an external device. Can integrate manufacturing and chip package manufacturing processes to meet wider client demand, simplifying semiconductor manufacturer manufacturing process and interface integration issues, and final package product electrical quality Will be improved.

さらに、本発明において半導体チップが接着されるための熱伝導ブロックは、金属、セラミックまたは無機高放熱材料からなっているため、その上にある半導体チップの動作時に生じた熱量を速やかに効率よく外部に放散することができ、半導体チップの寿命およびパッケージ構造の信頼性を向上させることができる。   Furthermore, since the heat conduction block for bonding the semiconductor chip in the present invention is made of metal, ceramic, or inorganic high heat dissipation material, the amount of heat generated during the operation of the semiconductor chip on it is quickly and efficiently externally applied. The lifetime of the semiconductor chip and the reliability of the package structure can be improved.

以下は、特定の実施例に基づいて本発明の実施形態を説明するものであり、この技術分野に精通した者は、本発明のその他の利点や効果を明細書に記載の内容から容易に理解することができる。本発明は、その他の異なる実施例によって実施や応用をしたり、明細書に記載の内容も異なる観点や応用に基づき、本発明の要旨から逸脱しない範囲で様々な修飾や変更が可能であり、そうした修飾や変更は本発明の請求範囲に入るものである。また、図面や説明の簡素化のため、パッケージ構造に２つの半導体チップが内蔵された例を説明するが、本発明の請求範囲はそれらに限定されるものではない。
［第１の実施形態］
図３-Ａ〜図３-Ｅは、本発明に係るチップ埋め込み型パッケージ構造の製造方法の第１の実施形態の断面を模式的に示す。ここで、それらの図面は簡素化された模式図であり、本発明に係る回路板の製造工程を模式的に示すに過ぎない。即ちそれらの図面では本発明に係る素子のみが表示され、その表示された素子はこれらの実施の形態に限定されるものではなく、その実際に実施される場合の数、形状、及び寸法などは自由に変更して設計することができ、その素子のレイアウト形態がより複雑となるのはいうまでもない。 The following describes embodiments of the present invention based on specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents described in the specification. can do. The present invention can be implemented and applied by other different embodiments, and various modifications and changes can be made without departing from the spirit of the present invention based on different viewpoints and applications described in the specification. Such modifications and changes are intended to fall within the scope of the present invention. In addition, for simplification of the drawings and description, an example in which two semiconductor chips are incorporated in a package structure will be described, but the scope of the present invention is not limited thereto.
[First Embodiment]
3A to 3E schematically show a cross section of the first embodiment of the method for manufacturing a chip-embedded package structure according to the present invention. Here, those drawings are simplified schematic views, and only schematically show the manufacturing steps of the circuit board according to the present invention. That is, only the elements according to the present invention are displayed in those drawings, and the displayed elements are not limited to these embodiments, and the number, shape, dimensions, etc. when actually implemented are as follows. Needless to say, the design can be freely changed and the layout of the element becomes more complicated.

図３-Ａに示すように、まず支持板３０を準備し、該支持板３０に開口３００を形成し
、該開口３００に熱伝導材料を充填し、該開口３００に熱伝導ブロック３１０を形成することにより、後続の工程において、該熱伝導ブロック３１０に半導体チップを接着する。前記支持板３０は、有機材料からなる単層基板または多層基板であり、該熱伝導ブロック３１０は例えば金属、セラミックまたは無機高放熱材料のいずれか一つからなるものであってよい。
次に、図３-Ｂに示すように、熱伝導ブロック３１０に半導体チップ３２０を接着する。
該半導体チップ３２０は、複数の電極パッド３２０ａを有し、熱伝導接着層（図示せず）を介して該熱伝導ブロック３１０に接着されている。また、該支持板３０には複数の電極パッド３２２ａを有する少なくとも１つの受動素子３２２を接着してもよく、該受動素子３２２は接着層（図示せず）を介して該支持板３０に接着されている。
図３-Ｃに示すように、支持板３０、半導体チップ３２０および受動素子３２２に誘電層
３３を形成し、該誘電層３３に複数の貫通孔３３０を形成して該半導体チップ３２０および該受動素子３２２の電極パッド３２０ａ、３２２ａを露出する。該誘電層３３は、エポキシ樹脂（Ｅｐｏｘｙ ｒｅｓｉｎ）、ポリイミド（Ｐｏｌｙｉｍｉｄｅ）、シアン酸エステル（Ｃｙａｎａｔｅ ｅｓｔｅｒ）、ガラスファイバー（Ｇｌａｓｓ ｆｉｂｅｒ）、ビスマレイミド・トリアジン（ＢＴ， Ｂｉｓｍａｌｅｉｍｉｄｅ ｔｒｉａｚｉｎｅ）またはエポキシ樹脂とガラスファイバー等の材質とが混合されたものからなる。 As shown in FIG. 3A, first, the support plate 30 is prepared, the opening 300 is formed in the support plate 30, the heat conduction material is filled in the opening 300, and the heat conduction block 310 is formed in the opening 300. Thus, the semiconductor chip is bonded to the heat conducting block 310 in the subsequent process. The support plate 30 may be a single layer substrate or a multilayer substrate made of an organic material, and the heat conduction block 310 may be made of any one of a metal, a ceramic, and an inorganic high heat dissipation material.
Next, as shown in FIG. 3B, the semiconductor chip 320 is bonded to the heat conducting block 310.
The semiconductor chip 320 has a plurality of electrode pads 320a and is bonded to the heat conductive block 310 via a heat conductive adhesive layer (not shown). Further, at least one passive element 322 having a plurality of electrode pads 322a may be bonded to the support plate 30, and the passive element 322 is bonded to the support plate 30 through an adhesive layer (not shown). ing.
As shown in FIG. 3C, a dielectric layer 33 is formed on the support plate 30, the semiconductor chip 320, and the passive element 322, and a plurality of through holes 330 are formed in the dielectric layer 33 to form the semiconductor chip 320 and the passive element. The electrode pads 320a and 322a of 322 are exposed. The dielectric layer 33 is made of an epoxy resin, a polyimide, a cyanate ester, a glass fiber, a bismaleimide triazine (BT, a bismaleimide triazine) or an epoxy resin and a glass fiber. It is made of a mixture of these materials.

図３-Ｄに示すように、誘電層３３に回路層３４を形成し、該回路層３４を該半導体チ
ップ３２０および該受動素子３２２に電気的に接続させている。該回路層３４は、該誘電層３３の貫通孔３３０に形成された導電構造３４０（例えば導電性を有するブラインドビアまたは導電バンプ）を介して該半導体チップ３２０および該受動素子３２２の電極パッド３２０ａ、３２２ａに電気的に接続されている。ただし、該回路層３４を形成する技術は多種多様であり且つ業界に周知されたものであるため、ここでは詳しい説明を省略する。 As shown in FIG. 3D, a circuit layer 34 is formed on the dielectric layer 33, and the circuit layer 34 is electrically connected to the semiconductor chip 320 and the passive element 322. The circuit layer 34 is connected to the semiconductor chip 320 and the electrode pads 320a of the passive elements 322 through conductive structures 340 (for example, conductive blind vias or conductive bumps) formed in the through holes 330 of the dielectric layer 33. It is electrically connected to 322a. However, since the techniques for forming the circuit layer 34 are various and well known in the industry, detailed description thereof is omitted here.

従って、本発明は、支持板３０の開口に形成される熱伝導ブロック３１０を介して半導体チップを接着し、該支持板３０、熱伝導ブロック３１０および誘電層３３の組み合わせにより、製造工程の温度変化によってパッケージ構造の反りが生じることを回避することができるとともに、従来技術のような、放熱板の厚さを増加したことによって生じるパッケージ構造の厚さ、重量および製造工程コストの増加を回避することができる。   Accordingly, in the present invention, a semiconductor chip is bonded via the heat conduction block 310 formed in the opening of the support plate 30, and the temperature change in the manufacturing process is achieved by the combination of the support plate 30, the heat conduction block 310 and the dielectric layer 33. As a result, it is possible to avoid the warpage of the package structure due to the increase in the thickness, weight and manufacturing process cost of the package structure caused by increasing the thickness of the heat sink as in the prior art. Can do.

図３-Ｅに示すように、この後、回路層３４に回路ビルドアップ製造工程が行われるこ
とにより、該回路層３４に回路ビルドアップ構造３５を形成し、且つ該回路ビルドアップ構造３５を該回路層３４に電気的に接続させている。このうち、回路ビルドアップ構造３５は、少なくとも１つの絶縁層３５０と、該絶縁層３５０に積層されている回路層３５２と、該絶縁層３５０を貫通し、該回路層３５２を絶縁層の下方の回路層３４に電気的に接続している導電構造３５２ａとを備え、該導電構造３５２ａは例えば導電性を有するブラインドビアである。 Thereafter, as shown in FIG. 3E, a circuit buildup manufacturing process is performed on the circuit layer 34, thereby forming a circuit buildup structure 35 on the circuit layer 34. The circuit layer 34 is electrically connected. Among these, the circuit build-up structure 35 includes at least one insulating layer 350, a circuit layer 352 stacked on the insulating layer 350, and the insulating layer 350. The circuit layer 352 is disposed below the insulating layer. A conductive structure 352a electrically connected to the circuit layer 34. The conductive structure 352a is, for example, a blind via having conductivity.

また、回路ビルドアップ構造３５の外表面の回路層に複数の電気接続パッド３５４が形成され、該電気接続パッド３５４を露出させる複数の貫通孔を有する絶縁保護層３６が被覆され、複数の導電素子３７、例えば半田ボール（ｓｏｌｄｅｒ ｂａｌｌ）、導電柱または半田柱が設けられることにより、該支持板３０の熱伝導ブロック３１０に接着された半導体チップ３２０が外部の電子装置に電気的に接続される。また、ここでは、該回路ビルドアップ構造が図示された層数に限定されるものではなく、実際の必要に応じて層数を増加させてもよい。   In addition, a plurality of electrical connection pads 354 are formed on a circuit layer on the outer surface of the circuit buildup structure 35, and an insulating protective layer 36 having a plurality of through holes exposing the electrical connection pads 354 is covered, and a plurality of conductive elements 37, for example, by providing a solder ball, a conductive column or a solder column, the semiconductor chip 320 bonded to the heat conductive block 310 of the support plate 30 is electrically connected to an external electronic device. Here, the circuit build-up structure is not limited to the illustrated number of layers, and the number of layers may be increased according to actual needs.

上記の製造工程によって形成されるチップ埋め込み型パッケージ構造は、開口３００を有し該開口３００に熱伝導ブロック３１０が形成されている支持板３０と、該熱伝導ブロック３１０に接着されている半導体チップ３２０と、該支持板３０および該半導体チップ３２０に形成されている誘電層３３と、該誘電層３３に形成され該半導体チップ３２０に電気的に接続されている回路層３４と、を備える。また、該チップ埋め込み型パッケージ構造は、受動素子３２２および回路ビルドアップ構造３５をさらに備える。   The chip-embedded package structure formed by the above manufacturing process includes a support plate 30 having an opening 300 and a heat conduction block 310 formed in the opening 300, and a semiconductor chip bonded to the heat conduction block 310. 320, a dielectric layer 33 formed on the support plate 30 and the semiconductor chip 320, and a circuit layer 34 formed on the dielectric layer 33 and electrically connected to the semiconductor chip 320. The chip embedded package structure further includes a passive element 322 and a circuit buildup structure 35.

前記支持板３０は、有機材料からなる単層基板または多層基板である。該熱伝導ブロック３１０、３１１は、金属、セラミックまたは無機高放熱材料のいずれか一つからなる。
半導体チップ３２０は複数の電極パッド３２０ａを有し、熱伝導ブロック３１０に接着されてよい。受動素子３２２は複数の電極パッド３２２ａを有し、支持板３０に直接接着されてよい。 The support plate 30 is a single layer substrate or a multilayer substrate made of an organic material. The heat conducting blocks 310 and 311 are made of any one of metal, ceramic, and inorganic high heat dissipation material.
The semiconductor chip 320 has a plurality of electrode pads 320 a and may be bonded to the heat conducting block 310. The passive element 322 has a plurality of electrode pads 322 a and may be directly bonded to the support plate 30.

誘電層３３は半導体チップ３２０および受動素子３２２の電極パッド３２０ａ、３２２ａを露出させるための複数の貫通孔３３０を有する。
回路層３４は、該誘電層３３に形成され、該誘電層に形成される導電構造３４０により該半導体チップ３２０および該受動素子３２２の電極パッド３２０ａ、３２２ａに電気的に接続されている。 The dielectric layer 33 has a plurality of through holes 330 for exposing the electrode pads 320 a and 322 a of the semiconductor chip 320 and the passive element 322.
The circuit layer 34 is formed on the dielectric layer 33, and is electrically connected to the semiconductor chip 320 and the electrode pads 320 a and 322 a of the passive element 322 by a conductive structure 340 formed in the dielectric layer.

回路ビルドアップ構造３５は、回路層３４に形成され、且つ該回路層３４に電気的に接続されている。また、該回路ビルドアップ構造３５の外表面の回路層には複数の電気接続パッド３５４が形成され、その最外層の回路層に例えばソルダーレジスト層である絶縁保護層３６が被覆され、該絶縁保護層３６には、複数の導電素子３７を設けられるように、該電気接続パッド３５４を露出させるための複数の貫通孔が設けられ、該支持板３０の熱伝導ブロック３１０に接着された該半導体チップ３２０が外部の電子装置に電気的に接続されている。
［第２の実施形態］
図４-Ａ〜図４-Ｅは、本発明に係るチップ埋め込み型パッケージ構造の製造方法の第２の実施形態の断面を模式的に示す。 The circuit build-up structure 35 is formed in the circuit layer 34 and is electrically connected to the circuit layer 34. In addition, a plurality of electrical connection pads 354 are formed on the circuit layer on the outer surface of the circuit build-up structure 35, and the outermost circuit layer is covered with an insulating protective layer 36, for example, a solder resist layer. In the layer 36, a plurality of through holes for exposing the electrical connection pads 354 are provided so that a plurality of conductive elements 37 can be provided, and the semiconductor chip bonded to the heat conduction block 310 of the support plate 30. 320 is electrically connected to an external electronic device.
[Second Embodiment]
4A to 4E schematically show a cross section of a second embodiment of the method for manufacturing a chip embedded package structure according to the present invention.

図４-Ａに示すように、まず第１の支持板４０および第２の支持板４１を準備し、該第
１の支持板４０に開口４００を形成し、該開口４００に熱伝導材料を充填し、熱伝導ブロック４２０を形成することにより、第１の支持構造４ａを形成するとともに、該第２の支持板４１における該第１の支持板４０の開口４００に対応する位置に開口４１０を形成し、半導体チップ４３０を該開口４１０に収容固定し、また、該第２の支持板４１に少なくとも１つの受動素子４３２を収容固定するための開口４１２をさらに形成することにより、第２の支持構造４ｂを形成する。 As shown in FIG. 4A, first, a first support plate 40 and a second support plate 41 are prepared, an opening 400 is formed in the first support plate 40, and a heat conduction material is filled in the opening 400. Then, by forming the heat conduction block 420, the first support structure 4a is formed, and the opening 410 is formed at a position corresponding to the opening 400 of the first support plate 40 in the second support plate 41. Then, the semiconductor chip 430 is accommodated and fixed in the opening 410, and the opening 412 for accommodating and fixing the at least one passive element 432 is further formed in the second support plate 41, whereby the second support structure is formed. 4b is formed.

前記第１、第２の支持板４０、４１は有機材料からなる単層基板または多層基板である。前記熱伝導ブロック４２０は金属、セラミックおよび無機高放熱材料のいずれか一つからなる。前記半導体チップ４３０は複数の電極パッド４３０ａを有し、前記受動素子４３２は複数の電極パッド４３２ａを有している。   The first and second support plates 40 and 41 are single layer substrates or multilayer substrates made of an organic material. The heat conduction block 420 is made of one of metal, ceramic, and inorganic high heat dissipation material. The semiconductor chip 430 has a plurality of electrode pads 430a, and the passive element 432 has a plurality of electrode pads 432a.

図４-Ｂに示すように、前記第２の支持構造４ｂを接着層（図示せず）を介して前記第
１の支持構造４ａに接着し、前記半導体チップ４３０が該第１の支持構造４ａの熱伝導ブロック４２０に対応して接着される。 As shown in FIG. 4B, the second support structure 4b is bonded to the first support structure 4a through an adhesive layer (not shown), and the semiconductor chip 430 is bonded to the first support structure 4a. The heat conduction block 420 is bonded in correspondence.

次に、図４-Ｃに示すように、前記第２の支持構造４Ｂに誘電層４４を形成し、該誘電
層４４に複数の貫通孔４４０を形成し、半導体チップ４３０および受動素子４３２における複数の電極パッド４３０ａ、４３２ａが露出される。 Next, as shown in FIG. 4C, a dielectric layer 44 is formed in the second support structure 4B, a plurality of through holes 440 are formed in the dielectric layer 44, and a plurality of semiconductor chips 430 and a plurality of passive elements 432 are formed. The electrode pads 430a and 432a are exposed.

図４-Ｄに示すように、前記誘電層４４に回路層４５を形成し、該回路層４５は該誘電
層４４に形成された導電構造４５０を介して半導体チップ４３０および受動素子４３２における電極パッド４３０ａ、４３２ａに電気的に接続される。 As shown in FIG. 4D, a circuit layer 45 is formed on the dielectric layer 44, and the circuit layer 45 is connected to electrode pads on the semiconductor chip 430 and the passive element 432 through a conductive structure 450 formed on the dielectric layer 44. 430a and 432a are electrically connected.

次に、本発明において、必要に応じて誘電層４４および回路層４５に回路ビルドアップ製造工程が行われることにより、必要とする電気的設計の回路接続を構成することができる。   Next, in the present invention, a circuit build-up manufacturing process is performed on the dielectric layer 44 and the circuit layer 45 as necessary, whereby a circuit connection having a required electrical design can be configured.

図４-Ｅに示すように、誘電層４４および回路層４５に回路ビルドアップ製造工程が行
われることにより、回路ビルドアップ構造４６を形成し、該回路ビルドアップ構造４６を該回路層４５に電気的に接続させている。該回路ビルドアップ構造４６は、少なくとも１つの絶縁層４６０と、該絶縁層４６０に積層されている回路層４６２と、該絶縁層４６０を貫通し、該回路層４６２を絶縁層の下方の回路層４５に電気的に接続する導電構造４６２ａ（例えば導電性を有するブラインドビア）と、を有している。 As shown in FIG. 4E, a circuit buildup manufacturing process is performed on the dielectric layer 44 and the circuit layer 45 to form a circuit buildup structure 46, and the circuit buildup structure 46 is electrically connected to the circuit layer 45. Connected. The circuit build-up structure 46 includes at least one insulating layer 460, a circuit layer 462 laminated on the insulating layer 460, and the insulating layer 460. The circuit layer 462 is disposed below the insulating layer. And a conductive structure 462a (for example, a blind via having conductivity) electrically connected to 45.

また、該回路ビルドアップ構造４６の外表面の回路層に複数の電気接続パッド４６４を形成し、その最外層の回路層に絶縁保護層４７が被覆され、該絶縁保護層４７に、導電素子４８を設けられるように、該電気接続パッド４６４を露出させるための複数の貫通孔が設けられることにより、第１の支持板４０の開口における熱伝導ブロック４２０に接着され且つ第２の支持板の開口４１０に収容される半導体チップ４３０が外部の電子装置に電気的に接続される。ここで、該回路ビルドアップ構造は図示された層数に限定されるものではなく、実際の必要に応じて層数を増加させてもよい。
［第３の実施形態］
さらに図５-Ａ〜図５-Ｅは、本発明に係るチップ埋め込み型パッケージ構造の製造方法の第３の実施形態の断面を模式的に示す。本実施形態の製造方法は第２の実施形態とほぼ同様であるが、相違点は、先に第２の支持構造への回路ビルドアップ製造工程が行われ、
半導体チップの外部への電気的接続を完了させたうえで、続いて回路ビルドアップ製造工程を終えた第２の支持構造を第１の支持構造に接着する点である。 In addition, a plurality of electrical connection pads 464 are formed on the circuit layer on the outer surface of the circuit build-up structure 46, and the insulating protective layer 47 is covered on the outermost circuit layer, and the conductive protective element 48 is formed on the insulating protective layer 47. By providing a plurality of through holes for exposing the electrical connection pads 464, the openings are bonded to the heat conduction block 420 at the opening of the first support plate 40 and the opening of the second support plate. The semiconductor chip 430 accommodated in 410 is electrically connected to an external electronic device. Here, the circuit build-up structure is not limited to the illustrated number of layers, and the number of layers may be increased according to actual needs.
[Third Embodiment]
Further, FIGS. 5A to 5E schematically show cross sections of a third embodiment of the method for manufacturing a chip embedded package structure according to the present invention. The manufacturing method of this embodiment is almost the same as that of the second embodiment, except that the circuit build-up manufacturing process for the second support structure is performed first.
The second support structure that has completed the circuit buildup manufacturing process is bonded to the first support structure after electrical connection to the outside of the semiconductor chip is completed.

図５-Ａに示すように、まず第１の支持板４ａおよび第２の支持板４ｂを準備する。該
第１の支持構造４ａは第１の支持板４０および該第１の支持板の開口に形成される熱伝導ブロック４２０を有し、該第２の支持構造４ｂは第２の支持板４１および該第２の支持板の開口に収容される半導体チップ４３０と受動素子４３２を有し、該半導体チップ４３０および受動素子４３２に複数の電極パッド４３０ａ、４３２ａが設けられている。 As shown in FIG. 5A, first, a first support plate 4a and a second support plate 4b are prepared. The first support structure 4a includes a first support plate 40 and a heat conduction block 420 formed in an opening of the first support plate, and the second support structure 4b includes the second support plate 41 and The semiconductor chip 430 accommodated in the opening of the second support plate and the passive element 432 are provided, and the semiconductor chip 430 and the passive element 432 are provided with a plurality of electrode pads 430a and 432a.

次に、図５-Ｂに示すように、第２の支持構造４ｂに誘電層４４を形成し、該誘電層に
半導体チップ４３０および受動素子４３２の電極パッド４３０ａ、４３２ａを露出させるための複数の貫通孔４４０を形成する。 Next, as shown in FIG. 5B, a dielectric layer 44 is formed on the second support structure 4b, and a plurality of electrode pads 430a and 432a for exposing the semiconductor chip 430 and the passive element 432 to the dielectric layer are exposed. A through hole 440 is formed.

図５-Ｃに示すように、誘電層４４に回路層４５を形成し、該回路層４５が誘電層の貫
通孔４４０に形成された導電構造４５０を介して半導体チップ４３０および受動素子４３２の電極パッド４３０ａ、４３２ａに電気的に接続されている。 As shown in FIG. 5C, a circuit layer 45 is formed in the dielectric layer 44, and the electrodes of the semiconductor chip 430 and the passive element 432 are formed through a conductive structure 450 formed in the through hole 440 of the dielectric layer. The pads 430a and 432a are electrically connected.

図５-Ｄに示すように、回路層４５に回路ビルドアップ製造工程が行われることにより
回路ビルドアップ構造４６を形成する。この回路ビルドアップ構造４６は絶縁層４６０と、該絶縁層４６０を貫通し、回路層４６２を絶縁層の下方の回路層４５に電気的に接続する導電構造４６２ａと、を備えている。また、該回路ビルドアップ構造４６の外表面の回路層に複数の電気接続パッド４６４を形成し、該電気接続パッド４６４を露出させるための複数の貫通孔を有している絶縁保護層４７が被覆されている。 As shown in FIG. 5D, a circuit buildup structure 46 is formed by performing a circuit buildup manufacturing process on the circuit layer 45. The circuit build-up structure 46 includes an insulating layer 460 and a conductive structure 462a that penetrates the insulating layer 460 and electrically connects the circuit layer 462 to the circuit layer 45 below the insulating layer. A plurality of electrical connection pads 464 are formed on the circuit layer on the outer surface of the circuit build-up structure 46, and the insulating protective layer 47 having a plurality of through holes for exposing the electrical connection pads 464 is covered. Has been.

図５-Ｅに示すように、回路製造工程が終了した第２の支持構造４ｂが接着層（図示せ
ず）を介して第１の支持構造４ａに接着され、半導体チップ４３０が熱伝導ブロック４２０の位置に対応する。最後に該絶縁保護層４７の貫通孔における電気接続パッド４６４に導電素子４８を形成する。 As shown in FIG. 5E, the second support structure 4b after the circuit manufacturing process is bonded to the first support structure 4a through an adhesive layer (not shown), and the semiconductor chip 430 is bonded to the heat conduction block 420. Corresponds to the position of. Finally, a conductive element 48 is formed on the electrical connection pad 464 in the through hole of the insulating protective layer 47.

上記の製造工程によって形成されるチップ埋め込み型パッケージ構造は、開口４００を有し該開口４００に熱伝導ブロック４２０が形成されている第１の支持板４０と、該第１の支持板４０に接着され、該第１の支持板の開口４００に対応する位置に熱伝導ブロック４２０を露出させる開口４１０が形成されている第２の支持板４１と、該熱伝導ブロック４２０に接着され該第２の支持板の開口４１０に収容されている半導体チップ４３０と、該第２の支持板４１および該半導体チップ４３０に形成されている誘電層４４と、該誘電層４４に形成され該半導体チップ４３０に電気的に接続されている回路層４５とを備えている。また、本発明に係るチップ埋め込み型パッケージ構造は、該第１の支持板４０に接着され、該第２の支持板４１に内蔵された少なくとも１つの受動素子４３２と、該回路層４５に形成され該回路層４５に電気的に接続されている回路ビルドアップ構造４６とをさらに備えている。また、該回路ビルドアップ構造４６の外表面の回路層に複数の電気接続パッド４６４が形成され、その最外層の回路層に絶縁保護層４７が被覆され、該絶縁保護層４７に、複数の導電素子４８を設けられるように、該電気接続パッド４６４を露出させるための複数の貫通孔が設けられている。   The chip-embedded package structure formed by the manufacturing process described above includes a first support plate 40 having an opening 400 and a heat conduction block 420 formed in the opening 400, and an adhesion to the first support plate 40. A second support plate 41 having an opening 410 for exposing the heat conduction block 420 at a position corresponding to the opening 400 of the first support plate, and the second support plate 41 bonded to the heat conduction block 420 The semiconductor chip 430 accommodated in the opening 410 of the support plate, the dielectric layer 44 formed on the second support plate 41 and the semiconductor chip 430, and the semiconductor chip 430 formed on the dielectric layer 44 And a circuit layer 45 connected to each other. The chip embedded type package structure according to the present invention is formed on the circuit layer 45 and at least one passive element 432 that is bonded to the first support plate 40 and built in the second support plate 41. And a circuit build-up structure 46 electrically connected to the circuit layer 45. In addition, a plurality of electrical connection pads 464 are formed on the circuit layer on the outer surface of the circuit build-up structure 46, and the outermost circuit layer is covered with an insulating protective layer 47. The insulating protective layer 47 has a plurality of conductive layers. A plurality of through holes for exposing the electrical connection pads 464 are provided so that the element 48 can be provided.

従来の技術と比較して、本発明に係るチップ埋め込み型パッケージ構造およびその製造方法は、主に半導体チップを支持板（または第１の支持板）の開口に形成された熱伝導ブロックに接着し、該チップを外部へ電気的に接続させることにより、チップ埋め込み型パッケージ構造を形成させているため、本発明によれば、該支持板および該支持板に形成された組み合わせ構造を介して、製造工程における温度変化がパッケージ構造にもたらす熱応力のバランスを維持することができるため、製造工程にける温度変化によってパッケー
ジ構造の反りが生じることを回避することができるとともに、従来技術のような、放熱板の厚さを増加したことによって生じるパッケージ構造の厚さ、重量および製造工程コストの増加を回避することができる。また、本発明は、実際の設計の必要に応じて支持板に能動素子および受動素子が収容され、複数の能受動素子が統合されたモジュール化パッケージ構造を形成することができるため、電子製品の多機能化の需要を満たしている。 Compared with the prior art, the chip-embedded package structure and the manufacturing method thereof according to the present invention mainly bond a semiconductor chip to a heat conduction block formed in an opening of a support plate (or a first support plate). Since the chip embedded type package structure is formed by electrically connecting the chip to the outside, according to the present invention, the manufacturing is performed via the support plate and the combination structure formed on the support plate. Since the balance of thermal stress brought about by the temperature change in the process on the package structure can be maintained, it is possible to avoid the warpage of the package structure due to the temperature change in the manufacturing process, and heat dissipation as in the prior art. The increase in thickness, weight and manufacturing process cost of the package structure caused by increasing the plate thickness can be avoided In addition, the present invention can form a modular package structure in which an active element and a passive element are accommodated in a support plate according to actual design needs and a plurality of active and passive elements are integrated. It meets the demand for multi-function.

また、本発明に係るチップ埋め込み型パッケージ構造では、誘電層および回路層に回路ビルドアップ製造工程がさらに行われることにより、半導体チップが内蔵された支持板に高密度化および細線化の多層回路構造が形成されるとともに、回路構造の外表面に複数の導電素子が設けられることにより、支持板に内蔵された半導体チップが外部の装置に直接電気的に接続されているため、チップキャリアの製造およびパッケージング工程を統合することができ、より幅広いクライアントの需要にも対応ができ、半導体業者の製造工程およびインタフェースの統合の問題を簡素化することができる。   Further, in the chip embedded type package structure according to the present invention, the circuit build-up manufacturing process is further performed on the dielectric layer and the circuit layer, so that the multi-layer circuit structure with high density and thin line is formed on the support plate in which the semiconductor chip is built. In addition, since a plurality of conductive elements are provided on the outer surface of the circuit structure, the semiconductor chip built in the support plate is directly electrically connected to an external device. The packaging process can be integrated to meet a wider range of client demands, and the semiconductor manufacturer's manufacturing process and interface integration issues can be simplified.

さらに、本発明に係るチップ埋め込み型パッケージ構造は、熱伝導ブロックが高放熱である金属、セラミックまたは無機材料のいずれか１つからなっているため、該熱伝導ブロックを放熱ルートとしてその上に直接接着された半導体チップの動作時に生じた熱量を速やかに且つ効率よく外部に放散することができ、半導体チップの寿命およびパッケージ構造の信頼性を向上させることができる。   Further, in the chip embedded type package structure according to the present invention, the heat conduction block is made of any one of a metal, ceramic or inorganic material having high heat dissipation, so that the heat conduction block is directly used as a heat dissipation route. The amount of heat generated during operation of the bonded semiconductor chip can be quickly and efficiently dissipated to the outside, and the life of the semiconductor chip and the reliability of the package structure can be improved.

上記のように、これらの実施の形態は本発明を例示する目的で示すものであり、本発明は、これらによって何ら限定されるものではない。本発明に係る実質的な技術内容は、特許請求の範囲に定義される。本発明はこの技術分野に精通したものが特許請求の範囲を脱しない範囲で色々な修飾や変更が可能であり、そうした修飾や変更は本発明の請求範囲に入るものである。   As described above, these embodiments are shown for the purpose of illustrating the present invention, and the present invention is not limited thereto. The substantial technical contents of the present invention are defined in the claims. Those skilled in the art can make various modifications and changes without departing from the scope of the claims, and such modifications and changes fall within the scope of the claims of the present invention.

従来のフリップチップ型半導体素子の断面を模式的に示す図である。It is a figure which shows typically the cross section of the conventional flip chip type semiconductor element. アメリカ特許第６，８４１，４１３号発明の断面を模式的に示す図である。It is a figure which shows typically the cross section of US Patent 6,841,413 invention. 本発明に係るチップ埋め込み型パッケージ構造の製造方法の第１の実施形態の断面を模式的に示す図である。It is a figure which shows typically the cross section of 1st Embodiment of the manufacturing method of the chip | tip embedded package structure which concerns on this invention. 本発明に係るチップ埋め込み型パッケージ構造の製造方法の第１の実施形態の断面を模式的に示す図である。It is a figure which shows typically the cross section of 1st Embodiment of the manufacturing method of the chip | tip embedded package structure which concerns on this invention. 本発明に係るチップ埋め込み型パッケージ構造の製造方法の第１の実施形態の断面を模式的に示す図である。It is a figure which shows typically the cross section of 1st Embodiment of the manufacturing method of the chip | tip embedded package structure which concerns on this invention. 本発明に係るチップ埋め込み型パッケージ構造の製造方法の第１の実施形態の断面を模式的に示す図である。It is a figure which shows typically the cross section of 1st Embodiment of the manufacturing method of the chip | tip embedded package structure which concerns on this invention. 本発明に係るチップ埋め込み型パッケージ構造の製造方法の第１の実施形態の断面を模式的に示す図である。It is a figure which shows typically the cross section of 1st Embodiment of the manufacturing method of the chip | tip embedded package structure which concerns on this invention. 本発明に係るチップ埋め込み型パッケージ構造の製造方法の第２の実施形態の断面を模式的に示す図である。It is a figure which shows typically the cross section of 2nd Embodiment of the manufacturing method of the chip | tip embedded package structure which concerns on this invention. 本発明に係るチップ埋め込み型パッケージ構造の製造方法の第２の実施形態の断面を模式的に示す図である。It is a figure which shows typically the cross section of 2nd Embodiment of the manufacturing method of the chip | tip embedded package structure which concerns on this invention. 本発明に係るチップ埋め込み型パッケージ構造の製造方法の第２の実施形態の断面を模式的に示す図である。It is a figure which shows typically the cross section of 2nd Embodiment of the manufacturing method of the chip | tip embedded package structure which concerns on this invention. 本発明に係るチップ埋め込み型パッケージ構造の製造方法の第２の実施形態の断面を模式的に示す図である。It is a figure which shows typically the cross section of 2nd Embodiment of the manufacturing method of the chip | tip embedded package structure which concerns on this invention. 本発明に係るチップ埋め込み型パッケージ構造の製造方法の第２の実施形態の断面を模式的に示す図である。It is a figure which shows typically the cross section of 2nd Embodiment of the manufacturing method of the chip | tip embedded package structure which concerns on this invention. 本発明に係るチップ埋め込み型パッケージ構造の製造方法の第３の実施形態の断面を模式的に示す図である。It is a figure which shows typically the cross section of 3rd Embodiment of the manufacturing method of the chip | tip embedded package structure which concerns on this invention. 本発明に係るチップ埋め込み型パッケージ構造の製造方法の第３の実施形態の断面を模式的に示す図である。It is a figure which shows typically the cross section of 3rd Embodiment of the manufacturing method of the chip | tip embedded package structure which concerns on this invention. 本発明に係るチップ埋め込み型パッケージ構造の製造方法の第３の実施形態の断面を模式的に示す図である。It is a figure which shows typically the cross section of 3rd Embodiment of the manufacturing method of the chip | tip embedded package structure which concerns on this invention. 本発明に係るチップ埋め込み型パッケージ構造の製造方法の第３の実施形態の断面を模式的に示す図である。It is a figure which shows typically the cross section of 3rd Embodiment of the manufacturing method of the chip | tip embedded package structure which concerns on this invention. 本発明に係るチップ埋め込み型パッケージ構造の製造方法の第３の実施形態の断面を模式的に示す図である。It is a figure which shows typically the cross section of 3rd Embodiment of the manufacturing method of the chip | tip embedded package structure which concerns on this invention.

符号の説明Explanation of symbols

１１ チップ
１１０ 電極パッド
１２ 金属バンプ
１３ 回路板
１３０ 接触パッド
１４ アンダーフィル
１５ プリ半田バンプ
２１ 放熱板
２３０，２５０，２７０ 貫通孔
２２ チップ
２２１ 電極パッド
２４，２５ 回路層
３０ 支持板
３００ 開口
３３０，４４０ 貫通孔
３１０，４２０ 熱伝導ブロック
３２０，４３０ 半導体チップ
３２０ａ，３２２ａ，４３０ａ，４３２ａ 電極パッド
３３，４４ 誘電層
３４，４５ 回路層
３４０，４５０ 導電構造
３２２，４３２ 受動素子
３５，４６ 回路ビルドアップ構造
３５０，４６０ 絶縁層
３５２，４６２ 回路層
３５２ａ，４６２ａ 導電構造
３５４，４６４ 電気接続パッド
３６，４７ 絶縁保護層
３７，４８ 導電素子
４０ 第１の支持板
４１ 第２の支持板
４００，４１０，４１２ 開口
４ａ 第１の支持構造
４ｂ 第２の支持構造 11 Chip 110 Electrode pad 12 Metal bump 13 Circuit board 130 Contact pad 14 Underfill 15 Pre-solder bump 21 Heat sink 230, 250, 270 Through hole 22 Chip 221 Electrode pad 24, 25 Circuit layer 30 Support plate
300 Openings 330, 440 Through holes 310, 420 Thermal conduction blocks 320, 430 Semiconductor chips 320a, 322a, 430a, 432a Electrode pads 33, 44 Dielectric layers 34, 45 Circuit layers 340, 450 Conductive structures 322, 432 Passive elements 35, 46 Circuit buildup structure 350, 460 Insulating layer 352, 462 Circuit layer 352a, 462a Conductive structure 354, 464 Electrical connection pad 36, 47 Insulating protective layer 37, 48 Conductive element 40 First support plate 41 Second support plate 400, 410, 412 Opening 4a First support structure 4b Second support structure

Claims (18)

少なくとも１つの開口が形成され、前記開口に熱伝導ブロックが形成されている支持板を準備する工程と、
複数の電極パッドを有する半導体チップを前記熱伝導ブロックに接着する工程と、
前記半導体チップの電極パッドを露出させるための貫通孔が形成されている誘電層を、前記支持板および前記半導体チップに形成する工程と、
前記半導体チップの電極パッドに電気的に接続されている回路層を、前記誘電層に形成する工程と、
を備えていることを特徴とするチップ埋め込み型パッケージ構造の製造方法。 Providing a support plate having at least one opening formed therein and a heat conduction block formed in the opening;
Bonding a semiconductor chip having a plurality of electrode pads to the thermally conductive block;
Forming a dielectric layer in which a through hole for exposing an electrode pad of the semiconductor chip is formed in the support plate and the semiconductor chip;
Forming a circuit layer electrically connected to the electrode pads of the semiconductor chip on the dielectric layer;
A method of manufacturing a chip-embedded package structure, comprising: 前記回路層に回路ビルドアップ構造を形成し、前記回路ビルドアップ構造を前記回路層に電気的に接続する工程をさらに備えていることを特徴とする請求項１に記載のチップ埋め込み型パッケージ構造の製造方法。   2. The chip embedded package structure according to claim 1, further comprising a step of forming a circuit buildup structure in the circuit layer and electrically connecting the circuit buildup structure to the circuit layer. Production method. 前記支持板に少なくとも１つの受動素子を接着し、前記回路層を前記受動素子に電気的に接続させることを特徴とする請求項１または２に記載のチップ埋め込み型パッケージ構造の製造方法。   3. The method of manufacturing a chip-embedded package structure according to claim 1, wherein at least one passive element is bonded to the support plate, and the circuit layer is electrically connected to the passive element. 前記熱伝導ブロックは、金属、セラミックおよび無機高放熱材料のいずれか１つからなることを特徴とする請求項１〜３のいずれかに記載のチップ埋め込み型パッケージ構造の製造方法。   The method for manufacturing a chip-embedded package structure according to any one of claims 1 to 3, wherein the heat conduction block is made of any one of a metal, a ceramic, and an inorganic high heat dissipation material. 少なくとも１つの開口が形成される第１の支持板および第２の支持板を準備し、前記第１の支持板の開口に熱伝導ブロックを形成することにより第１の支持構造を形成し、複数の電極パッドを有する半導体チップを前記第２の支持板の開口に収容することにより、第２の支持構造を形成する工程と、
前記半導体チップが前記熱伝導ブロックの位置に対応して接着されるように、前記第１の支持構造に第２の支持構造を接着し、前記第２の支持構造が誘電層、回路層および回路ビルドアップ構造を有し、前記回路ビルドアップ構造を、前記誘電層を貫通する導電構造を介して前記半導体チップの電極パッドに電気的に接続させる工程と、
を備えていることを特徴とするチップ埋め込み型パッケージ構造の製造方法。 Preparing a first support plate and a second support plate in which at least one opening is formed, and forming a first support structure by forming a heat conduction block in the opening of the first support plate; Forming a second support structure by accommodating a semiconductor chip having a plurality of electrode pads in the opening of the second support plate;
A second support structure is bonded to the first support structure so that the semiconductor chip is bonded corresponding to the position of the heat conducting block, and the second support structure is a dielectric layer, a circuit layer, and a circuit. Having a build-up structure, electrically connecting the circuit build-up structure to an electrode pad of the semiconductor chip through a conductive structure penetrating the dielectric layer;
A method of manufacturing a chip-embedded package structure, comprising: 前記第２の支持構造に誘電層、回路層および回路ビルドアップ構造を形成しておき、前記第１の支持構造に接着することを特徴とする請求項５に記載のチップ埋め込み型パッケージ構造の製造方法。   6. The method of manufacturing a chip-embedded package structure according to claim 5, wherein a dielectric layer, a circuit layer, and a circuit build-up structure are formed on the second support structure and bonded to the first support structure. Method. 前記第２の支持構造を前記第１の支持構造に接着しておき、前記第２の支持構造に誘電層、回路層および回路ビルドアップ構造を形成することを特徴とする請求項５または６に記載のチップ埋め込み型パッケージ構造の製造方法。   7. The second support structure is bonded to the first support structure, and a dielectric layer, a circuit layer, and a circuit build-up structure are formed on the second support structure. A manufacturing method of the chip embedded type package structure described. 前記回路ビルドアップ構造の外表面の回路層に複数の電気接続パッドを形成し、前記回路ビルドアップ構造の外表面に絶縁保護層を形成し、前記絶縁保護層に前記電気接続パッドを露出させるための複数の貫通孔を形成することを特徴とする請求項５〜７のいずれかに記載のチップ埋め込み型パッケージ構造の製造方法。   A plurality of electrical connection pads are formed on a circuit layer on the outer surface of the circuit build-up structure, an insulating protective layer is formed on the outer surface of the circuit build-up structure, and the electrical connection pads are exposed to the insulating protective layer The method of manufacturing a chip embedded type package structure according to claim 5, wherein a plurality of through holes are formed. 少なくとも１つの受動素子が前記第２の支持板に収容され、前記回路層が前記受動素子に電気的に接続されていることを特徴とする請求項５〜８のいずれかに記載のチップ埋め込み型パッケージ構造の製造方法。   9. The chip embedded type according to claim 5, wherein at least one passive element is accommodated in the second support plate, and the circuit layer is electrically connected to the passive element. A manufacturing method of a package structure. 前記熱伝導ブロックは、金属、セラミックおよび無機高放熱材料のいずれか１つからなることを特徴とする請求項５〜９のいずれかに記載のチップ埋め込み型パッケージ構造の製造方法。   10. The method for manufacturing a chip-embedded package structure according to claim 5, wherein the heat conduction block is made of any one of metal, ceramic, and inorganic high heat dissipation material. 少なくとも１つの開口を有し、前記開口に熱伝導ブロックが形成されている支持板と、複数の電極パッドを有し、前記熱伝導ブロックに接着されている少なくとも１つの半導体チップと、
前記支持板および前記半導体チップに形成され、前記半導体チップの電極パッドが露出されるための貫通孔が設けられている誘電層と、
前記誘電層に形成され前記半導体チップの電極パッドに電気的に接続されている回路層とを備えていることを特徴とするチップ埋め込み型パッケージ構造。 A support plate having at least one opening and a heat conduction block formed in the opening; at least one semiconductor chip having a plurality of electrode pads and bonded to the heat conduction block;
A dielectric layer formed in the support plate and the semiconductor chip, and provided with a through hole for exposing an electrode pad of the semiconductor chip;
And a circuit layer formed on the dielectric layer and electrically connected to the electrode pad of the semiconductor chip. 前記回路層に回路ビルドアップ構造がさらに形成され、前記回路ビルドアップ構造が前記回路層に電気的に接続されていることを特徴とする請求項１１に記載のチップ埋め込み型パッケージ構造。   12. The embedded chip package structure according to claim 11, wherein a circuit buildup structure is further formed in the circuit layer, and the circuit buildup structure is electrically connected to the circuit layer. 前記熱伝導ブロックは、金属、セラミックおよび無機高放熱材料のいずれか１つからなることを特徴とする請求項１１または１２に記載のチップ埋め込み型パッケージ構造。   13. The chip embedded package structure according to claim 11, wherein the heat conduction block is made of any one of metal, ceramic, and inorganic high heat dissipation material. 前記支持板に少なくとも１つの受動素子が接着され、前記回路層が前記受動素子に電気的に接続されていることを特徴とする請求項１１〜１３のいずれかに記載のチップ埋め込み型パッケージ構造。   The embedded chip package structure according to claim 11, wherein at least one passive element is bonded to the support plate, and the circuit layer is electrically connected to the passive element. 少なくとも１つの開口を有し、前記開口に熱伝導ブロックが形成されている第１の支持板と、
前記第１の支持板に形成され、前記第１の支持板の開口に対応する位置に前記熱伝導ブロックを露出させるための開口が形成されている第２の支持板と、
前記第２の支持板の開口に収容され、前記熱伝導ブロックに接着され、電極パッドを有する半導体チップと、
前記第２の支持板および半導体チップに形成され、前記半導体チップの電極パッドが露出されている誘電層と、
前記誘電層に形成され、前記半導体チップの電極パッドに電気的に接続されている回路層と、を備えていることを特徴とするチップ埋め込み型パッケージ構造。 A first support plate having at least one opening, in which a heat conduction block is formed;
A second support plate formed in the first support plate, wherein an opening for exposing the heat conduction block is formed at a position corresponding to the opening of the first support plate;
A semiconductor chip housed in an opening of the second support plate, bonded to the heat conduction block, and having an electrode pad;
A dielectric layer formed on the second support plate and the semiconductor chip, the electrode pad of the semiconductor chip being exposed;
And a circuit layer formed on the dielectric layer and electrically connected to an electrode pad of the semiconductor chip. 前記回路層に回路ビルドアップ構造がさらに形成され、前記回路ビルドアップ構造が前記回路層に電気的に接続されていることを特徴とする請求項１５に記載のチップ埋め込み型パッケージ構造。   The embedded chip package structure according to claim 15, wherein a circuit buildup structure is further formed in the circuit layer, and the circuit buildup structure is electrically connected to the circuit layer. 前記熱伝導ブロックは、金属、セラミックおよび無機高放熱材料のいずれか１つからなることを特徴とする請求項１５または１６に記載のチップ埋め込み型パッケージ構造。   17. The chip embedded package structure according to claim 15, wherein the heat conduction block is made of any one of metal, ceramic, and inorganic high heat dissipation material. 少なくとも１つの受動素子が前記第２の支持板に収容され、前記回路層が前記受動素子に電気的に接続されていることを特徴とする請求項１５〜１７のいずれかに記載のチップ埋め込み型パッケージ構造。   The chip embedded type according to claim 15, wherein at least one passive element is accommodated in the second support plate, and the circuit layer is electrically connected to the passive element. Package structure.
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