JP2006253479A - Solid-state image element and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a thin, high-breakdown-voltage, solid-state imaging element which is stable and reliable even if the element, especially the width of an electrode is miniaturized, and can facilitate its manufacturing and has high reliability. <P>SOLUTION: A solid-state imaging element comprises a photoelectric converter formed on a semiconductor substrate and a charge transfer part for transferring electric charge generated by the photoelectric converter. A charge transfer electrode in the charge transfer part has a laminated layer structure; a first layer electrode made of a first layer conductive film, and a second layer electrode made of a second layer conductive film formed on the upper layer of the first layer electrode. A first gate oxide film formed under the first layer electrode has a stacked layer structure including a bottom oxide film made of an silicon oxide film formed on the semiconductor substrate, a silicon nitride film formed on the bottom oxide film, and a top oxide film made of a silicon oxide film formed on the silicon nitride film. A second gate oxide film formed under the second layer electrode is made of a silicon oxide film. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device and a method for manufacturing the same, and more particularly to a gate oxide film.

  In recent years, in solid-state imaging devices, the number of imaging pixels has increased to more than gigapixels, and miniaturization of electrode widths is also increasing. Under such circumstances, when patterning the gate oxide film formed under the charge transfer electrode, the margin tends to be small, and the demand for high accuracy tends to be extremely high.

  As shown in an example of a cross-sectional structure in FIG. 9, the conventional solid-state imaging device includes a photodiode portion, a charge transfer portion including a charge transfer device (CCD), and a charge transfer portion in a p-well 12 formed on the surface of the semiconductor substrate 1. The charge generated in the photodiode portion is guided to the transfer channel 14 formed of the n-type impurity region by applying a voltage to the charge transfer electrode of the charge transfer portion, and sequentially read out. Has been. That is, in the charge transfer unit, the charge generated in the photodiode unit is guided to the transfer channel 14, and a three-layer structure including a silicon oxide film (SiO) 2a, a silicon nitride film (SiN) 2b, and a silicon oxide film 2c is formed on the upper layer. In this structure, voltage is sequentially applied by applying a voltage to a gate electrode (charge transfer electrode) 3 serving as a charge transfer electrode and readout electrode (hereinafter referred to as readout electrode) formed through the gate oxide film 2. As described above, when light is incident on the photodiode portion, photoelectric conversion is performed in the n-type impurity region to generate a signal charge. When a read pulse is applied to the gate electrode 3 serving as a charge transfer electrode and a read electrode, the transfer channel is generated. Move to 14. Although details of the structure will be described later, in this structure, signal charges generated in the vicinity of the substrate surface are accelerated and read by an electric field generated by a read pulse.

  Conventionally, as described above, the gate oxide film of the solid-state imaging device has a so-called ONO structure in which a silicon nitride film that is a high breakdown voltage gate is sandwiched between silicon oxide films. In recent solid-state imaging devices that have been miniaturized, a gate oxide film having a thin and high withstand voltage is indispensable. The use of a gate oxide film having an ONO structure (hereinafter referred to as ONO film) It is an essential structure.

  By the way, in order to improve the initial characteristics, in order to suppress the dark current in the photodiode portion and to stabilize the characteristics, so-called hydrogen annealing, in which heat treatment is performed while supplying hydrogen sufficiently, stabilizes the initial characteristics of the device. This is an extremely important part for conversion (Patent Document 1). Therefore, on the photodiode, the upper two layers of the ONO film, that is, the silicon nitride film, are removed to form a single layer film to form a hydrogen passage. Then, after hydrogen treatment, a method of re-forming silicon nitride or the like as an antireflection film on the photodiode is employed.

  On the other hand, signal charges generated in the vicinity of the substrate surface are accelerated by an electric field generated by a read pulse, and when read, some become hot carriers and trapped in the silicon nitride film, causing a change in read gate voltage with time. .

  In particular, as device miniaturization progresses, the gate length becomes shorter, so the number of electron collisions tends to decrease and the frequency of hot carrier generation tends to increase, and the time-dependent change in the voltage applied to the read gate is becoming a serious problem. is there.

JP 2003-332556 A

As described above, in the conventional solid-state imaging device, the gate structure that can be thinned with high withstand voltage and the gate oxide film necessary for realizing the hydrogen annealing for improving the initial characteristics are re-formed. The two cannot be satisfied at the same time, such as a gate structure that is unnecessary and does not change with time due to hot carriers, which is a serious problem.
The interelectrode insulating film 4 formed between the first layer electrode and the second layer electrode is formed of a thermal oxide film. In this case, a film thickness of about 69 nm is required to obtain a sufficient breakdown voltage by thermal oxidation. However, when an attempt is made to form such a thick thermal oxide film, the extension of the diffusion length due to the heat applied during the film formation is a serious problem that prevents miniaturization of the element.
In addition, gate breakdown due to a so-called bamboo phenomenon in which a crack is formed at the crystal interface of the electrode due to heat treatment as a device is miniaturized and a bamboo-like crystal grows may be a problem.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a thin, high-voltage solid-state imaging device that is stable and reliable even when the device is miniaturized, in particular, the electrode width.

  It is another object of the present invention to provide a method for manufacturing a solid-state imaging device that is easy to manufacture and highly reliable.

  The solid-state imaging device of the present invention is a solid-state imaging device comprising a photoelectric conversion unit formed on a semiconductor substrate and a charge transfer unit that transfers charges generated by the photoelectric conversion unit, the charge transfer unit The charge transfer electrode is composed of a first layer electrode composed of a first layer conductive film and a second layer electrode composed of a second layer conductive film formed on the first layer electrode. The first gate oxide film formed under the first layer electrode is formed on the bottom oxide film made of a silicon oxide (SiO) film formed on the semiconductor substrate surface and on the bottom oxide film. A laminated structure (ONO) film including a silicon nitride (SiN) film and a top oxide film made of a silicon oxide (SiO) film formed on the silicon nitride film is formed under the second layer electrode. The second gate oxide film is a silicon oxide film Characterized in that it is made.

  With this configuration, the gate oxide film under the second layer electrode and the interelectrode insulating film formed between the first layer electrode and the second layer electrode are formed of a CVD oxide film, which is compared with thermal oxidation. Therefore, it is possible to provide a solid-state imaging device that can be formed at a low temperature and is highly miniaturized and highly reliable. In particular, by using a silicon oxide film formed by a high temperature CVD method called an HTO film, a dense silicon oxide film having a high withstand voltage can be formed. In the case where the charge is read out from the second layer electrode, no high voltage is applied to the first layer electrode. Therefore, there are few hot carrier problems even if the gate oxide film is composed of an ONO film. Therefore, it is desirable to have a structure in which charge is read from the second layer electrode.

In the solid-state imaging device of the present invention, the silicon oxide film is a CVD film.
With this configuration, as described above, it can be formed at a lower temperature than the thermal oxide film.

In the solid-state imaging device of the invention, the silicon oxide film is a laminated film of a thermal oxide film and a CVD film.
With this configuration, a dense thermal oxide film and a CVD film that can be formed at a lower temperature than the case of using the thermal oxidation method are used to reduce the thermal influence on the element while reducing the thermal effect on the device. Can be formed.

In addition, the solid-state imaging device of the present invention includes a solid-state imaging device including an impurity ion implantation region for potential adjustment on the surface of the substrate under the second layer electrode.
With this configuration, the difference in surface potential due to the difference in film quality and film thickness between the gate oxide film under the first layer electrode and the second layer electrode can be compensated by adjusting the impurity concentration on the surface of the semiconductor substrate. And a solid-state imaging device with uniform characteristics can be provided.

The solid-state imaging device of the present invention includes one in which the gate oxide film under the second layer electrode is formed in the same process as the gate oxide film in the peripheral circuit portion.
According to this configuration, the gate oxide film of the transistor in the peripheral circuit can be formed of the silicon oxide film only by changing the mask pattern without adding a process, and the influence of hot carriers can be prevented.

The solid-state imaging device of the present invention includes a solid-state imaging device that constitutes a single-layer electrode structure in which the first layer electrode and the second layer electrode are juxtaposed via an interelectrode insulating film.
According to this configuration, since the difference in the gate oxide film can be compensated by adjusting the surface potential, excellent characteristics can be obtained even with a single-layer electrode structure.

In the solid-state imaging device of the present invention, the second layer electrode is formed so as to run on the second layer electrode via an interelectrode insulating film and constitutes a two-layer electrode structure.
According to this configuration, the interelectrode insulating film between the first layer electrode and the second layer electrode is also formed of a CVD film having excellent film quality, thereby further improving the reliability.

  The method of the present invention is a method of manufacturing a solid-state imaging device in which a photoelectric conversion unit and a charge transfer unit that transfers charges generated by the photoelectric conversion unit are formed on a semiconductor substrate. A bottom oxide film made of a silicon oxide (SiO) film on a semiconductor substrate surface; a silicon nitride (SiN) film formed on the bottom oxide film; and a silicon oxide (SiO) film formed on the silicon nitride film Forming a laminated structure (ONO) film including a top oxide film comprising: forming a first layer conductive film; and patterning the first layer conductive film to form a first layer electrode Removing the silicon nitride film using the first layer electrode as a mask and patterning the first gate oxide film so as to remain only under the first layer electrode; and a second gate oxide film. Characterized in that it comprises a step of forming a step of forming a silicon oxide film by the CVD method, the second layer electrode consisting of a second layer conductive film over the silicon oxide.

  According to this configuration, the gate oxide film is removed up to the silicon nitride film using the first layer electrode as a mask, the CVD oxide film is formed around the first layer electrode, and the gate oxide of the interelectrode insulating film and the second layer electrode is formed. Since the film is formed, a highly accurate and reliable solid-state imaging device can be formed without increasing the number of steps. Here, it is desirable to use anisotropic etching for patterning the silicon nitride of the first gate oxide film. Thereby, it can comprise so that an edge may become perpendicular | vertical to the semiconductor substrate surface.

In addition, the method of the present invention includes a step of forming a thermal oxide film by thermally oxidizing the surface of the first layer electrode prior to the step of forming the silicon oxide film by a CVD method.
With this configuration, by forming the stacked film of the thermal oxide film and the CVD oxide film, it is possible to obtain a highly reliable and highly reliable film quality while shortening the time required for the film formation.

  In the method of the present invention, after the first layer electrode is formed, impurities are introduced into a region corresponding to the region below the second layer electrode, whereby the surface of the semiconductor substrate under the first gate oxide film and the second layer electrode are formed. Including an impurity introducing step of adjusting the impurity concentration on the surface of the semiconductor substrate so that the surface potential of the surface of the semiconductor substrate under the gate oxide film becomes equal.

  According to this configuration, it is possible to easily suppress variation in characteristics due to the difference in the gate oxide film by an impurity introduction process such as ion implantation.

  In the method of the present invention, in the step of forming the second layer electrode, after the second layer conductive film is formed, the second layer conductive film is flattened and aligned with the first layer electrode. And including.

  In the method of the present invention, the step of forming the second layer electrode includes a step of forming a second layer conductive film and then patterning the second layer conductive film.

  The method of the present invention includes one in which the gate electrode of the transistor constituting the peripheral circuit is composed of the second layer conductive film.

  According to this configuration, the gate oxide film can be formed in the same process as the silicon oxide under the second layer electrode, and hot carrier accumulation can be suppressed.

  This method also eliminates the need to form an opening in silicon nitride for forming a hydrogen passage during hydrogen annealing.

As described above, according to the solid-state imaging device of the present invention, the gate oxide film under the first layer electrode is an ONO film, and the gate oxide film under the second layer electrode is a silicon oxide film formed by a CVD method. By doing so, it is possible to form a solid-state imaging device having excellent characteristics even when miniaturization is achieved while reducing the thermal process while reducing the influence of hot carriers.
According to the method for manufacturing a solid-state imaging device of the present invention, the gate oxide film is removed up to the silicon nitride film using the first layer electrode as a mask, a CVD oxide film is formed around the first layer electrode, and an interelectrode insulating film is formed. In addition, since the gate oxide film of the second layer electrode is configured, it is possible to form a highly accurate and reliable solid-state imaging device without increasing the number of steps.

Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1 is a cross-sectional view showing a main part of a solid-state imaging device, FIG. 2 is a plan view, and FIG. 3 is a main part plan view of an imaging region. 1 is a cross-sectional view taken along line AA in FIG. 3 and a cross section taken along line BB in FIG. FIG. 3 is an enlarged view of the imaging region 100 of FIG. As shown in FIG. 1, in this solid-state imaging device, the charge transfer electrode of the charge transfer portion formed on the silicon substrate 1 is composed of a first layer electrode 3a and a second layer electrode 3b. The first gate oxide film 2 formed below 3a includes a bottom oxide film 2a made of a silicon oxide (SiO) film formed on the surface of the semiconductor substrate, and a silicon nitride (SiN) formed on the bottom oxide film. ) Film 2b and a laminated structure (ONO) film including a top oxide film 2c made of a silicon oxide (SiO) film formed on the silicon nitride film, and formed under the second layer electrode 3b. The second gate oxide film 4 is composed of a silicon oxide film. In addition, the structure which reads out an electric charge from the 2nd layer electrode 3b is taken. Here, the bottom oxide film 2a has a thickness of 25 nm, the silicon nitride film 2b has a thickness of 50 nm, and the top oxide film 2c has a thickness of 8 nm. The second gate oxide film 4 is composed of a thermal oxide film having a thickness of 20 nm and a silicon oxide film formed by a high temperature CVD method having a thickness of 30 nm.

  As shown in the schematic plan view of FIG. 2, the solid-state imaging device chip includes an imaging region 100 composed of a photodiode and a charge transfer unit on a semiconductor substrate, and a peripheral circuit unit such as an amplifier formed around the imaging region 100. 200, and a pad portion 300 as an external connection terminal is formed on the peripheral portion. It is an AA cross section of FIG. As shown in the figure, a plurality of photodiodes 30 are formed in the p-well 12 separated in the element isolation region 11, and a charge transfer unit 40 for transferring signal charges detected by the photodiodes is provided in the photodiode 30. It is formed so as to exhibit a meandering shape in between. Although not shown in FIG. 3, the charge transfer channel 14 through which the signal charge transferred by the charge transfer unit 40 moves has a meandering shape in a direction crossing the direction in which the charge transfer unit 40 extends. It is formed.

  Further, an overdrain buffer layer 13 made of a high-concentration p-type semiconductor layer is formed below the p-well 12 so that charges can be drawn out by applying a voltage. On the surface of the charge transfer portion 40, a first layer electrode 3a and a second layer electrode 3b are arranged via a gate oxide film 2 via an interelectrode insulating film 4 composed of a silicon oxide film 4a and an HTO film 4b. Yes. The photodiode 30 is formed of an n-type impurity region 31 that forms a pn junction with the p-well 12 and a high-concentration p-type impurity region as a surface potential adjustment layer 32 formed on the surface of the n-type impurity region 31. Has been.

  An antireflection film 6 made of a silicon nitride film having a thickness of 30 nm is formed on the first layer electrode 3a and the second layer electrode 3b with a silicon oxide film 5 interposed therebetween. The upper layer is a tungsten thin film having a thickness of 200 nm having an opening in the light receiving region of the photodiode 30 as a light shielding layer 7 through a titanium nitride layer (not shown) having a thickness of 50 nm formed by sputtering. Has been. Further, this upper layer is covered with a planarizing film 10 of a translucent film made of a silicon oxide film 9 and a BPSG film.

  As described above, the light shielding film 7 having an opening formed in a region corresponding to the photodiode 30 is provided above the solid-state imaging device, and the color filter 50 and the planarization are performed via the planarization film 10 made of a BPSG film. A film 70 and a microlens 60 are sequentially stacked.

  Next, the charge transfer electrode forming process in the manufacturing process of the solid-state imaging device will be described with reference to FIGS. 4 (a) to 4 (c) to 5 (a) to 5 (c). In this example, after ion implantation is performed to form an n-type impurity region 31 for forming a photodiode region, a p-type impurity diffusion region as a surface potential adjustment layer 32, and an n-type impurity region as a transfer channel 14, A gate oxide film and a gate electrode are formed. At this time, it is necessary to set the diffusion time on the assumption that the diffusion length is extended by heating in the subsequent process. In the following steps, the photodiode region and the transfer channel formed in the semiconductor substrate are omitted for simplification.

First, a 25 nm-thickness silicon oxide film 2a is formed by thermal oxidation in a p-well 12 formed on the surface of an n-type silicon substrate 1. Here, oxidation was performed by heating to 950 ° C. in an HCl / O ₂ = 1 slm / 10 slm atmosphere.

Thereafter, a silicon nitride film 2b having a thickness of 50 nm is formed on the bottom oxide film 2a by CVD. Here, the deposition conditions were set to 780 ° C. in an atmosphere of SiH ₂ Cl ₂ / NH ₃ = 0.09 slm / 0.9 slm (0.5 Torr).

Further, a silicon oxide film having a thickness of 8 nm is formed as a top oxide film 2c on the silicon nitride film 2b by a CVD method to form a gate oxide film having a three-layer structure (FIG. 4A). Here, the CVD conditions were set to 800 ° C. in a SiH ₄ / H ₂ O = 0.05 slm / 2.5 slm (1.2 Torr) atmosphere.

Subsequently, a doped amorphous silicon layer for forming the first layer electrode 3 a is formed on the gate oxide film 2. (FIG. 4B).
That is, a phosphorus-doped first layer doped film having a thickness of 0.3 to 0.25 μm is formed on the gate oxide film 2 by a low pressure CVD method using SiH ₄ added with PH ₃ and N ₂ as a reactive gas. An amorphous silicon film 3a is formed. The substrate temperature at this time shall be 600-700 degreeC.

  Subsequently, a resist R1 is applied to form a resist pattern for forming the first layer electrode (FIG. 4C).

Then, using the resist pattern R1 as a mask, the first layer doped amorphous silicon film is etched to form the first layer electrode 3a (FIG. 5A). At this time, the first layer doped amorphous silicon film 3a is selected by reactive ion etching using a mixed gas of HBr and O ₂ with the mask pattern as a mask and the silicon nitride film 2b of the gate oxide film 2 as an etching stopper. Then, the silicon nitride film 2b is removed by etching and the first electrode and peripheral circuit wiring are formed. Here, it is desirable to use an etching apparatus such as an ECR (Electron Cyclotron Resonance) system or an ICP (Inductively Coupled Plasma) system. The peripheral circuit wiring may be formed of a second layer doped amorphous silicon film. Here, when patterning the silicon nitride film 2b, it is desirable to use anisotropic etching so that the pattern edges are vertical.

  Then, an interelectrode insulating film 4 composed of a silicon oxide film 4a and an HTO film 4b and serving as a second gate oxide film is formed on the entire surface of the substrate including on the first layer electrode 3a by thermal oxidation. FIG. 5B). At this time, the silicon oxide film is formed in an oxygen atmosphere at 850 ° C. for 30 minutes, and the HTO film is formed by a CVD method at a substrate temperature of 850 ° C.

Then, a phosphorus-doped second layer dope having a film thickness of 0.3 to 0.25 μm is formed on the interelectrode insulating film 4 by a low pressure CVD method using SiH ₄ added with PH ₃ and N ₂ as a reactive gas. A triamorphous silicon film b is formed. The substrate temperature at this time shall be 600-700 degreeC.
Subsequently, the second layer doped amorphous silicon film 3b is patterned on the upper layer by photolithography to form a second layer electrode 3b (FIG. 5C).

  Then, after forming the insulating film 5 on the upper layer, a silicon nitride film is formed as the antireflection film 6 and patterned so as to cover the photodiode region. Further, a TEOS film 6S is formed, a tungsten film as a light shielding film 7 is formed through TiN (not shown) as an adhesive layer, and the pattern of the light shielding film 7 is patterned using a resist pattern as a mask.

  A 700 nm-thick BPSG film is formed on the light-shielding film 7 thus formed via the silicon oxide film 9, and then reflowed and planarized at 850 ° C. to form the planarizing film 10.

  Finally, the filter layer 50, the planarization layer 70, and the lens 60 are formed to form the solid-state imaging device shown in FIG.

  According to the solid-state imaging device thus formed, the gate oxide film 4 below the second layer electrode 3b and the interelectrode insulating film 4 formed between the first layer electrode 3a and the second layer electrode 3b. Is formed with a two-layer film of thermal oxide film and CVD oxide film, so it can be formed at a lower temperature (high temperature process can be completed in a short time) compared to the case where it is formed only by thermal oxidation. The extension of the diffusion length due to the above is also reduced, and it is possible to provide a solid-state imaging device with high reliability by miniaturization. In particular, by using a silicon oxide film formed by a high temperature CVD method called an HTO film, a dense silicon oxide film having a high withstand voltage can be formed. Further, the charge is read from the second layer electrode 3b. In this structure, since the first layer electrode a is not subjected to a high electric field, even if the gate oxide film is composed of an ONO film, hot carriers are used. There are few problems.

  Further, in the peripheral circuit, for example, the amplifier, as shown in the cross section of the main part in FIG. 6, the gate oxide film of the MOSFET constituting the amplifier is constituted by the second gate oxide film 4, and the gate electrode is formed from the second conductive layer. The second layer electrode is formed in the same process. For this reason, even when the peripheral circuit is miniaturized, the gate oxide film is not an ONO film and does not include a silicon nitride layer. Therefore, the influence of hot carriers is prevented, and a highly reliable solid-state imaging device is obtained. be able to.

  In the patterning of the ONO film, it is desirable to pattern silicon nitride using anisotropic etching. As a result, a pattern edge perpendicular to the substrate surface can be obtained, and a highly accurate and reliable solid-state imaging device can be obtained.

  In addition, since there is a region that is not covered with silicon nitride, a hydrogen passage for hydrogen annealing is also secured. In addition, it can be formed without any special process.

  Further, since the surface of the first layer electrode is formed without being thermally oxidized, a stringer that causes a problem in the generation of a whisker-like recrystallization region so-called gate bird's beak extending from the first layer electrode or patterning of the second layer electrode Is also suppressed, deterioration of the breakdown voltage can be prevented, and the yield is improved.

  In this step, since the silicon nitride of the ONO film in the photodiode region is also removed by etching, it is not necessary to pattern the silicon nitride of the ONO film in the photodiode region after forming the charge transfer electrode. This eliminates the need for silicon oxide for use as a stopper in the silicon nitride patterning step on the second layer electrode.

  Even when various plasma processes such as plasma CVD or plasma etching are used, since the silicon nitride of the ONO film is removed, the plasma charging effect can be suppressed and the reliability can be improved.

(Embodiment 2)
In the first embodiment, the substrate surfaces under the first layer electrode 3a and the second layer electrode 3b are configured in the same manner. However, as shown in FIGS. 7A to 7C, an ion implantation step is added, In order to compensate for the difference in surface potential due to the difference in the gate oxide film, ions may be selectively implanted into the region below the second layer electrode 3b to adjust the surface potential and make the characteristics uniform.

  In manufacturing, it is formed in the same manner as in the first embodiment, but after patterning the first layer electrode 3a, the surface potential difference due to the difference in the gate oxide film is compensated by ion implantation, and the first layer electrode 3a and the first layer electrode 3a are formed. An ion implantation region d is formed under the second layer electrode 3b so that the surface potential is equal under the two layer electrode 3b.

  According to the solid-state imaging device formed in this way, it is possible to provide a charge transfer unit with uniform characteristics. A highly accurate pattern can be obtained even when miniaturized, and the reliability of the charge transfer electrode can be improved.

  In the first embodiment, the case where the charge transfer electrode having the two-layer electrode structure is used is described. However, when the charge transfer electrode having the single-layer electrode structure is formed by the planarization process after forming the conductive film having the two-layer structure. Needless to say, this is also applicable.

(Embodiment 3)
In the first embodiment, as shown in FIGS. 5A to 5B, the second layer conductive film constituting the second layer electrode is formed by photolithography, but according to the present embodiment, As shown in FIGS. 8A to 8D, a second-layer conductive film for forming the second-layer electrode is deposited sufficiently thick, and is flattened by CMP to form the first-layer electrode 3a and the second-layer electrode. The layer electrode 3b may have a single layer electrode structure in which the layer electrode 3b is juxtaposed via the interelectrode insulating film 4.

Again, after patterning the first layer electrode 3a, the surface potential difference due to the difference in the gate oxide film is compensated by ion implantation so that the surface potential becomes equal between the first layer electrode 3a and the second layer electrode 3b. In addition, an ion implantation region d is formed under the second layer electrode 3b.
In this way, it is possible to provide a solid-state imaging device having charge transfer electrodes with uniform characteristics.

  As described above, according to the solid-state imaging device of the present invention, the pattern edge of the silicon nitride film can be patterned with high accuracy, and a fine and highly reliable electrode can be formed. It is effective for a solid-state imaging device having a charge transfer electrode, and an increase in the number of pixels can be expected.

Sectional drawing which shows the solid-state image sensor of Embodiment 1 of this invention The top view which shows the solid-state image sensor of Embodiment 1 of this invention 1 is a main part plan view showing a solid-state imaging device according to Embodiment 1 of the present invention; The figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. The figure which shows the manufacturing process of the solid-state image sensor of Embodiment 1 of this invention. The figure which shows the peripheral circuit part of the solid-state image sensor of Embodiment 1 of this invention. The figure which shows the manufacturing process of the solid-state image sensor of Embodiment 2 of this invention. The figure which shows the manufacturing process of the solid-state image sensor of Embodiment 3 of this invention. The figure which shows the solid-state image sensor of a prior art example

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2a Bottom oxide film 2b Silicon nitride film 2c Top oxide film 3 Gate electrode 4 Interelectrode insulating film 5 Insulating film 6 Antireflection film 7 Light shielding film

Claims (13)

A solid-state imaging device comprising a photoelectric conversion unit formed on a semiconductor substrate and a charge transfer unit that transfers charges generated by the photoelectric conversion unit,
The charge transfer electrode of the charge transfer portion is a first layer electrode formed of a first layer conductive film and a second layer formed of a second layer conductive film formed on the first layer electrode. Composed of electrodes,
The first gate oxide film formed under the first layer electrode is:
A bottom oxide film made of a silicon oxide (SiO) film formed on the surface of the semiconductor substrate, a silicon nitride (SiN) film formed on the bottom oxide film, and a silicon oxide (SiN) formed on the silicon nitride film ( A layered structure (ONO) film including a top oxide film made of (SiO) film,
A solid-state imaging device in which the second gate oxide film formed under the second layer electrode is composed of a silicon oxide film. The solid-state imaging device according to claim 1,
The solid-state imaging device, wherein the silicon oxide film is a CVD film. The solid-state imaging device according to claim 1,
The solid-state imaging device, wherein the silicon oxide film is a laminated film of a thermal oxide film and a CVD film. The solid-state imaging device according to claim 1,
A solid-state imaging device including an impurity ion implantation region for potential adjustment on a substrate surface under the second layer electrode. The solid-state imaging device according to claim 1,
The solid-state imaging device, wherein the gate oxide film under the second layer electrode is formed in the same process as the gate oxide film in the peripheral circuit portion. The solid-state imaging device according to claim 1,
The first layer electrode and the second layer electrode are solid-state imaging devices that constitute a single-layer electrode structure in which the first layer electrode and the second layer electrode are juxtaposed via an interelectrode insulating film. The solid-state imaging device according to claim 1,
The second-layer electrode is a solid-state imaging device that is formed so as to run on the second-layer electrode via an inter-electrode insulating film and constitutes a two-layer electrode structure. In a method for manufacturing a solid-state imaging device, on a semiconductor substrate, a photoelectric conversion unit and a charge transfer unit that transfers charges generated by the photoelectric conversion unit are formed.
The step of forming the charge transfer part comprises:
A bottom oxide film made of a silicon oxide (SiO) film on the surface of the semiconductor substrate, a silicon nitride (SiN) film formed on the bottom oxide film, and a silicon oxide (SiO) film formed on the silicon nitride film Forming a laminated structure (ONO) film including a top oxide film,
Forming a first layer conductive film;
Patterning the first layer conductive film to form a first layer electrode;
Removing the silicon nitride film using the first layer electrode as a mask and patterning the first gate oxide film so as to remain only under the first layer electrode;
Forming a silicon oxide film by a CVD method as a second gate oxide film;
Forming a second layer electrode made of a second layer conductive film on the silicon oxide. It is a manufacturing method of the solid-state image sensing device according to claim 8,
Prior to the step of forming the silicon oxide film by a CVD method, a method for manufacturing a solid-state imaging device including a step of forming a thermal oxide film by thermally oxidizing the surface of the first layer electrode. It is a manufacturing method of the solid-state image sensing device according to claim 8,
After forming the first layer electrode, impurities are introduced into a region corresponding to the region below the second layer electrode, so that the surface of the semiconductor substrate under the first gate oxide film and the region under the second gate oxide film are formed. A method for manufacturing a solid-state imaging device, comprising an impurity introduction step of adjusting an impurity concentration on the surface of the semiconductor substrate so that the surface potentials on the surface of the semiconductor substrate are equal. It is a manufacturing method of the solid-state image sensing device according to claim 10,
The step of forming the second layer electrode includes a planarization step of planarizing the second layer conductive film after forming the second layer conductive film and aligning the second layer conductive film with the first layer electrode. Production method. It is a manufacturing method of the solid-state image sensing device according to claim 8,
The step of forming the second layer electrode includes a step of patterning the second layer conductive film after forming the second layer conductive film. It is a manufacturing method of the solid-state image sensing device according to claim 8,
A method of manufacturing a solid-state imaging device in which a gate electrode of a transistor constituting a peripheral circuit is formed of a second layer conductive film.

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