JP2006245186A - Semiconductor device and its manufacturing process - Google Patents

Semiconductor device and its manufacturing process Download PDF

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Publication number
JP2006245186A
JP2006245186A JP2005057202A JP2005057202A JP2006245186A JP 2006245186 A JP2006245186 A JP 2006245186A JP 2005057202 A JP2005057202 A JP 2005057202A JP 2005057202 A JP2005057202 A JP 2005057202A JP 2006245186 A JP2006245186 A JP 2006245186A
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semiconductor device
solder
wiring pattern
electrode
conductive
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Tomohiko Uda
智彦 宇田
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Seiko Epson Corp
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Seiko Epson Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device, and a process for manufacturing it efficiently. <P>SOLUTION: The process for manufacturing a semiconductor device comprises a step for opposing the electrode 12 of a semiconductor chip 10 and a wiring pattern 22 each other through a solder 30 containing bismuth, and a step for forming a conductive portion 40 connecting the electrode 12 and the wiring pattern 22 electrically by thermally melting the solder 30 at a temperature between the melting point and 300°C and then hardening the solder. Content of bismuth in the solder 30 is 3-57%. In the step for forming the conductive portion 40, the solder 30 is heated at a temperature higher than the melting point for shorter than 10 sec. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

配線パターンと半導体チップの電極とを、はんだを利用して電気的に接続することが知られている。この場合、配線パターンと電極とを電気的に接続する導電部が形成されることが一般的である。はんだは、ビスマスを含有することで融点が下がることが知られているが、ビスマスを含有するはんだを利用すると導電部内にビスマスの偏析部が発生することがあった。信頼性の高い半導体装置を製造するためには、特に、導電部の中央部にビスマスの偏析部を形成しないことが重要である。   It is known that a wiring pattern and an electrode of a semiconductor chip are electrically connected using solder. In this case, a conductive portion that electrically connects the wiring pattern and the electrode is generally formed. It is known that the melting point of solder is lowered by containing bismuth, but when a solder containing bismuth is used, a segregation part of bismuth may be generated in the conductive part. In order to manufacture a highly reliable semiconductor device, it is particularly important not to form a bismuth segregated portion in the central portion of the conductive portion.

本発明の目的は、信頼性の高い半導体装置、及び、これを効率よく製造する方法を提供することにある。
特開２００１−３５９７８号公報 An object of the present invention is to provide a highly reliable semiconductor device and a method for efficiently manufacturing the same.
JP 2001-35978 A

（１）本発明に係る半導体装置の製造方法は、半導体チップの電極と配線パターンとを、ビスマスを含有するはんだを介して対向させること、及び、
前記はんだを、融点以上３００度未満の温度で加熱して溶融させ、その後硬化させて、前記電極と前記配線パターンとを電気的に接続する導電部を形成することを含み、
前記はんだのビスマス含有量は、３％よりも多く５７％未満であり、
前記導電部を形成する工程で、前記融点以上の温度で前記はんだを加熱する時間は１０秒未満である。本発明によると、融点の低いはんだを利用して半導体装置を製造することができる。そのため、半導体装置の製造効率を高めることができる。また、本発明によると、中央部を避けて側方部にビスマスの偏析部が配置された導電部を形成することができる。そのため、信頼性の高い半導体装置を製造することができる。
（２）この半導体装置の製造方法において、
前記はんだは前記配線パターンにめっきされていてもよい。
（３）この半導体装置において、
前記導電部を形成する工程で、前記はんだの溶融時間が１０秒未満になるように、前記はんだを加熱してもよい。
（４）本発明に係る半導体装置は、上記方法で製造されてなる。
（５）本発明に係る半導体装置は、配線パターンが形成された配線基板と、
複数の電極を有し、前記電極が前記配線パターンと対向するように前記配線基板に搭載された半導体チップと、
それぞれの前記電極と前記配線パターンとの間に配置されて両者を電気的に接続する導電部と、
を含み、
前記導電部は、前記配線パターンの上端面から前記電極の上端面に至るように形成された中央部と、前記中央部を囲む側方部とを含み、
前記導電部は、ビスマスの含有量が９０％を超えるビスマスの偏析部を有し、
前記偏析部は、前記導電部の前記中央部を避けて前記側方部に配置されてなる。本発明によると、応力に対する信頼性の高い半導体装置を提供することができる。
（６）この半導体装置において、
前記偏析部は、前記配線パターンとオーバーラップしないように配置されていてもよい。
（７）この半導体装置において、
前記電極は、パッドと、前記パッドに形成されたバンプとを含み、
前記偏析部は、前記バンプの先端面とオーバーラップしないように配置されていてもよい。
（８）この半導体装置において、
前記偏析部は、前記導電部の表面に露出するように配置されていてもよい。
（９）この半導体装置において、
前記偏析部は、前記導電部の表面から露出しないように配置されていてもよい。 (1) In the method for manufacturing a semiconductor device according to the present invention, the electrode of the semiconductor chip and the wiring pattern are opposed to each other through solder containing bismuth, and
The solder is melted by heating at a temperature not lower than 300 ° C. and less than 300 ° C. and then cured to form a conductive portion that electrically connects the electrode and the wiring pattern;
The solder has a bismuth content greater than 3% and less than 57%;
In the step of forming the conductive portion, the time for heating the solder at a temperature equal to or higher than the melting point is less than 10 seconds. According to the present invention, a semiconductor device can be manufactured using a solder having a low melting point. Therefore, the manufacturing efficiency of the semiconductor device can be increased. In addition, according to the present invention, it is possible to form a conductive portion in which a bismuth segregation portion is disposed on a side portion while avoiding the central portion. Therefore, a highly reliable semiconductor device can be manufactured.
(2) In this method of manufacturing a semiconductor device,
The solder may be plated on the wiring pattern.
(3) In this semiconductor device,
In the step of forming the conductive portion, the solder may be heated so that the melting time of the solder is less than 10 seconds.
(4) The semiconductor device according to the present invention is manufactured by the above method.
(5) A semiconductor device according to the present invention includes a wiring board on which a wiring pattern is formed,
A semiconductor chip having a plurality of electrodes, and mounted on the wiring board so that the electrodes face the wiring pattern;
A conductive portion disposed between each of the electrodes and the wiring pattern to electrically connect both;
Including
The conductive portion includes a central portion formed so as to reach the upper end surface of the electrode from the upper end surface of the wiring pattern, and a side portion surrounding the central portion,
The conductive part has a bismuth segregation part in which the bismuth content exceeds 90%,
The segregation part is arranged on the side part so as to avoid the central part of the conductive part. According to the present invention, a highly reliable semiconductor device against stress can be provided.
(6) In this semiconductor device,
The segregation part may be arranged so as not to overlap the wiring pattern.
(7) In this semiconductor device,
The electrode includes a pad and a bump formed on the pad,
The segregation part may be disposed so as not to overlap the tip surface of the bump.
(8) In this semiconductor device,
The segregation part may be arranged so as to be exposed on the surface of the conductive part.
(9) In this semiconductor device,
The segregation part may be arranged so as not to be exposed from the surface of the conductive part.

以下、本発明を適用した実施の形態について図面を参照して説明する。ただし、本発明は以下の実施の形態に限定されるものではない。   Embodiments to which the present invention is applied will be described below with reference to the drawings. However, the present invention is not limited to the following embodiments.

図１〜図３は、本発明を適用した実施の形態に係る半導体装置の製造方法について説明するための図である。   1 to 3 are diagrams for explaining a method of manufacturing a semiconductor device according to an embodiment to which the present invention is applied.

本実施の形態に係る半導体装置の製造方法は、半導体チップ１０を用意することを含んでいてもよい（図１及び図２、図４及び図５参照）。半導体チップ１０は、例えばシリコン基板であってもよい。半導体チップ１０は、集積回路１１を有していてもよい。集積回路１１の構成は特に限定されないが、例えば、トランジスタ等の能動素子や、抵抗、コイル、コンデンサ等の受動素子を含んでいてもよい。また、半導体チップ１０は複数の電極１２を有する。電極１２は、半導体チップ１０の内部と電気的に接続されていてもよい。電極１２は、集積回路１１と電気的に接続されていてもよい。あるいは、集積回路１１に電気的に接続されていない電極を含めて、電極１２と称してもよい。電極１２は、パッド１６とパッド１６上に形成されたバンプ１８とによって構成されていてもよい（図３参照）。パッド１６は、例えば、アルミニウム又は銅等の金属で薄く平らに形成されていてもよい。また、バンプ１８は、例えば金バンプであってもよい。電極１２が配置される領域や配列も特に限定されない。電極１２は、例えば、集積回路１１とオーバーラップする領域内に配置されていてもよい。半導体チップ１０は、パッシベーション膜を有してもよい（図示せず）。パッシベーション膜は、例えば、ＳｉＯ２、ＳｉＮ、ポリイミド樹脂等で形成されていてもよい。 The method for manufacturing a semiconductor device according to the present embodiment may include preparing a semiconductor chip 10 (see FIGS. 1, 2, 4, and 5). The semiconductor chip 10 may be a silicon substrate, for example. The semiconductor chip 10 may have an integrated circuit 11. The configuration of the integrated circuit 11 is not particularly limited. For example, the integrated circuit 11 may include an active element such as a transistor and a passive element such as a resistor, a coil, and a capacitor. Further, the semiconductor chip 10 has a plurality of electrodes 12. The electrode 12 may be electrically connected to the inside of the semiconductor chip 10. The electrode 12 may be electrically connected to the integrated circuit 11. Alternatively, an electrode that is not electrically connected to the integrated circuit 11 may be referred to as the electrode 12. The electrode 12 may be composed of a pad 16 and a bump 18 formed on the pad 16 (see FIG. 3). The pad 16 may be formed thin and flat with a metal such as aluminum or copper, for example. The bumps 18 may be gold bumps, for example. There is no particular limitation on the region and arrangement in which the electrodes 12 are arranged. For example, the electrode 12 may be disposed in a region overlapping the integrated circuit 11. The semiconductor chip 10 may have a passivation film (not shown). The passivation film may be formed of, for example, SiO 2 , SiN, polyimide resin, or the like.

本実施の形態に係る半導体装置の製造方法は、配線基板２０を用意することを含んでいてもよい（図１及び図２参照）。配線基板２０の材料や構造は特に限定されず、既に公知となっているいずれかの基板を利用してもよい。配線基板２０は、フレキシブル基板であってもよく、リジッド基板であってもよい。あるいは、配線基板２０は、テープ基板であってもよい。配線基板２０は、積層型の基板であってもよく、あるいは、単層の基板であってもよい。また、配線基板２０の外形も特に限定されるものではない。配線基板２０には配線パターン２２が形成されてなる。配線パターン２２は、配線基板２０の表面に設けられていてもよい。配線基板２０が多層基板である場合、配線パターン２２は、配線基板２０の層間に形成されていてもよい（図示せず）。配線パターン２２の構造や材料は、特に限定されず、既に公知となっているいずれかの配線を利用してもよい。例えば、配線パターン２２は、銅（Ｃｕ）、クローム（Ｃｒ）、チタン（Ｔｉ）、ニッケル（Ｎｉ）、チタンタングステン（Ｔｉ−Ｗ）、金（Ａｕ）、アルミニウム（Ａｌ）、ニッケルバナジウム（ＮｉＶ）、タングステン（Ｗ）のうちのいずれかを積層して、あるいはいずれかの一層で形成されていてもよい。配線基板２０は、図示しない保護膜をさらに有してもよい。保護膜は、配線パターン２２の一部を覆うように形成されていてもよい。   The manufacturing method of the semiconductor device according to the present embodiment may include preparing the wiring board 20 (see FIGS. 1 and 2). The material and structure of the wiring substrate 20 are not particularly limited, and any substrate that is already known may be used. The wiring board 20 may be a flexible board or a rigid board. Alternatively, the wiring substrate 20 may be a tape substrate. The wiring substrate 20 may be a laminated substrate or a single layer substrate. Further, the outer shape of the wiring board 20 is not particularly limited. A wiring pattern 22 is formed on the wiring substrate 20. The wiring pattern 22 may be provided on the surface of the wiring board 20. When the wiring board 20 is a multilayer board, the wiring pattern 22 may be formed between the layers of the wiring board 20 (not shown). The structure and material of the wiring pattern 22 are not particularly limited, and any known wiring may be used. For example, the wiring pattern 22 includes copper (Cu), chromium (Cr), titanium (Ti), nickel (Ni), titanium tungsten (Ti-W), gold (Au), aluminum (Al), and nickel vanadium (NiV). , Any one of tungsten (W) may be laminated or formed in any one layer. The wiring board 20 may further include a protective film (not shown). The protective film may be formed so as to cover a part of the wiring pattern 22.

本実施の形態に係る半導体装置の製造方法は、図１に示すように、半導体チップ１０の電極１２と配線パターン２２とを、ビスマスを含有するはんだ３０を介して対向させることを含む。はんだ３０は、例えば、配線パターン２２にめっきされていてもよい（図１参照）。あるいは、はんだ３０は、ペースト状で配線パターン２２上に設けられていてもよい。あるいは、はんだ３０は、電極１２に設けられていてもよい。はんだにビスマスを添加すると、はんだの融点が下がることが知られている。そのため、ビスマスを含有するはんだ３０を利用することで、後述する導電部４０を形成する工程を低温で行うことができる。これにより、効率よく半導体装置を製造することが可能になる。また、半導体チップ１０や配線基板２０に損傷を与えることなく、半導体装置を製造することが可能になる。なお、本実施の形態に係る半導体装置の製造方法では、はんだ３０のビスマス含有量は、３％よりも多く５７％未満である。これにより、ビスマスを含有しない場合と比較してはんだ３０の融点を顕著に下げることができる。   As shown in FIG. 1, the method for manufacturing a semiconductor device according to the present embodiment includes causing the electrodes 12 of the semiconductor chip 10 and the wiring pattern 22 to face each other via a solder 30 containing bismuth. For example, the solder 30 may be plated on the wiring pattern 22 (see FIG. 1). Alternatively, the solder 30 may be provided on the wiring pattern 22 in a paste form. Alternatively, the solder 30 may be provided on the electrode 12. It is known that the melting point of solder decreases when bismuth is added to the solder. Therefore, by using the solder 30 containing bismuth, the step of forming the conductive portion 40 described later can be performed at a low temperature. Thereby, it becomes possible to manufacture a semiconductor device efficiently. In addition, the semiconductor device can be manufactured without damaging the semiconductor chip 10 and the wiring substrate 20. In the semiconductor device manufacturing method according to the present embodiment, the bismuth content of the solder 30 is more than 3% and less than 57%. Thereby, compared with the case where bismuth is not contained, the melting point of the solder 30 can be lowered significantly.

本実施の形態に係る半導体装置の製造方法は、図２及び図３に示すように、電極１２と配線パターン２２とを電気的に接続する導電部４０を形成することを含む。なお、図３は図２の一部拡大図であり、電極１２と配線パターン２２との接合状態を説明するための図である。本工程では、はんだ３０を、融点以上３００度未満の温度で加熱して溶融させ、その後硬化させて導電部４０を形成する。また、本工程では、融点以上の温度ではんだ３０を加熱する時間は１０秒未満である。本工程では、例えばボンディングツールによって、はんだ３０を融点以上の温度で加熱してもよい。すなわち、ヒーターを内蔵するボンディングツールで半導体チップ１０を保持して、半導体チップ１０をはんだ３０の融点以上の温度に加熱し、電極１２と配線パターン２２（はんだ３０）とを接触させて、はんだ３０を加熱してもよい。このとき、電極１２がはんだ３０と接触してから、ボンディングツールが半導体チップ１０から離れるまでの時間を、１０秒未満としてもよい。ただし、はんだ３０を加熱する方法はこれに限られるものではない。例えば、誘導電流を利用して、はんだ３０を加熱してもよい。なお、本実施の形態に係る半導体装置の製造方法では、はんだ３０の溶融時間が１０秒未満になるように、はんだ３０を加熱してもよい。   As shown in FIGS. 2 and 3, the method for manufacturing a semiconductor device according to the present embodiment includes forming a conductive portion 40 that electrically connects the electrode 12 and the wiring pattern 22. FIG. 3 is a partially enlarged view of FIG. 2 and is a diagram for explaining a bonding state between the electrode 12 and the wiring pattern 22. In this step, the solder 30 is heated and melted at a temperature not lower than the melting point and lower than 300 degrees, and then cured to form the conductive portion 40. In this step, the time for heating the solder 30 at a temperature equal to or higher than the melting point is less than 10 seconds. In this step, the solder 30 may be heated at a temperature equal to or higher than the melting point, for example, with a bonding tool. That is, the semiconductor chip 10 is held by a bonding tool incorporating a heater, the semiconductor chip 10 is heated to a temperature equal to or higher than the melting point of the solder 30, and the electrode 12 and the wiring pattern 22 (solder 30) are brought into contact with each other. May be heated. At this time, the time from the contact of the electrode 12 with the solder 30 to the separation of the bonding tool from the semiconductor chip 10 may be less than 10 seconds. However, the method of heating the solder 30 is not limited to this. For example, the solder 30 may be heated using an induced current. In the method of manufacturing a semiconductor device according to the present embodiment, the solder 30 may be heated so that the melting time of the solder 30 is less than 10 seconds.

導電部４０は、図３に示すように、中央部４２と側方部４４とを含む。中央部４２は、配線パターン２２の上端面から電極１２の上端面に至るように形成されてなる。そして、側方部４４は、中央部４２を囲むように形成されてなる。また、導電部４０は、ビスマスの含有量が９０％を超えるビスマスの偏析部４５を有する。偏析部４５は、中央部４２を避けて側方部４４に配置されてなる。先に説明した条件ではんだ３０を加熱することで、上記の構造をなす導電部４０を形成することができる。なお、偏析部４５は、配線パターン２２とオーバーラップしないように配置されていてもよい。また、電極１２がバンプ１８を有する場合、偏析部４５は、バンプ１８の先端面とオーバーラップしないように配置されていてもよい。また、偏析部４５は、導電部４０の表面に露出するように配置されていてもよい。あるいは、偏析部４５は、導電部４０の表面から露出しないように配置されていてもよい。はんだ３０に含まれるビスマスの量や、加熱温度、ボンディング時の加圧力等を調整して、偏析部４５の位置や大きさを制御してもよい。   As shown in FIG. 3, the conductive portion 40 includes a central portion 42 and side portions 44. The central portion 42 is formed so as to extend from the upper end surface of the wiring pattern 22 to the upper end surface of the electrode 12. The side portion 44 is formed so as to surround the central portion 42. The conductive portion 40 has a bismuth segregation portion 45 in which the bismuth content exceeds 90%. The segregation part 45 is arranged on the side part 44 while avoiding the central part 42. By heating the solder 30 under the conditions described above, the conductive portion 40 having the above structure can be formed. In addition, the segregation part 45 may be arrange | positioned so that it may not overlap with the wiring pattern 22. FIG. Further, when the electrode 12 has the bump 18, the segregating portion 45 may be arranged so as not to overlap the tip surface of the bump 18. Moreover, the segregation part 45 may be arrange | positioned so that the surface of the electroconductive part 40 may be exposed. Or the segregation part 45 may be arrange | positioned so that it may not be exposed from the surface of the electroconductive part 40. FIG. The position and size of the segregating portion 45 may be controlled by adjusting the amount of bismuth contained in the solder 30, the heating temperature, the pressure applied during bonding, and the like.

先に説明したように、はんだ３０はビスマスを含有する。通常、ビスマスを含有するはんだを利用して導電部を形成すると、導電部内にビスマスの偏析部が発生することがあった。ところで、半導体チップ１０実装後の温度の低下や、半導体装置が置かれる環境の変化によって、導電部には力が加えられることがある。このときに、導電部の内部に偏析部が形成されていると、偏析部を起点にして導電部の破壊が生じる恐れがあった。特に、偏析部が導電部の中央部に配置されると、導電部の破壊が生じやすくなる。すなわち、中央部から導電部の破壊が発生し、これが側方部に至り、導電部が完全に破断することがあった。このことから、導電部の破壊を防止するためには、中央部内に破壊の起点となりうる部分を配置しないことが重要である。   As explained above, the solder 30 contains bismuth. Usually, when a conductive part is formed using solder containing bismuth, a segregated part of bismuth may occur in the conductive part. By the way, a force may be applied to the conductive portion due to a decrease in temperature after mounting the semiconductor chip 10 or a change in environment where the semiconductor device is placed. At this time, if the segregation part is formed inside the conductive part, the conductive part may be broken starting from the segregation part. In particular, when the segregation part is disposed at the central part of the conductive part, the conductive part is easily broken. That is, the conductive part is broken from the central part, which reaches the side part, and the conductive part may be completely broken. For this reason, in order to prevent destruction of the conductive portion, it is important not to arrange a portion that can be a starting point of destruction in the central portion.

ところで、導電部４０では、図３に示すように、ビスマスの偏析部４５は、中央部４２を避けて側方部４４に形成される。言い換えると、中央部４２内には偏析部４５が配置されない。すなわち、先に説明した方法によれば、中央部４２内に破壊の起点となりうる部分が配置されないように、導電部４０を形成することができる。そのため、破壊されにくい構造をなす導電部４０を形成することができる。すなわち、応力に対する信頼性の高い半導体装置を製造することができる。また、中央部４２は、配線パターン２２の上端面から電極１２の上端面に至るように形成されていることから、中央部４２によって配線パターンと電極１２との電気的な導通を確保することができる。このことから、電気的な信頼性の高い半導体装置を製造することができる。   Incidentally, in the conductive portion 40, as shown in FIG. 3, the bismuth segregated portion 45 is formed in the side portion 44 while avoiding the central portion 42. In other words, the segregation part 45 is not arranged in the central part 42. That is, according to the method described above, the conductive portion 40 can be formed so that a portion that can be a starting point of destruction is not disposed in the central portion 42. Therefore, it is possible to form the conductive portion 40 having a structure that is not easily destroyed. That is, a semiconductor device with high reliability against stress can be manufactured. Further, since the central portion 42 is formed so as to extend from the upper end surface of the wiring pattern 22 to the upper end surface of the electrode 12, the central portion 42 can ensure electrical conduction between the wiring pattern and the electrode 12. it can. Thus, a semiconductor device with high electrical reliability can be manufactured.

そして、配線基板２０を切断する工程や、検査工程などを経て、図４に示す半導体装置１を製造してもよい。半導体装置１は、配線パターン２２が形成された配線基板２０を有する。半導体装置１は、複数の電極１２を有する半導体チップ１０を有する。半導体チップ１０は、電極１２が配線パターン２２と対向するように配線基板２０に搭載されてなる。半導体装置１は、それぞれの電極１２と配線パターン２２との間に配置されて両者を電気的に接続する導電部４０を有する。導電部４０は、配線パターン２２の上端面から電極１２の上端面に至るように形成された中央部４２と、中央部４２を囲む側方部４４とを含む。導電部４０は、ビスマスの含有量が９０％を超えるビスマスの偏析部４５を有する。偏析部４５は、導電部４０の中央部４２を避けて側方部４４に配置されてなる。先に説明したように、導電部４０は破壊しにくい構造をなすため、信頼性の高い半導体装置を提供することができる。   And you may manufacture the semiconductor device 1 shown in FIG. 4 through the process of cut | disconnecting the wiring board 20, an inspection process, etc. FIG. The semiconductor device 1 has a wiring substrate 20 on which a wiring pattern 22 is formed. The semiconductor device 1 includes a semiconductor chip 10 having a plurality of electrodes 12. The semiconductor chip 10 is mounted on the wiring board 20 so that the electrode 12 faces the wiring pattern 22. The semiconductor device 1 includes a conductive portion 40 that is disposed between each electrode 12 and the wiring pattern 22 and electrically connects the two. The conductive portion 40 includes a central portion 42 formed so as to reach the upper end surface of the electrode 12 from the upper end surface of the wiring pattern 22 and a side portion 44 surrounding the central portion 42. The conductive portion 40 has a bismuth segregation portion 45 in which the bismuth content exceeds 90%. The segregation part 45 is arranged on the side part 44 avoiding the central part 42 of the conductive part 40. As described above, since the conductive portion 40 has a structure that is not easily broken, a highly reliable semiconductor device can be provided.

そして、図５には、半導体装置１を有する電子モジュール１０００を示す。電子モジュール１０００は、表示デバイスであってもよい。表示デバイスは、例えば液晶表示デバイスやＥＬ（Electrical Luminescence）表示デバイスであってもよい。さらに、半導体装置１を有する電子機器として、図６にノート型パーソナルコンピュータ２０００を、図７に携帯電話３０００を、それぞれ示す。   FIG. 5 shows an electronic module 1000 having the semiconductor device 1. The electronic module 1000 may be a display device. The display device may be, for example, a liquid crystal display device or an EL (Electrical Luminescence) display device. Further, as an electronic device having the semiconductor device 1, FIG. 6 shows a notebook personal computer 2000 and FIG. 7 shows a mobile phone 3000.

なお、本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。例えば、本発明は、実施の形態で説明した構成と実質的に同一の構成（例えば、機能、方法及び結果が同一の構成、あるいは目的及び効果が同一の構成）を含む。また、本発明は、実施の形態で説明した構成の本質的でない部分を置き換えた構成を含む。また、本発明は、実施の形態で説明した構成と同一の作用効果を奏する構成又は同一の目的を達成することができる構成を含む。また、本発明は、実施の形態で説明した構成に公知技術を付加した構成を含む。   In addition, this invention is not limited to embodiment mentioned above, A various deformation | transformation is possible. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that achieves the same effect as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

図１は、本発明を適用した実施の形態に係る半導体装置の製造方法を説明するための図である。FIG. 1 is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment to which the present invention is applied. 図２は、本発明を適用した実施の形態に係る半導体装置の製造方法を説明するための図である。FIG. 2 is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment to which the present invention is applied. 図３は、本発明を適用した実施の形態に係る半導体装置の製造方法を説明するための図である。FIG. 3 is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment to which the present invention is applied. 図４は、本発明を適用した実施の形態に係る方法で製造した半導体装置を示す図である。FIG. 4 is a diagram showing a semiconductor device manufactured by a method according to an embodiment to which the present invention is applied. 図５本発明を適用した実施の形態に係る半導体装置を有する電子デバイスを示す図である。5 is a diagram showing an electronic device having a semiconductor device according to an embodiment to which the present invention is applied. 図６は、本発明を適用した実施の形態に係る半導体装置を有する電子機器を示す図である。FIG. 6 is a diagram showing an electronic apparatus having a semiconductor device according to an embodiment to which the present invention is applied. 図７は、本発明を適用した実施の形態に係る半導体装置を有する電子機器を示す図である。FIG. 7 is a diagram showing an electronic apparatus having a semiconductor device according to an embodiment to which the present invention is applied.

符号の説明Explanation of symbols

１０…半導体チップ、 １２…電極、 １６…パッド、 １８…バンプ、 ２０…配線基板、 ２２…配線パターン、 ３０…はんだ、 ４０…導電部、 ４２…中央部、 ４４…側方部、 ４５…偏析部   DESCRIPTION OF SYMBOLS 10 ... Semiconductor chip, 12 ... Electrode, 16 ... Pad, 18 ... Bump, 20 ... Wiring board, 22 ... Wiring pattern, 30 ... Solder, 40 ... Conductive part, 42 ... Center part, 44 ... Side part, 45 ... Segregation Part

Claims (9)

半導体チップの電極と配線パターンとを、ビスマスを含有するはんだを介して対向させること、及び、
前記はんだを、融点以上３００度未満の温度で加熱して溶融させ、その後硬化させて、前記電極と前記配線パターンとを電気的に接続する導電部を形成することを含み、
前記はんだのビスマス含有量は、３％よりも多く５７％未満であり、
前記導電部を形成する工程で、前記融点以上の温度で前記はんだを加熱する時間は１０秒未満である半導体装置の製造方法。 Opposing the semiconductor chip electrode and the wiring pattern through solder containing bismuth, and
The solder is melted by heating at a temperature not lower than 300 ° C. and less than 300 ° C. and then cured to form a conductive portion that electrically connects the electrode and the wiring pattern;
The solder has a bismuth content greater than 3% and less than 57%;
The method of manufacturing a semiconductor device, wherein in the step of forming the conductive portion, the time for heating the solder at a temperature equal to or higher than the melting point is less than 10 seconds. 請求項１記載の半導体装置の製造方法において、
前記はんだは前記配線パターンにめっきされてなる半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the solder is plated on the wiring pattern. 請求項１又は請求項２記載の半導体装置において、
前記導電部を形成する工程で、前記はんだの溶融時間が１０秒未満になるように、前記はんだを加熱する半導体装置の製造方法。 The semiconductor device according to claim 1 or 2,
A method of manufacturing a semiconductor device, wherein the solder is heated so that the melting time of the solder is less than 10 seconds in the step of forming the conductive portion. 請求項１から請求項３のいずれかに記載の方法で製造された半導体装置。   A semiconductor device manufactured by the method according to claim 1. 配線パターンが形成された配線基板と、
複数の電極を有し、前記電極が前記配線パターンと対向するように前記配線基板に搭載された半導体チップと、
それぞれの前記電極と前記配線パターンとの間に配置されて両者を電気的に接続する導電部と、
を含み、
前記導電部は、前記配線パターンの上端面から前記電極の上端面に至るように形成された中央部と、前記中央部を囲む側方部とを含み、
前記導電部は、ビスマスの含有量が９０％を超えるビスマスの偏析部を有し、
前記偏析部は、前記導電部の前記中央部を避けて前記側方部に配置されてなる半導体装置。 A wiring board on which a wiring pattern is formed;
A semiconductor chip having a plurality of electrodes, and mounted on the wiring board so that the electrodes face the wiring pattern;
A conductive portion disposed between each of the electrodes and the wiring pattern to electrically connect both;
Including
The conductive portion includes a central portion formed so as to reach the upper end surface of the electrode from the upper end surface of the wiring pattern, and a side portion surrounding the central portion,
The conductive part has a bismuth segregation part in which the bismuth content exceeds 90%,
The segregation part is a semiconductor device arranged at the side part so as to avoid the central part of the conductive part. 請求項５記載の半導体装置において、
前記偏析部は、前記配線パターンとオーバーラップしないように配置されてなる半導体装置。 The semiconductor device according to claim 5.
The segregation part is a semiconductor device arranged so as not to overlap the wiring pattern. 請求項５又は請求項６記載の半導体装置において、
前記電極は、パッドと、前記パッドに形成されたバンプとを含み、
前記偏析部は、前記バンプの先端面とオーバーラップしないように配置されてなる半導体装置。 The semiconductor device according to claim 5 or 6,
The electrode includes a pad and a bump formed on the pad,
The segregation part is a semiconductor device that is arranged so as not to overlap the tip surface of the bump. 請求項５から請求項７のいずれかに記載の半導体装置において、
前記偏析部は、前記導電部の表面に露出するように配置されてなる半導体装置。 The semiconductor device according to any one of claims 5 to 7,
The segregation part is a semiconductor device arranged to be exposed on the surface of the conductive part. 請求項５から請求項７のいずれかに記載の半導体装置において、
前記偏析部は、前記導電部の表面から露出しないように配置されてなる半導体装置。 The semiconductor device according to any one of claims 5 to 7,
The segregation part is a semiconductor device arranged so as not to be exposed from the surface of the conductive part.
JP2005057202A 2005-03-02 2005-03-02 Semiconductor device and its manufacturing process Withdrawn JP2006245186A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110074020A1 (en) * 2009-09-30 2011-03-31 Fujitsu Limited Semiconductor device and method for mounting semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110074020A1 (en) * 2009-09-30 2011-03-31 Fujitsu Limited Semiconductor device and method for mounting semiconductor device

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