JP2006229153A - Nitride semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nitride semiconductor device which uses an adjustment layer enabling fine adjustments of a warp of a wafer without the need for limits on a material, and reduces an uneven joint caused by a warp of a wafer with a support substrate. <P>SOLUTION: The nitride semiconductor device is manufactured by a step of forming at least one or more nitride semiconductor device layers 3 on a growth substrate 1, a step of joining one principle surface of the support substrate 10 on the nitride semiconductor device layer 3, and a step of removing the growth substrate 1 from the joined nitride semiconductor device layer 3 and support substrate 10. The nitride semiconductor device includes an adjustment layer 11, which is made of a material having a different thermal expansion coefficient from that of the support substrate 10, on the other principle surface of the substrate 10. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a nitride semiconductor device and a nitride semiconductor device.

  In recent years, nitride compound semiconductors such as GaN, InN, and AlN have been actively used as materials for electronic devices such as light emitting elements such as blue and green light emitting diodes (LEDs) and blue-violet semiconductor lasers, and high-speed transistors that can operate at high temperatures. It is used. Since this nitride-based semiconductor is generally difficult to produce a bulk single crystal, it is formed on a heterogeneous substrate (growth substrate) such as sapphire or SiC using a hetero-epitaxial growth method.

  However, since sapphire is an insulator, it is necessary to form p and n electrodes on the same surface of the semiconductor layer, so that the number of elements that can be taken from a wafer with the same diameter is small, and the effective light emitting area in the same element area is further reduced. There was a problem. The sapphire substrate has a thermal conductivity of 42 W / m · k, which is lower than the thermal conductivity of GaN, 130 W / m · k. For this reason, the nitride semiconductor element formed on the sapphire substrate has a problem in heat dissipation performance.

  Therefore, a method of removing the sapphire substrate from the nitride-based semiconductor element layer by etching, polishing, laser irradiation (for example, refer to Non-Patent Document 1) or the like is used. Generally, the thickness of the nitride-based semiconductor element layer is used. Is very thin, from several μm to several tens of μm, so that cracks and cracks are likely to occur when the substrate is removed or in subsequent processes. Therefore, it is necessary to join the support substrate to the surface of the nitride-based semiconductor element layer in advance by thermocompression bonding or the like.

  However, as shown in FIG. 14A, when the nitride-based semiconductor element layer 503 on the sapphire substrate 501 and the support substrate 510 are bonded via the fusion layer 509, the surface of the semiconductor element layer is nitrided. The sapphire substrate 501 is warped due to a large difference in thermal expansion coefficient between the physical semiconductor element layer 503 and the sapphire substrate 501. 14B, when the nitride-based semiconductor element layer 503 and the support substrate 510 are bonded, the area where the nitride-based semiconductor element layer 503 and the support substrate 510 are in contact with each other in the substrate plane. Limited.

  Therefore, it is very difficult to obtain a bond with good adhesion over the entire surface of the substrate, and there is a region in the wafer surface that is partially insufficiently bonded to the support substrate, and in this region, a sapphire substrate There is a problem in that cracks and cracks are likely to occur in the semiconductor element layer when removing.

Therefore, a nitride-based semiconductor element is disclosed in which a back surface layer having a thermal expansion coefficient smaller than that of the growth substrate is provided on the back surface side of the growth substrate, thereby suppressing warpage of the growth substrate (for example, Patent Documents). 1).
Physica Satus Solidi (a) 159, 1997, p.R3 JP 2000-22283 A

  However, since the nitride semiconductor device described in Patent Document 1 described above includes a back surface layer on the back surface of a growth substrate such as a sapphire substrate, the back surface layer has a nitride semiconductor device layer on the growth substrate. When forming, it will be exposed to severe conditions, such as high temperature or the atmosphere of highly reactive raw material gas. For this reason, the back surface layer needs to be made of a material that can withstand severe conditions, and there is a limitation in the selectivity of the material. Also, when forming a nitride-based semiconductor element layer, due to the influence of the back surface layer, heating of the growth substrate is likely to be non-uniform in the plane, so that the element characteristics of the grown nitride-based semiconductor element layer are surface. There is a problem in that it is likely to be non-uniform or the reproducibility is lowered. Furthermore, since the back surface layer has already been formed when forming the nitride-based semiconductor element layer, it is difficult to finely adjust the warpage after forming the nitride-based semiconductor element layer.

  Therefore, in view of the above-mentioned problems, the present invention uses an adjustment layer that can finely adjust the warpage of the wafer without requiring material limitations, and performs non-uniform bonding with the support substrate due to the warpage of the wafer. An object of the present invention is to provide a nitride semiconductor device manufacturing method and a nitride semiconductor device that can be reduced.

  In order to achieve the above object, the first feature of the present invention is that (a) a step of forming at least one nitride-based semiconductor element layer on the first substrate, and (b) a second substrate. Forming an adjustment layer made of a material having a coefficient of thermal expansion different from that of the second substrate on one main surface of the second substrate; and (c) forming the adjustment layer on the other side of the second substrate on the nitride-based semiconductor element layer. A method of manufacturing a nitride-based semiconductor device, comprising: a step of bonding the surfaces; and (d) a step of removing the first substrate from the bonded nitride-based semiconductor device layer and the second substrate. To do.

  According to the method for manufacturing a nitride-based semiconductor element according to the first feature, the adjustment layer is formed on the back surface side of the second substrate (support substrate), so that it is non-uniform with the support substrate due to the warpage of the wafer. Bonding can be reduced. For this reason, the generation of cracks in the nitride-based semiconductor element layer in the removal of the first substrate (growth substrate) can be suppressed over the entire wafer surface. Further, by reducing the warpage of the second substrate (support substrate), it is possible to make the process (electrode formation, polishing, etc.) of the element layer after removing the substrate uniform, and elements can be obtained from the wafer with a high yield. Further, since the adjustment layer is not provided on the back surface of the first substrate (growth substrate), the element characteristics in the surface can be made uniform, and a nitride-based semiconductor element having good element characteristics can be obtained. It can be obtained with good reproducibility. Furthermore, since the adjustment layer is formed on the back surface side of the second substrate (support substrate), the adjustment layer is not exposed to harsh conditions and does not require material limitations. Further, since the second substrate (supporting substrate) on which the adjustment layer is formed is bonded after the formation of the nitride-based semiconductor element layer, the warpage of the wafer can be finely adjusted.

  In the method for manufacturing a nitride-based semiconductor element according to the first feature, the nitride-based semiconductor element layer formed on the first substrate has a property of being convexly curved toward the supporting substrate to be bonded. The adjustment layer is preferably made of a material having a smaller thermal expansion coefficient than that of the second substrate.

  According to this method for manufacturing a nitride-based semiconductor element, since the adjustment layer is made of a material having a smaller thermal expansion coefficient than that of the second substrate, the second substrate has a property of being concavely curved toward the nitride-based semiconductor element layer side. Can have. For this reason, the second substrate and the nitride-based semiconductor element layer can be uniformly bonded.

  Furthermore, it is preferable that the second substrate used in the above-described method for manufacturing a nitride-based semiconductor element has a composite of a metal and an oxide of the metal as a main component, and the adjustment layer is a Si layer.

  Further, in the method for manufacturing a nitride-based semiconductor element according to the first feature, when the nitride-based semiconductor element layer formed on the first substrate has a property of being concavely curved toward the supporting substrate to be joined, The adjustment layer is preferably made of a material having a larger thermal expansion coefficient than that of the second substrate.

  According to this method for manufacturing a nitride-based semiconductor element, since the adjustment layer is made of a material having a thermal expansion coefficient larger than that of the second substrate, the second substrate is curved in a convex shape toward the nitride-based semiconductor element layer side. Can have. For this reason, the second substrate and the nitride-based semiconductor element layer can be uniformly bonded.

  Furthermore, it is preferable that the second substrate used in the above-described method for manufacturing a nitride-based semiconductor element has a composite of a metal and an oxide of the metal as a main component, and the adjustment layer is a layer made of metal.

  The second feature of the present invention is that a step of forming at least one nitride-based semiconductor element layer on the first substrate and one main layer of the second substrate on the nitride-based semiconductor element layer are provided. A nitride-based semiconductor device manufactured by a step of bonding surfaces, and a step of removing the first substrate from the bonded nitride-based semiconductor device layer and the second substrate, (a) a second The gist is that the nitride-based semiconductor element includes an adjustment layer made of a material having a different thermal expansion coefficient from that of the second substrate on the other main surface of the substrate.

  According to the nitride semiconductor device according to the second feature, by forming the adjustment layer on the back surface side of the second substrate (support substrate), non-uniform bonding with the support substrate due to warpage of the wafer is reduced. can do. For this reason, the generation of cracks in the nitride-based semiconductor element layer in the removal of the first substrate (growth substrate) can be suppressed over the entire wafer surface. Further, by reducing the warpage of the second substrate (support substrate), it is possible to make the process (electrode formation, polishing, etc.) of the element layer after removing the substrate uniform, and elements can be obtained from the wafer with a high yield. Furthermore, since the adjustment layer is formed on the back surface side of the second substrate (support substrate), the adjustment layer is not exposed to harsh conditions and does not require material limitations. Further, since the second substrate (supporting substrate) on which the adjustment layer is formed is bonded after the formation of the nitride-based semiconductor element layer, the warpage of the wafer can be finely adjusted.

  According to the present invention, a nitride-based semiconductor device that uses an adjustment layer that can finely adjust the warpage of the wafer without requiring material limitations and reduces non-uniform bonding with the support substrate due to the warpage of the wafer. And a nitride-based semiconductor device can be provided.

  Next, first to fourth embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and ratios of dimensions and the like are different from actual ones. Accordingly, specific dimensions and the like should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  First, the outline of the first to fourth embodiments of the present invention will be described. In the first to fourth embodiments, as shown in FIG. 1A, the adjustment layer 11 made of a material having a coefficient of thermal expansion different from that of the support substrate 10 is formed on one main surface of the support substrate 10. To do. Then, the nitride-based semiconductor element layer 3 on the growth substrate 1 and the support substrate 10 are bonded via the fusion layer 9. In the conventional method, during cooling after bonding, as shown in FIG. 14B, warpage due to a difference in thermal expansion coefficient between the support substrate 510 and the fusion layer 503 occurs, and pressure is applied within the substrate surface. However, in the present invention, as shown in FIG. 1B, the support substrate 10 on which the adjustment layer 11 is formed is bonded to suppress the occurrence of warpage in the wafer surface. be able to.

(First embodiment)
2 and 3 are cross-sectional views for explaining the method for manufacturing the nitride-based light-emitting diode device according to the first embodiment. In the first embodiment, a case will be described in which a nitride-based semiconductor element layer formed on a sapphire substrate has a property of curving convexly toward the supporting substrate to be bonded. In the first embodiment, by forming an adjustment layer made of a material having a smaller thermal expansion coefficient than that of the support substrate, the support substrate can have a property of being concavely curved toward the nitride-based semiconductor element layer side.

  First, as shown in FIG. 2A, a buffer layer 102, an underlayer 113, an n-type contact layer 103, and an n-type cladding layer 104 are formed on a sapphire substrate 101 by using a MOCVD (Metal Organic Chemical Vapor Deposition) method. Then, the active layer 105, the p-type cap layer 106, the p-type cladding layer 107, and the p-type contact layer 108 are sequentially grown, and then the p-side electrode is formed by vacuum deposition.

Specifically, with the sapphire substrate 101 held at a temperature of about 400 to 700 ° C., a source gas composed of NH ₃ and TMGa (trimethylgallium) is used to form about 0001 on the sapphire substrate 101. A buffer layer 102 made of undoped non-single crystal GaN having a thickness of 10 to 50 nm is grown.

Next, with the sapphire substrate 101 held at a growth temperature of about 1000 to 1200 ° C. (for example, 1150 ° C.), a thickness of about 3 μm is formed on the buffer layer 102 using a source gas composed of NH ₃ and TMGa. An underlying layer 113 made of undoped single crystal GaN is grown.

Next, in a state where the sapphire substrate 101 is maintained at a growth temperature of about 1000 to 1200 ° C. (for example, 1150 ° C.), a base layer is formed using a source gas composed of NH ₃ and TMGa and a dopant gas composed of SiH _4. An n-type contact layer 103 made of single-crystal GaN doped with Si having a thickness of about 0.5 μm is grown on 113.

Next, with the sapphire substrate 101 held at a growth temperature of about 1000 to 1200 ° C. (for example, 1150 ° C.), a source gas composed of NH ₃ , TMGa and TMAl (trimethylaluminum), and a dopant gas composed of SiH ₄ Is used to grow an n-type cladding layer 104 made of single crystal Al _0.1 Ga _0.9 N doped with Si having a thickness of about 0.15 μm on the n-type contact layer 103.

Next, in a state where the sapphire substrate 101 is maintained at a growth temperature of about 700 to 1000 ° C. (for example, 850 ° C.), a source gas made of NH ₃ , TMGa and TMIn (trimethylindium) is used to form the n-type cladding layer 104. On top, a barrier layer made of undoped single crystal GaN having a thickness of about 10 nm and a well layer made of undoped single crystal Ga _0.9 In _0.1 N having a thickness of about 5 nm are alternately grown. As a result, an active layer 105 having an MQW structure having four barrier layers and three well layers is grown.

Next, in a state where the sapphire substrate 101 is held at a growth temperature of about 700 to 1000 ° C. (for example, 850 ° C.), a source gas composed of NH ₃ , TMGa and TMAl and a dopant gas composed of CP ₂ Mg are used. Then, a p-type cap layer 106 made of single crystal p-type Al _0.2 Ga _0.8 N doped with Mg having a thickness of about 10 nm is grown on the active layer 105.

Next, in a state where the sapphire substrate 101 is held at a growth temperature of about 1000 to 1200 ° C. (for example, 1150 ° C.), a source gas composed of NH ₃ , TMGa and TMAl and a dopant gas composed of CP ₂ Mg are used. Then, a p-type cladding layer 107 made of single crystal Al _0.1 Ga _0.9 N doped with Mg having a thickness of about 0.1 μm is grown on the p-type cap layer 106.

Next, in a state where the sapphire substrate 101 is held at a growth temperature of about 700 to 1000 ° C. (for example, 850 ° C.), a source gas composed of NH ₃ , TMGa and TMAl and a dopant gas composed of CP ₂ Mg are used. A p-type contact layer 108 made of single crystal Ga _0.95 In _0.05 N doped with Mg having a thickness of about 5 nm is grown on the p-type cladding layer 107.

  Next, the p-type cap layer 106, the p-type cladding layer 107, and the p-type contact layer 108 are converted to p-type by performing heat treatment or electron beam treatment. In this manner, the buffer layer 102, the base layer 113, the n-type contact layer 103, the n-type cladding layer 104, the active layer 105, the p-type cap layer 106, the p-type cladding layer 107, and the p-type contact layer 108 are configured. A nitride-based semiconductor element layer is formed.

  Thereafter, a reflective p-side electrode composed of an Ag layer having a thickness of about 200 nm, a Pt layer having a thickness of about 200 nm, and an Au layer having a thickness of about 500 nm is sequentially formed by a vacuum deposition method.

  Here, due to the difference in thermal expansion coefficient between the sapphire substrate 101 and the nitride-based semiconductor element layer, the nitride-based semiconductor element layer is curved in a convex shape toward the supporting substrate to be bonded. This amount of bending is a difference of about 50 μm between the central portion and the end portion of a 2-inch φ size wafer at room temperature.

On the other hand, as shown in FIG. 2 (b), it is made of a composite material of Cu and Cu ₂ O (for example, a composite material having a content of Cu: 50% by weight and Cu ₂ O: 50% by weight), and is about 200 μm. An adjustment layer 111 made of a Si layer having a thickness of about 5 μm is formed on one main surface of the support substrate 110 having a thickness of about 5 μm by a vacuum deposition method through an adhesive layer made of a Ti layer having a thickness of about 10 nm. To do. The adjustment layer 111 is made of a material having a smaller thermal expansion coefficient than the support substrate 110. Note that the adhesive layer made of the Ti layer has a thermal expansion coefficient comparable to that of the support substrate 110 made of a composite material of Cu and Cu ₂ O, and therefore does not correspond to the adjustment layer 111 here. Further, a fusion layer 109 made of an Au layer having a thickness of about 500 nm is sequentially formed on the other main surface of the support substrate 110 by a vacuum deposition method through an adhesive layer made of a Ti layer having a thickness of about 10 nm. To do.

Here, the thermal expansion coefficients of the support substrate 110 made of the composite material having the contents of Cu: 50 wt% and Cu ₂ O: 50 wt% and the adjustment layer 111 made of the Si layer are about 10 ×, respectively. 10 ⁻⁶ / K and about 4 × 10 ⁻⁶ / K, and the support substrate 110 is concavely curved toward the nitride-based semiconductor element layer to be bonded. This amount of bending is a difference of about 50 μm between the central portion and the end portion of a 2-inch φ size wafer at room temperature. Since the thickness of the fusion layer 109 is about 500 nm, which is extremely smaller than the thickness of the adjustment layer (5 μm), the influence on the curvature of the support substrate 110 can be ignored.

  If necessary, the support substrate 110 after the formation of the adjustment layer 111 may be annealed.

  Next, as shown in FIG. 2C, the p-side electrode on the nitride-based semiconductor element layer and the fusion layer 109 made of the Au layer on the support substrate 110 are made of Au—Sn, Pd—Sn, In -Thermocompression bonding is performed via solder made of Pd or the like or conductive paste made of Ag. For example, in the case of joining via a solder made of Au—Sn (Au: 80 wt%, Sn: 20 wt%), the support substrate 110 is heated to about 300 ° C., and several 10 under a pressure of about 0.3 Pa. Thermocompression bonding is performed by holding for a minute.

  Next, as shown in FIG. 3A, the sapphire substrate 101 is removed from the semiconductor element layer by melting the sapphire substrate 101 and the semiconductor element layer near the nitride-based semiconductor element layer interface.

Specifically, first, a third harmonic (wavelength: about 355 nm) or a fourth harmonic (wavelength: about 266 nm) or a KrF excimer laser of Nd: YAG (or Nd: YVO4, etc.) laser light from a sapphire substrate. By irradiating light (wavelength: about 248 nm) or the like with an energy density of about 200 to 1000 mJ / cm ² , the laser light is absorbed by the GaN layer near the sapphire / GaN interface, thereby converting GaN into Ga and N ₂ . Decompose. By heating this to about 40 ° C., the decomposed Ga becomes a molten state, so that the sapphire substrate 101 is separated from the nitride-based semiconductor element layer. The adhered Ga can be removed with an aqueous hydrochloric acid solution. Thereafter, the n-type contact layer 103 is exposed by polishing or etching.

  Next, as shown in FIG. 3B, a light-transmitting property comprising a Ti layer having a thickness of about 1 nm and an Al layer having a thickness of about 5 nm on the n-type contact layer 103 using a vacuum deposition method. The n-side electrode 112 is formed.

  Next, as shown in FIG. 3C, element isolation is performed by dicing, laser scribing, or selective etching of the support substrate 110. Thus, the nitride semiconductor device according to the first embodiment is formed.

  According to the method for manufacturing a nitride semiconductor device and the nitride semiconductor device according to the first embodiment, by forming the adjustment layer 111 on the back surface side of the support substrate 110, the nitride system caused by the warpage of the wafer. Non-uniform bonding between the semiconductor element layer and the support substrate 110 can be reduced. For this reason, generation | occurrence | production of the crack of the nitride type semiconductor element layer in the removal of the sapphire substrate 101 can be suppressed on the whole wafer surface. Further, by reducing the warpage of the support substrate 110, it is possible to make the process (electrode formation, polishing, etc.) of the element layer after removing the substrate uniform, and an element can be obtained from the wafer with a high yield.

  Further, according to the nitride semiconductor device manufacturing method and the nitride semiconductor device according to the first embodiment, since there is no adjustment layer on the back surface of the growth substrate (sapphire substrate 101), The element characteristics can be made uniform, and a nitride semiconductor element having good element characteristics can be obtained with good reproducibility.

  In addition, since the adjustment layer 111 is formed on the back surface side of the support substrate 110, the adjustment layer 111 is not exposed to harsh conditions and does not require material limitations. In addition, since the support substrate 110 on which the adjustment layer 111 is formed is bonded after the nitride-based semiconductor element layer is formed, the wafer warpage can be finely adjusted.

  In the first embodiment, it is preferable to anneal the support substrate 110 after the adjustment layer 111 is formed. Thereby, since the adhesiveness of the adjustment layer 111 and the support substrate 110 can be improved, peeling at the same interface can be suppressed when a relatively large curvature is required. Further, the amount of bending can be adjusted again depending on the temperature of the annealing treatment.

In addition, the adjustment layer 111 can be removed after the support substrate 110 is bonded to the nitride-based semiconductor element layer. Therefore, even if SiO ₂ or the like is used as the material of the adjustment layer 111, the conductivity and heat dissipation are not deteriorated by removing the adjustment layer 111. Similarly, when Si or GaAs or the like is used as the support substrate 110 and its cleavage is to be used, even if a metal having malleability and viscosity is used as the material of the adjustment layer 111, the adjustment layer 111 is removed. , Cleavage can be ensured.

  Further, since the adjustment layer 111 is formed on the surface of the support substrate 110 opposite to the bonding surface with the nitride-based semiconductor element layer, the adhesion between the support substrate 110 and the nitride-based semiconductor element layer is deteriorated. There is no need to consider.

  In the first embodiment, since the adjustment layer 111 is made of a material having a smaller thermal expansion coefficient than that of the support substrate 110, the support substrate 110 has a property of being concavely curved toward the nitride-based semiconductor element layer side. it can. For this reason, uniform joining of the support substrate 110 and the nitride-based semiconductor element layer is possible. As such an example, the support substrate 110 is preferably composed mainly of a composite of a metal and an oxide of the metal, and the adjustment layer 111 is preferably a Si layer.

  In the first embodiment, the support substrate 110 is preferably conductive, more preferably a metal or a metal composite. Since the metal or the metal composite has not only good conductivity but also excellent thermal conductivity, the heat dissipation of the nitride-based semiconductor element can be improved.

(Second Embodiment)
4 and 5 are cross-sectional views for explaining a method for manufacturing a nitride-based light-emitting diode element according to the second embodiment. In the second embodiment, a case will be described in which the nitride-based semiconductor element layer formed on the Si substrate has a property of curving concavely toward the supporting substrate to be bonded. In the second embodiment, by forming the adjustment layer made of a material having a larger thermal expansion coefficient than that of the support substrate, the support substrate can have a property of being curved in a convex shape toward the nitride-based semiconductor element layer side.

  First, as shown in FIG. 4A, a buffer layer 202, a base layer 213, an n-type contact layer 203, an n-type cladding layer 204, an active layer 205, a p-type layer are formed on an Si substrate 201 by using the MOCVD method. A cap layer 206, a p-type cladding layer 207, and a p-type contact layer 208 are sequentially grown, and then a p-side electrode is formed by vacuum deposition.

Specifically, with the Si substrate 201 held at a temperature of about 1000 to 1200 ° C. (for example, 1150 ° C.), using a source gas composed of NH ₃ and TMGa, on the (111) surface of the Si substrate, A buffer layer 202 made of an AlN / GaN multilayer film in which about 50 pairs of Al layers having a thickness of about 5 nm and GaN layers having a thickness of about 20 nm are alternately stacked is grown.

  Next, as in the first embodiment, the base layer 213, the n-type contact layer 203, the n-type cladding layer 204, the active layer 205, the p-type cap layer 206, the p-type cladding layer 207, and the p-type contact layer 208 are used. A nitride-based semiconductor element layer constituted by is formed. Thereafter, similarly to the first embodiment, the p-side electrode is formed by a vacuum deposition method.

  Here, due to the difference in thermal expansion coefficient between the Si substrate 201 and the nitride semiconductor element layer described above, the nitride semiconductor element layer is concavely curved toward the supporting substrate to be joined. The amount of bending is about 50-100 μm at the center and the edge of a 5 inch φ wafer at room temperature.

On the other hand, as shown in FIG. 4 (b), it is made of a composite material of Cu and Cu ₂ O (for example, a composite material having a Cu: 50 wt% content ratio and Cu ₂ O: 50 wt% content), and is about 200 μm. An adjustment layer 211 made of a Cu layer having a thickness of about 5 μm is formed on one main surface of the support substrate 210 having a thickness of about 5 μm by a vacuum deposition method through an adhesive layer made of a Ti layer having a thickness of about 10 nm. To do. The adjustment layer 211 is made of a material having a thermal expansion coefficient larger than that of the support substrate 210. Note that the adhesive layer made of the Ti layer has a thermal expansion coefficient comparable to that of the support substrate 210 made of a composite material of Cu and Cu ₂ O, and therefore does not correspond to the adjustment layer 211 here. Further, a fusion layer 209 made of an Au layer having a thickness of about 500 nm is sequentially formed on the other main surface of the support substrate 210 by a vacuum vapor deposition method through an adhesive layer made of a Ti layer having a thickness of about 10 nm. To do.

Here, the thermal expansion coefficients of the support substrate 210 made of the composite material having the content ratio of Cu: 50% by weight and Cu ₂ O: 50% by weight and the adjustment layer 211 made of the Cu layer are about 10 ×, respectively. 10 ⁻⁶ / K and about 17 × 10 ⁻⁶ / K, and the support substrate 210 is concavely curved toward the nitride-based semiconductor element layer to be bonded. The amount of bending is about 50 to 100 μm at the center and the edge of a 5 inch φ wafer at room temperature.

  If necessary, the support substrate 210 after the formation of the adjustment layer 211 may be annealed.

  Next, as shown in FIG. 4C, the p-side electrode on the nitride-based semiconductor element layer and the fusion layer 209 on the support substrate 210 are made of Au—Sn, Pd—Sn, In—Pd, or the like. Then, thermocompression bonding is performed through a solder or a conductive paste made of Ag. For example, in the case of joining via a solder composed of Au—Sn (Au: 80 wt%, Sn: 20 wt%), the support substrate 210 is heated to about 300 ° C., and several 10 under a pressure of about 0.3 Pa. Thermocompression bonding is performed by holding for a minute.

  Next, as shown in FIG. 5A, the Si substrate 201 is removed from the nitride-based semiconductor element layer by wet etching using a hydrofluoric acid-based aqueous solution. Thereafter, the n-type contact layer 203 is exposed by polishing or etching.

  Next, as shown in FIG. 5B, a translucent n-side electrode 212 is formed as in the first embodiment.

  Next, as shown in FIG. 5C, element isolation is performed as in the first embodiment. In this way, the nitride semiconductor device according to the second embodiment is formed.

  According to the method for manufacturing a nitride semiconductor device and the nitride semiconductor device according to the second embodiment, since the adjustment layer 211 is made of a material having a thermal expansion coefficient larger than that of the support substrate 210, the support substrate 210 is made of nitride. It can have the property of curving convexly toward the system semiconductor element layer side. For this reason, uniform joining of the support substrate 210 and the nitride-based semiconductor element layer is possible. As such an example, it is preferable that the support substrate 210 has a composite of a metal and an oxide of the metal as a main component, and the adjustment layer 211 is a metal layer.

(Third embodiment)
6 to 9 are views for explaining a method of manufacturing a nitride semiconductor laser according to the third embodiment. In the third embodiment, a case will be described in which a nitride-based semiconductor element layer formed on a sapphire substrate has a property of curving convexly toward the supporting substrate to be bonded. In the third embodiment, by forming an adjustment layer made of a material having a smaller thermal expansion coefficient than that of the support substrate, the support substrate can have a property of being concavely curved toward the nitride-based semiconductor element layer side.

  First, as shown in FIG. 6A, a buffer layer 302, a base layer 313, an n-type contact layer 303, and an n-type cladding layer 304 are formed on a sapphire substrate 301 by using a MOCVD (Metal Organic Chemical Vapor Deposition) method. Then, the n-type light guide layer 314, the active layer 305, the p-type carrier block layer 315, the p-type light guide layer 319, the p-type cladding layer 307, and the p-type contact layer 308 are sequentially grown. Thereafter, a ridge portion, an electrode block layer, a p-side electrode, and a p-side pad electrode are formed.

  Specifically, as in the first embodiment, the buffer layer 302, the base layer 313, and the n-type contact layer 303 are grown on the sapphire substrate 301.

Next, with the sapphire substrate 301 held at a growth temperature of about 1000 to 1200 ° C. (for example, 1150 ° C.), a source gas composed of NH ₃ , TMGa and TMAl (trimethylaluminum), a dopant gas composed of SiH ₄ , Is used to grow an n-type cladding layer 304 made of single crystal Al _0.07 Ga _0.93 N doped with Si having a thickness of about 1.0 μm on the n-type contact layer 303.

Next, in a state where the sapphire substrate 301 is held at a growth temperature of about 700 to 1000 ° C. (for example, 850 ° C.), a source gas composed of NH ₃ and TMGa and a dopant gas composed of SiH ₄ are used to form an n-type. An n-type light guide layer 314 made of single-crystal GaN doped with Si having a thickness of about 0.1 μm is grown on the cladding layer 304.

Next, in a state where the sapphire substrate 301 is held at a growth temperature of about 700 to 1000 ° C. (for example, 850 ° C.), a source gas composed of NH ₃ , TMGa, and TMIn is used on the n-type light guide layer 314. Barrier layers made of undoped single crystal Ga _0.95 In _0.05 N having a thickness of about 20 nm and well layers made of undoped single crystal Ga _0.85 In _0.15 N having a thickness of about 3.5 nm are alternately grown. . As a result, an active layer 305 having an MQW structure having four barrier layers and three well layers is grown.

Next, in a state where the sapphire substrate 301 is held at a growth temperature of about 700 to 1000 ° C. (for example, 850 ° C.), a source gas composed of NH ₃ , TMGa and TMAl and a dopant gas composed of CP ₂ Mg are used. Then, a p-type carrier block layer 315 made of single-crystal p-type Al _0.25 Ga _0.75 N doped with Mg having a thickness of about 20 nm is grown on the active layer 305.

Next, in a state where the sapphire substrate 301 is held at a growth temperature of about 1000 to 1200 ° C. (for example, 1150 ° C.), a source gas composed of NH ₃ and TMGa and a dopant gas composed of CP ₂ Mg are used to form p. A p-type light guide layer 319 made of single-crystal GaN doped with Mg and having a thickness of about 0.1 μm is grown on the type carrier block layer 315.

Next, in a state where the sapphire substrate 301 is maintained at a growth temperature of about 1000 to 1200 ° C. (for example, 1150 ° C.), a source gas composed of NH ₃ , TMGa and TMAl and a dopant gas composed of CP ₂ Mg are used. Then, a p-type cladding layer 307 made of Mg-doped single crystal Al _0.07 Ga _0.93 N having a thickness of about 0.5 μm is grown on the p-type light guide layer 319.

Next, in a state where the sapphire substrate 301 is held at a growth temperature of about 700 to 1000 ° C. (for example, 850 ° C.), a source gas composed of NH ₃ , TMGa and TMAl and a dopant gas composed of CP ₂ Mg are used. Then, a p-type contact layer 308 made of single crystal Ga _0.99 In _0.01 N doped with Mg having a thickness of about 3 nm is grown on the p-type cladding layer 307.

  Next, the p-type carrier block layer 315, the p-type light guide layer 319, the p-type clad layer 307, and the p-type contact layer 308 are made p-type by performing heat treatment or electron beam treatment. In this manner, the buffer layer 302, the base layer 313, the n-type contact layer 303, the n-type cladding layer 304, the n-type light guide layer 314, the active layer 305, the p-type carrier block layer 315, the p-type light guide layer 319, A nitride-based semiconductor element layer constituted by the p-type cladding layer 307 and the p-type contact layer 308 is formed.

  Thereafter, predetermined regions of the p-type cladding layer 307 and the p-type contact layer 308 are removed by using a photolithography technique and reactive ion etching with a chlorine-based gas, thereby having a width of about 1.5 μm. , A ridge portion 317 composed of a stripe-shaped convex portion extending in the (1-100) direction is formed. At this time, the etching depth is controlled so that the thickness of the flat portion other than the convex portion of the p-type cladding layer 307 is about 0.05 μm.

Next, after forming a SiO ₂ film having a thickness of about 0.2 μm so as to cover the entire surface using a plasma CVD method, using a photolithography technique and reactive ion etching with CF ₄ gas, by removing a portion located on Jo surface of the p-type contact layer 308 of SiO ₂ layer, forming a current blocking layer made of SiO ₂ layer.

  Next, a p-type layer comprising a Pt layer having a thickness of about 1 nm, a Pd layer having a thickness of about 100 nm, and a Ni layer having a thickness of about 240 nm on the exposed surface of the p-type contact layer 308. Ohmic electrodes are formed in stripes. Further, on the surface of the current blocking layer, a Ti layer having a thickness of about 100 nm, a Pt layer having a thickness of about 150 nm, and an Au layer having a thickness of about 3 μm are formed so as to cover the p-side ohmic electrode. The p-side pad electrode 316 is sequentially formed by a vacuum deposition method.

  Here, due to the difference in thermal expansion coefficient between the sapphire substrate 301 and the nitride-based semiconductor element layer described above, the nitride-based semiconductor element layer is curved in a convex shape toward the supporting substrate to be bonded.

On the other hand, as shown in FIG. 6B, as in the first embodiment, a composite material of Cu and Cu ₂ O (for example, Cu: 50 wt%, Cu ₂ O: 50 wt% content rate) A Si layer having a thickness of about 5 μm on one main surface of a support substrate 310 having a thickness of about 200 μm via an adhesive layer made of a Ti layer having a thickness of about 10 nm. The adjustment layer 311 to be formed is formed by a vacuum deposition method. The adjustment layer 311 is made of a material having a smaller thermal expansion coefficient than the support substrate 310. Note that the adhesive layer made of the Ti layer has a thermal expansion coefficient comparable to that of the support substrate 310 made of a composite material of Cu and Cu ₂ O, and therefore does not correspond to the adjustment layer 311 here. Further, a fusion layer 309 made of an Au layer having a thickness of about 500 nm is sequentially formed on the other main surface of the support substrate 310 by a vacuum deposition method through an adhesive layer made of a Ti layer having a thickness of about 10 nm. To do.

Here, the thermal expansion coefficients of the support substrate 310 made of the composite material having the contents of Cu: 50 wt% and Cu ₂ O: 50 wt% described above and the adjustment layer 311 made of the Si layer are about 10 ×, respectively. 10 ⁻⁶ / K and about 4 × 10 ⁻⁶ / K, and the support substrate 110 is concavely curved toward the nitride-based semiconductor element layer to be bonded.

  If necessary, the support substrate 310 after the formation of the adjustment layer 311 may be annealed.

  Next, as shown in FIG. 6C, as in the first embodiment, the p-side pad electrode 316 on the nitride-based semiconductor element layer and the fusion layer 309 on the support substrate 310 are heated. Crimp.

  Next, as in the first embodiment, the sapphire substrate 301 is removed from the nitride-based semiconductor element layer by absorbing Nd: YAG laser light or the like in the GaN layer near the sapphire / GaN interface. Thereafter, the adhered Ga is removed with a hydrochloric acid aqueous solution, and the n-type contact layer 303 is exposed by polishing or etching.

  Next, as shown in FIGS. 7A and 7B, an Al layer having a thickness of about 6 nm and a thickness of about 10 nm are formed in a predetermined region on the n-type contact layer 303 by using a vacuum deposition method. An n-side ohmic electrode composed of a Ni layer having a thickness of about 100 nm and an Au layer having a thickness of about 100 nm is formed. Then, an n-side pad electrode 320 made of an Ni layer having a thickness of about 10 nm and an Au layer having a thickness of about 700 nm is formed on the n-side ohmic electrode.

  Next, as shown in FIGS. 8A and 8B, a predetermined region other than the n-side pad electrode 320 is etched by reactive ion etching using a chlorine-based gas until the support substrate 310 is reached. Thus, the laser resonator end face 318 composed of the (1-100) plane orthogonal to the ridge stripe and the (-1100) plane is formed.

  Next, as shown in FIGS. 9A and 9B, element isolation is performed by dicing, laser scribing, or selective etching of the support substrate 310. In this manner, the nitride semiconductor laser according to the third embodiment is formed.

  According to the method for manufacturing a nitride semiconductor device and the nitride semiconductor device according to the third embodiment, since the adjustment layer 311 is made of a material having a smaller thermal expansion coefficient than that of the support substrate 310, the support substrate 310 is made of nitride. It can have the property of curving concavely toward the semiconductor element layer side. For this reason, uniform joining of the support substrate 310 and the nitride-based semiconductor element layer is possible. As such an example, it is preferable that the support substrate 310 includes a composite of a metal and an oxide of the metal as a main component, and the adjustment layer 311 is a Si layer.

(Fourth embodiment)
10 to 13 are views for explaining a method of manufacturing the nitride semiconductor laser according to the fourth embodiment. In the fourth embodiment, a case will be described in which the nitride-based semiconductor element layer formed on the Si substrate has a property of curving concavely toward the supporting substrate to be bonded. In the fourth embodiment, by forming an adjustment layer made of a material having a larger thermal expansion coefficient than that of the support substrate, the support substrate can have a property of being curved convexly toward the nitride-based semiconductor element layer side.

  First, as shown in FIG. 10A, the buffer layer 402, the underlayer 413, the n-type contact layer 403, the n-type cladding layer 404, and the n-type light guide layer 414 are formed on the Si substrate 401 by using the MOCVD method. Then, an active layer 405, a p-type carrier block layer 415, a p-type light guide layer 419, a p-type cladding layer 407, and a p-type contact layer 408 are sequentially grown, and then a p-side electrode is formed by vacuum deposition.

  Specifically, as in the second embodiment, about 50 pairs of Al layers having a thickness of about 5 nm and GaN layers having a thickness of about 20 nm are alternately stacked on the (111) plane of the Si substrate. A buffer layer 402 made of an AlN / GaN multilayer film is grown.

  Next, as in the third embodiment, the base layer 413, the n-type contact layer 403, the n-type cladding layer 404, the active layer 405, the p-type carrier block layer 415, the p-type light guide layer 419, and the p-type cladding. A nitride-based semiconductor element layer constituted by the layer 407 and the p-type contact layer 408 is formed.

  Next, as in the third embodiment, the ridge 417, the current blocking layer, the p-side electrode, and the p-type are formed using photolithography, reactive ion etching, plasma CVD, and vacuum deposition. A pad electrode 416 is formed.

  Here, due to the difference in thermal expansion coefficient between the Si substrate 401 and the nitride-based semiconductor element layer described above, the nitride-based semiconductor element layer is curved convexly toward the supporting substrate to be bonded.

On the other hand, as shown in FIG. 10B, as in the second embodiment, a composite material of Cu and Cu ₂ O (for example, Cu: 50 wt%, Cu ₂ O: 50 wt% content rate) A Cu layer having a thickness of about 3 μm on one main surface of a support substrate 410 having a thickness of about 200 μm via an adhesive layer made of a Ti layer having a thickness of about 10 nm. The adjustment layer 411 is formed by a vacuum deposition method. The adjustment layer 411 is made of a material having a larger thermal expansion coefficient than that of the support substrate 410. Note that the adhesive layer made of the Ti layer has a thermal expansion coefficient comparable to that of the support substrate 410 made of a composite material of Cu and Cu ₂ O, and therefore does not correspond to the adjustment layer 411 here. Further, a fusion layer 409 made of an Au layer having a thickness of about 500 nm is sequentially formed on the other main surface of the support substrate 410 by a vacuum deposition method through an adhesive layer made of a Ti layer having a thickness of about 10 nm. To do.

Here, the thermal expansion coefficients of the support substrate 410 made of the composite material having the contents of Cu: 50% by weight and Cu ₂ O: 50% by weight and the adjustment layer 411 made of the Cu layer are about 10 ×, respectively. 10 ⁻⁶ / K and about 17 × 10 ⁻⁶ / K, and the support substrate 410 is concavely curved toward the nitride-based semiconductor element layer to be bonded.

  If necessary, the support substrate 210 after the formation of the adjustment layer 211 may be annealed.

  Next, as shown in FIG. 10C, as in the third embodiment, the p-side electrode on the nitride-based semiconductor element layer and the fusion layer 409 on the support substrate 410 are made of Au—Sn. Thermocompression bonding is performed via a solder made of Pd—Sn, In—Pd, or a conductive paste made of Ag.

  Next, as shown in FIGS. 11A and 11B, as in the third embodiment, an n-side ohmic electrode is formed in a predetermined region on the n-type contact layer 403 by using a vacuum evaporation method. Form. Then, the n-side pad electrode 420 is formed on the n-side ohmic electrode.

  Next, as shown in FIGS. 12A and 12B, as in the third embodiment, a predetermined region other than the n-side pad electrode 420 is subjected to reactive ion etching using a chlorine-based gas. The laser resonator end face 418 is formed.

  Next, as shown in FIGS. 13A and 13B, element isolation is performed by dicing, laser scribing, or selective etching of the support substrate 410. In this manner, the nitride semiconductor laser according to the fourth embodiment is formed.

  According to the method for manufacturing a nitride semiconductor device and the nitride semiconductor device according to the fourth embodiment, since the adjustment layer 411 is made of a material having a thermal expansion coefficient larger than that of the support substrate 410, the support substrate 410 is made of nitride. It can have the property of curving convexly toward the system semiconductor element layer side. For this reason, the support substrate 410 and the nitride-based semiconductor element layer can be uniformly bonded. As such an example, the support substrate 410 is preferably composed mainly of a composite of a metal and an oxide of the metal, and the adjustment layer 411 is a metal layer.

(Other embodiments)
Although the present invention has been described according to the above-described embodiments, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  For example, in the first to fourth embodiments, the method of manufacturing a light emitting diode or a semiconductor laser that mainly uses light emitted from the active layer of the nitride semiconductor element layer has been exemplified, but the present invention is not limited thereto. In addition, the present invention can also be used for manufacturing a light emitting device that combines a phosphor that uses the light emitted from these light emitting devices as excitation light. Further, it can be applied to electronic devices such as HEMT (High Electron Mobility Transistor) having a nitride-based semiconductor element layer, SAW (Surface Acoustic Wave) devices, and light receiving elements. Further, by applying the substrate replacement technique according to the present invention, it is possible to apply to a multi-wavelength semiconductor laser, thereby improving the yield of the emission point interval in the wafer plane in the multi-wavelength laser. .

  In the first to fourth embodiments, the removal by laser irradiation and the wet etching are exemplified as the method for removing the growth substrate. However, the present invention is not limited to this, and polishing is performed according to the substrate material to be used. Etching by dry or dry is possible. Alternatively, the interface between the growth substrate and the semiconductor element layer may be separated by applying a sudden temperature change using the difference in thermal expansion coefficient between the growth substrate and the semiconductor element layer. In addition, laser irradiation can be achieved by incorporating a release layer such as a metal film, a dielectric film (or a laminated film thereof), an amorphous layer, or a layer with a void in the semiconductor element layer or at the interface with the growth substrate. Alternatively, the substrate may be removed by selectively decomposing and etching the release layer or the nitride-based semiconductor element layer near the release layer by dry etching.

  In the first to fourth embodiments, the MOCVD method is used for crystal growth of each nitride semiconductor layer. However, the present invention is not limited to this, and the HVPE method, the gas source MBE method, or the like is used. Alternatively, each nitride semiconductor layer may be crystal-grown. The crystal structure of the nitride compound semiconductor may be a wurtzite type or a zinc blende type structure. Further, the growth plane orientation is not limited to (0001), and may be (11-20) or (1-100).

  In the first to fourth embodiments, the nitride-based semiconductor element layer including a layer made of GaN, AlGaN, InGaN, AlN or the like is used. However, the present invention is not limited to this, and GaN, AlGaN, InGaN. Alternatively, a nitride-based semiconductor element layer including a layer other than the layer made of AlN may be used. The semiconductor element layer may have a current confinement structure such as a mesa structure or a ridge structure.

  In the first to fourth embodiments, the sapphire substrate and the Si substrate are used as the growth substrate for the nitride semiconductor element layer. However, the present invention is not limited to this, and the growth of the nitride semiconductor is not limited thereto. Possible substrates such as SiC, GaAs, MgO, ZnO, spinel and GaN can be used.

  In the first and second embodiments, it has been described that the p-side electrode is disposed on the entire surface. However, the p-side electrode may be disposed on only a part of the surface. In the case where an electrode is provided only in part, it is more desirable to form a film that reflects light. Further, it is desirable to provide a pad electrode in order to strengthen the adhesive force with the support substrate.

The support substrate material is preferably conductive. In addition to the metal-metal oxide composite material used in the first to fourth embodiments, a conductive semiconductor (Si, SiC, GaAs, ZnO) is used. Etc.), metals or composite metals (Al, Fe—Ni, Cu—W, CU—Mo, etc.) can be used. In general, a metal-based material is superior to a semiconductor material in terms of mechanical properties and is not easily cracked, and thus is suitable as a support substrate material. More preferably, a high conductivity metal and a metal oxide, such as W, Mo, Ni, and Cu ₂ O, are combined with a highly conductive metal such as Cu, Ag, and Au, so that the high conductivity and the high conductivity are obtained. It is to use a material having both mechanical strength. In this case, for example, Cu—Cu ₂ O (Cu: 50 wt%, Cu ₂ O: 50 wt%), Cu—W (Cu: 50 wt%, W: 50 wt%), Cu—Mo (Cu: 50 wt%). %, Mo: 50% by weight) are 10 × 10 ⁻⁶ / K, 7 × 10 ⁻⁶ / K, and 7 × 10 ⁻⁶ / K, respectively. Examples of the adjustment layer material having a small thermal expansion coefficient with respect to the substrate material include Si, W, and Mo. Examples of the adjustment layer material having a large thermal expansion coefficient with respect to the substrate material include Ni, Au, Cu, An—Sn, Ag, and Al.

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

It is sectional drawing for demonstrating the outline of the nitride type semiconductor element which concerns on the 1st-4th embodiment. It is sectional drawing for demonstrating the manufacturing method of the nitride type semiconductor device which concerns on 1st Embodiment (the 1). It is sectional drawing for demonstrating the manufacturing method of the nitride type semiconductor device which concerns on 1st Embodiment (the 2). It is sectional drawing for demonstrating the manufacturing method of the nitride type semiconductor device which concerns on 2nd Embodiment (the 1). It is sectional drawing for demonstrating the manufacturing method of the nitride type semiconductor device which concerns on 2nd Embodiment (the 2). It is sectional drawing for demonstrating the manufacturing method of the nitride type semiconductor device which concerns on 3rd Embodiment (the 1). (A) is sectional drawing for demonstrating the manufacturing method of the nitride type semiconductor element which concerns on 3rd Embodiment (the 2), (b) is a top view of (a). (A) is sectional drawing for demonstrating the manufacturing method of the nitride-type semiconductor element which concerns on 3rd Embodiment (the 3), (b) is a top view of (a). (A) is sectional drawing for demonstrating the manufacturing method of the nitride type semiconductor element which concerns on 3rd Embodiment (the 4), (b) is a top view of (a). It is sectional drawing for demonstrating the manufacturing method of the nitride type semiconductor device which concerns on 4th Embodiment (the 1). (A) is sectional drawing for demonstrating the manufacturing method of the nitride-type semiconductor element which concerns on 4th Embodiment (the 2), (b) is a top view of (a). (A) is sectional drawing for demonstrating the manufacturing method of the nitride-type semiconductor element which concerns on 4th Embodiment (the 3), (b) is a top view of (a). (A) is sectional drawing for demonstrating the manufacturing method of the nitride type semiconductor element which concerns on 4th Embodiment (the 4), (b) is a top view of (a). It is sectional drawing for demonstrating the outline of the conventional nitride-type semiconductor element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,101,201,301,401,501 ... Growth substrate 3,503 ... Nitride semiconductor element layer 9,109,209,309,409,509 ... Fusion layer 10,110,210,310,410, 510 ... Support substrate 11, 111, 211, 311, 411, 511 ... Adjustment layer 102, 202, 302, 402 ... Buffer layer 103, 203, 303, 403 ... n-type contact layer 104, 204, 304, 404 ... n-type Cladding layer 105, 205, 305, 405 ... Active layer 106, 206 ... p-type cap layer 107, 207, 307, 407 ... p-type cladding layer 108, 208, 308, 408 ... p-type contact layer 112, 212, 312, 412: n-side electrode 113, 213, 313, 413 ... base layer 314, 414 ... n-type light guide layer 315, 15 ... p-type carrier blocking layer 316, 416 ... p-side pad electrode 317,417 ... ridge portion 318,418 ... laser resonator facet 319,419 ... p-type optical guide layer 320, 420 ... n-side pad electrode

Claims (6)

Forming at least one nitride-based semiconductor element layer on the first substrate;
Forming an adjustment layer made of a material having a coefficient of thermal expansion different from that of the second substrate on one main surface of the second substrate;
Bonding the other main surface of the second substrate on the nitride-based semiconductor element layer;
Removing the first substrate from the bonded nitride-based semiconductor element layer and the second substrate. A method for manufacturing a nitride-based semiconductor element, comprising: When the nitride-based semiconductor element layer formed on the first substrate has a property of being convexly curved toward the supporting substrate to be bonded,
The method for manufacturing a nitride-based semiconductor element according to claim 1, wherein the adjustment layer is made of a material having a smaller thermal expansion coefficient than the second substrate. The second substrate is mainly composed of a composite of a metal and an oxide of the metal,
The method for manufacturing a nitride semiconductor device according to claim 2, wherein the adjustment layer is a Si layer. When the nitride-based semiconductor element layer formed on the first substrate has a property of being concavely curved toward the supporting substrate to be joined,
The method for manufacturing a nitride semiconductor device according to claim 1, wherein the adjustment layer is made of a material having a larger thermal expansion coefficient than that of the second substrate. The second substrate is mainly composed of a composite of a metal and an oxide of the metal,
The method of manufacturing a nitride semiconductor device according to claim 4, wherein the adjustment layer is a layer made of the metal. Forming at least one nitride-based semiconductor element layer on the first substrate; bonding one main surface of the second substrate on the nitride-based semiconductor element layer; A nitride semiconductor device manufactured by the step of removing the first substrate from the bonded nitride semiconductor device layer and the second substrate,
A nitride-based semiconductor element comprising an adjustment layer made of a material having a coefficient of thermal expansion different from that of the second substrate on the other main surface of the second substrate.

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