JP2006229117A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology which can improve the performance of a semiconductor device. <P>SOLUTION: On a semiconductor substrate 1, NMOS transistors 11, 31 and PMOS transistors 21, 41 are formed. The gate insulating film 13 of the NMOS transistor 11, and the gate insulating film 23 of the PMOS transistor 21 are composed of a film having a dielectric constant higher than a silicon oxide film and a silicon nitride oxide film, respectively. The gate insulating film 33 of the NMOS transistor 31 is composed of a lower layer film 33a and an upper layer film 33b contacted with a gate electrode 34 laminated on the lower layer film 33a. The gate insulating film 13 of the NMOS transistor 11 and the gate insulating film 23 of the PMOS transistor 21 are formed of different materials, and the gate insulating film 13 of the NMOS transistor 11 and the upper layer film 33a of the gate insulating film 33 of the NMOS transistor 31 are formed of the same materials. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a plurality of MOS transistors and a method for manufacturing the same.

  In order to miniaturize a MOS transistor and improve the degree of integration and performance of a CMOS integrated circuit, it is necessary to reduce the gate insulating film of the MOS transistor. However, when a silicon oxide film or silicon oxynitride film is used as the material of the gate insulating film, the direct tunnel current flowing between the gate electrode and the semiconductor substrate increases as the film thickness decreases, resulting in a large power consumption. Problem arises.

Therefore, in Non-Patent Document 1 and Patent Documents 1 and 2, a technique using a high dielectric film as a material of the gate insulating film is proposed. With this technique, gate insulation is suppressed while suppressing an increase in leakage current. The equivalent oxide thickness (SiO ₂ ) of the film, that is, the effective thickness of the gate insulating film can be reduced.

  The specification of the unpublished patent application “Japanese Patent Application No. 2004-203712” by the present applicant also discloses a technique of using a high dielectric film as the material of the gate insulating film.

C. Hobbs et al., “Fermi Level Pinning at the PolySi / Metal Oxide Interface”, 2003 Symposium on VLSI Technology Digest of Technical Papers, p.9 JP 2003-23100 A JP 2003-309188 A

  However, as described in Non-Patent Document 1, for example, polysilicon is used as a material for a gate electrode, and a high dielectric material containing hafnium (Hf) or aluminum (Al) is used as a material for a gate insulating film. When used, the threshold voltage of the PMOS transistor or NMOS transistor is not sufficiently lowered, and the performance of the semiconductor device including these transistors may be lowered.

  In general, in a CMOS integrated circuit, an internal circuit and an input / output circuit serving as an interface with the outside operate with different power supply voltages, and a higher voltage is applied to the input / output circuit than to the internal circuit. Therefore, a gate insulating film that is thicker in the input / output circuit than in the internal circuit is used. As described above, even in a semiconductor device including a MOS transistor having a thin gate insulating film and a MOS transistor having a thick gate insulating film, when a high dielectric film is used as the material of the gate insulating film, Those threshold voltages are not sufficiently lowered, and the performance of the semiconductor device may be lowered.

  In addition, when different materials are used as the material of the gate insulating film in the two MOS transistors, the other MOS that has already been formed when the insulating film material that becomes the gate insulating film of one MOS transistor is formed. Insulating film material used as a gate insulating film of a transistor may be damaged, and as a result, the performance of the semiconductor device may be deteriorated.

  Therefore, the present invention has been made in view of the above problems, and an object thereof is to provide a technique capable of improving the performance of a semiconductor device.

  A first semiconductor device according to the present invention includes a first NMOS transistor, a second NMOS transistor having a gate insulating film thicker than a gate insulating film of the first NMOS transistor, and a PMOS transistor. Each of the gate insulating films of the NMOS transistor and the PMOS transistor includes a film that has a higher dielectric constant than that of the silicon oxide film and the silicon oxynitride film and is in contact with the gate electrode. The gate insulating film of the second NMOS transistor The film includes a first film and a second film stacked on the first film and in contact with the gate electrode, and the film of the first NMOS transistor, the film of the PMOS transistor, Are made of different materials, the film of the first NMOS transistor and the second NMOS transistor Wherein the second layer of the same material.

  According to a second semiconductor device of the present invention, a first NMOS transistor, a first PMOS transistor, a second PMOS transistor having a gate insulating film thicker than a gate insulating film of the first PMOS transistor, Each gate insulating film of the first NMOS transistor and the first PMOS transistor includes a film in contact with a gate electrode having a higher dielectric constant than a silicon oxide film and a silicon nitride oxide film, The gate insulating film of the second PMOS transistor includes a first film and a second film stacked on the first film and in contact with the gate electrode, and the film of the first NMOS transistor The film of the first PMOS transistor is made of a different material, the film of the first PMOS transistor, And the second layer of the PMOS transistor of the same material.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device including a first region and a second region in which first and second MOS transistors are respectively formed. Forming a first insulating film material to be a gate insulating film of the transistor on the entire surface of the semiconductor substrate; and (b) a first electrode material to be a gate electrode of the first MOS transistor being the first insulating material. Forming on the entire surface of the film material; and (c) leaving the first electrode material and the first insulating film material in the first region, and the first electrode material in the second region and Removing the first insulating film material; and (d) a second insulating film material to be a gate insulating film of the second MOS transistor on the structure obtained by executing the step (c); Said second MOS transistor A step of depositing a second electrode material to be a gate electrode of the star over the entire surface in this order; and (e) leaving the second insulating film material and the second electrode material in the second region, Removing the second insulating film material and the second electrode material in the first region.

  According to the first semiconductor device of the present invention, in the first NMOS transistor and the PMOS transistor, the film that contacts the gate electrode, including the gate insulating film, is formed of a different material. The material of the film and the material of the film of the PMOS transistor can be individually selected. Accordingly, since the material of the portion in contact with the gate electrode in the gate insulating film affects the threshold voltage of the MOS transistor, the threshold voltages of the first NMOS transistor and the PMOS transistor are each set to appropriate values. Can be set to As a result, the performance of the semiconductor device is improved.

  Further, since the gate insulating film of the second NMOS transistor includes the second film made of the same material as the high dielectric constant film included in the gate insulating film of the first NMOS transistor, the second NMOS transistor Can be set to an appropriate value, and the manufacturing cost can be reduced while reducing the effective thickness of the gate insulating film of the second NMOS transistor.

  Further, according to the second semiconductor device of the present invention, in the first NMOS transistor and the first PMOS transistor, the film that contacts the gate electrode, which is included in the gate insulating film, is formed of different materials. The material of the film of the first NMOS transistor and the material of the film of the first PMOS transistor can be individually selected. Accordingly, since the material of the portion in contact with the gate electrode in the gate insulating film affects the threshold voltage of the MOS transistor, the threshold voltages of the first NMOS transistor and the first PMOS transistor are independently set. It can be set to an appropriate value. As a result, the performance of the semiconductor device is improved.

  Further, since the gate insulating film of the second PMOS transistor includes the second film made of the same material as the high dielectric constant film included in the gate insulating film of the first PMOS transistor, the second PMOS transistor Can be set to an appropriate value, and the manufacturing cost can be reduced while reducing the effective thickness of the gate insulating film of the second PMOS transistor.

  According to the method for manufacturing a semiconductor device of the present invention, when the step (e) is performed, the first insulating film material in the first region is covered with the first electrode material. Therefore, when the second insulating film material and the second electrode material in the first region are removed, the first insulating film material that becomes the gate insulating film of the first MOS transistor is prevented from being damaged. it can. As a result, the performance of the semiconductor device can be improved.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 1 of the present invention. The semiconductor device according to the first embodiment includes a thin film region where a MOS transistor having a relatively small gate insulating film is formed and a thickness where a MOS transistor having a relatively large gate insulating film is formed. And a membrane region. For example, a circuit in which a relatively small gate voltage is applied to the gate electrode of a MOS transistor is formed in the thin film region, such as an internal circuit in an integrated circuit, and an input / output circuit in the integrated circuit is formed in the thick film region. Thus, a circuit is formed in which a relatively large gate voltage is applied to the gate electrode of the MOS transistor.

  As shown in FIG. 1, the semiconductor device according to the first embodiment includes a semiconductor substrate 1 made of, for example, a silicon substrate. An element isolation insulating film 2 made of, for example, a silicon oxide film is formed in the upper surface of the semiconductor substrate 1, and the plurality of MOS transistors are electrically insulated by the element isolation insulating film 2.

  A p-type well region 3 and an n-type well region 4 are formed in the upper surface of the semiconductor substrate 1 in the thin film region, and an NMOS transistor 11 and a PMOS transistor 21 are respectively formed in the well regions 3 and 4. Has been. On the other hand, a p-type well region 5 and an n-type well region 6 are formed in the upper surface of the semiconductor substrate 1 in the thick film region. Are formed respectively.

  Two n-type source / drain regions 12 of the NMOS transistor 11 are formed apart from each other in the upper surface of the well region 3, and two p-types of the PMOS transistor 21 are formed in the upper surface of the well region 4. The source / drain regions 22 of the mold are formed apart from each other. Two n-type source / drain regions 32 of the NMOS transistor 31 are formed apart from each other in the upper surface of the well region 5, and 2 of the PMOS transistor 41 in the upper surface of the well region 6. Two p-type source / drain regions 42 are formed apart from each other.

  A gate electrode 14 is formed on the well region 3 between the source / drain regions 12 via a gate insulating film 13. A gate electrode 14 is formed on the well region 4 between the source / drain regions 22 via a gate insulating film 23. An electrode 24 is formed. Further, a gate electrode 34 is formed on the well region 5 between the source / drain regions 32 via a gate insulating film 33, and on the well region 6 between the source / drain regions 42 via a gate insulating film 43. Thus, a gate electrode 44 is formed. The gate electrodes 14, 24, 34, and 44 are made of, for example, polysilicon, tantalum nitride (TaN), titanium nitride (TiN), or tungsten (W).

  A side wall 15 of the NMOS transistor 11 is formed on the side surfaces of the gate insulating film 13 and the gate electrode 14, and a side wall 25 of the PMOS transistor 21 is formed on the side surfaces of the gate insulating film 23 and the gate electrode 24. Yes. A sidewall 35 of the NMOS transistor 31 is formed on the side surfaces of the gate insulating film 33 and the gate electrode 34, and a sidewall 45 of the PMOS transistor 41 is formed on the side surfaces of the gate insulating film 43 and the gate electrode 44. Has been. The sidewalls 15, 25, 35, 45 are made of, for example, a silicon nitride film.

  On the semiconductor substrate 1, an interlayer insulating film 50 is formed so as to cover the element isolation insulating film 2, the NMOS transistors 11 and 31, and the PMOS transistors 21 and 41. A plurality of contact plugs 51 are formed in the interlayer insulating film 50 so as to penetrate the interlayer insulating film 50 and reach the source / drain regions 12, 22, 32, and 42, respectively. On the interlayer insulating film 50, a plurality of wirings 52 that are in contact with the plurality of contact plugs 51 are formed. For example, the interlayer insulating film 50 is made of a silicon oxide film, the contact plug 51 is made of polysilicon, and the wiring 52 is made of aluminum.

In the thin film region according to the first embodiment, the structure of the gate insulating film of the MOS transistor is, for example, a single layer structure. The gate insulating film 13 of the NMOS transistor 11 is made of a film having a dielectric constant higher than that of the silicon oxide film and the silicon oxynitride film, and the film is made of, for example, hafnium oxide (HfO ₂ ), its silicon compound, or its nitride. . The gate insulating film 23 of the PMOS transistor 21 is made of a film having a dielectric constant higher than that of the silicon oxide film and the silicon oxynitride film, which is different from the gate insulating film 13 of the NMOS transistor 11. Al ₂ O ₃ ) and nitrides thereof.

  On the other hand, in the thick film region according to the first embodiment, the gate insulating film of the MOS transistor has a two-layer structure, for example, and the gate insulating film in the thick film region is formed thicker than the gate insulating film in the thin film region. Yes. The gate insulating film 33 of the NMOS transistor 31 includes a lower layer film 33 a formed on the semiconductor substrate 1 and an upper layer film 33 b that is stacked on the lower layer film 33 a and is in contact with the gate electrode 34. The lower layer film 33 a is made of, for example, a silicon oxide film or a silicon oxynitride film, and the upper layer film 33 b is made of the same material as the gate insulating film 13 of the NMOS transistor 11. Therefore, when the gate insulating film 13 is made of hafnium oxide, the upper layer film 33b in the gate insulating film 33 is also made of hafnium oxide.

  The gate insulating film 43 of the PMOS transistor 41 includes a lower layer film 43 a formed on the semiconductor substrate 1 and an upper layer film 43 b that is stacked on the lower layer film 43 a and is in contact with the gate electrode 44. The lower layer film 43 a is made of, for example, a silicon oxide film or a silicon oxynitride film, and the upper layer film 43 b is made of the same material as the gate insulating film 23 of the PMOS transistor 21. Therefore, when the gate insulating film 23 is made of aluminum oxide, the upper layer film 43b in the gate insulating film 43 is also made of aluminum oxide.

  Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described. 2 to 10 are cross-sectional views showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps. First, as shown in FIG. 2, the element isolation insulating film 2 is formed in the upper surface of the semiconductor substrate 1, and then the well regions 3 to 6 are formed. Then, an insulating film material 63 that forms the lower layer film 33 a of the gate insulating film 33 in the NMOS transistor 31 and the lower layer film 43 a of the gate insulating film 43 in the PMOS transistor 41 is formed on the entire upper surface of the exposed semiconductor substrate 1. The insulating film material 63 is made of, for example, a silicon oxide film, and is formed by thermally oxidizing the upper surface of the semiconductor substrate 1. Note that nitriding treatment may be performed on the insulating film material 63.

  Next, as shown in FIG. 3, a photoresist 64 covering the thick film region is formed on the semiconductor substrate 1, and wet etching is performed on the exposed insulating film material 63 using the photoresist 64 as a mask. Do. Thereby, the insulating film material 63 in the thin film region is removed. Then, the photoresist 64 is removed.

  Next, as shown in FIG. 4, an insulating film material 73 to be the upper layer film 33 b of the gate insulating film 13 of the NMOS transistor 11 and the gate insulating film 33 of the NMOS transistor 31 is formed on the entire surface. The insulating film material 73 is made of, for example, hafnium oxide, a silicon compound thereof, or a nitride thereof.

  Next, as shown in FIG. 5, a photoresist 74 covering the region where the NMOS transistor 11 is formed in the thin film region and the region where the NMOS transistor 31 is formed in the thick film region is formed on the insulating film material 73. Then, wet etching or dry etching is performed on the exposed insulating film material 73 using the photoresist 74 as a mask. Thus, the insulating film material 73 in the region where the PMOS transistor 21 is formed in the thin film region and the insulating film material 73 in the region where the PMOS transistor 41 is formed in the thick film region are removed. Then, the photoresist 74 is removed.

  Next, as shown in FIG. 6, an insulating film material 83 to be the upper layer film 43 b of the gate insulating film 23 of the PMOS transistor 21 and the gate insulating film 43 of the PMOS transistor 41 is formed on the entire surface. The insulating film material 83 is made of, for example, aluminum oxide or a nitride thereof.

  Next, as shown in FIG. 7, a photoresist 84 covering the region where the PMOS transistor 21 is formed in the thin film region and the region where the PMOS transistor 41 is formed in the thick film region is formed on the insulating film material 83. Then, wet etching or dry etching is performed on the exposed insulating film material 83 by using the photoresist 84 as a mask. Thereby, the insulating film material 83 in the region where the NMOS transistor 11 is formed in the thin film region and the insulating film material 83 in the region where the NMOS transistor 31 is formed in the thick film region are removed. Then, the photoresist 84 is removed.

  Next, as shown in FIG. 8, an electrode material 94 to be the gate electrodes 14, 24, 34, 44 is formed on the entire surface. The electrode material 94 is made of, for example, polysilicon, tantalum nitride, titanium nitride, or tungsten. Then, the electrode material 94 and the insulating film materials 63, 73, and 83 are patterned. As a result, as shown in FIG. 9, the gate insulating film 13 made of the insulating film material 73 and the gate insulating film 23 made of the insulating film material 83 are formed, and the gate electrodes 14 and 24 made of the electrode material 94 are formed. Is formed. At the same time, the lower layer film 33 a is made of the insulating film material 63, the upper layer film 33 b is made of the insulating film material 73, the lower layer film 43 a is made of the insulating film material 63, and the upper layer film 43 b is made of the insulating film material 83. A gate insulating film 43 is formed, and gate electrodes 34 and 44 made of an electrode material 94 are formed.

  Next, if it is necessary to form an extension region, impurity halo implantation is performed. Then, as shown in FIG. 10, sidewalls 15, 25, 35, 45 are formed, and then source / drain regions 12, 22, 32, 42 are formed.

  Next, if necessary, a silicide process is performed, and an interlayer insulating film 50, a contact plug 51, and a wiring 52 are sequentially formed. Thereby, the semiconductor device shown in FIG. 1 is completed.

  As described above, in the semiconductor device according to the first embodiment, in the NMOS transistor 11 and the PMOS transistor 21 in the thin film region, the gate insulating films 13 and 23 that are in contact with the gate electrodes 14 and 24 are formed of different materials. Therefore, the high dielectric material of the gate insulating film 13 of the NMOS transistor 11 and the high dielectric material of the gate insulating film 23 of the PMOS transistor 21 can be individually selected. Therefore, as can be understood from the contents described in Non-Patent Document 1 described above, the portion of the high dielectric material in contact with the gate electrode in the gate insulating film affects the threshold voltage of the MOS transistor. The threshold voltages of the NMOS transistor 11 and the PMOS transistor 21 can be independently set to appropriate values. As a result, the performance of the semiconductor device can be improved.

  For example, when the gate electrodes 14 and 24 are formed of polysilicon, the gate insulating film 13 is formed of hafnium oxide and the gate insulating film 23 is formed of aluminum oxide, whereby the NMOS transistor 11 and the PMOS transistor 21 are formed. Both threshold voltages can be sufficiently reduced, and the performance of the semiconductor device can be improved.

  Also in the NMOS transistor 31 and the PMOS transistor 41 in the thick film region, the upper layer film 33b of the gate insulating film 33 and the upper layer film 43b of the gate insulating film 43, which are in contact with the gate electrodes 34 and 44, are formed of different materials. Therefore, the threshold voltages of the NMOS transistor 31 and the PMOS transistor 41 can be set to appropriate values independently of each other. As a result, the performance of the semiconductor device can be improved.

  Further, the gate insulating film 33 of the NMOS transistor 31 in the thick film region includes the upper layer film 33b that contacts the gate electrode 34 and is made of the same high dielectric constant material as the gate insulating film 13 of the NMOS transistor 11 in the thin film region. The threshold voltage of the NMOS transistor 31 can be set to an appropriate value, and the manufacturing cost can be reduced while reducing the effective film thickness of the gate insulating film 33 of the NMOS transistor 31.

  In the first embodiment, the gate insulating film 43 of the PMOS transistor 41 in the thick film region is made of the same high dielectric constant material as the gate insulating film 23 of the PMOS transistor 21 in the thin film region, and is an upper layer in contact with the gate electrode 44. Since the film 43b is included, the threshold voltage of the PMOS transistor 41 can be set to an appropriate value, and the manufacturing cost can be reduced while reducing the effective film thickness of the gate insulating film 43 of the PMOS transistor 41. Can be reduced.

As materials for the gate insulating films 13 and 23, the upper layer film 33b of the gate insulating film 33, and the upper layer film 43b of the gate insulating film 43, zirconium oxide (ZrO ₂ ), yttrium oxide (Y ₂ O ₃ ), and lanthanum oxide are used. A high dielectric material made of (La ₂ O ₃ ), titanium oxide (TiO ₂ ), or praseodymium oxide (PrO _x ) can also be used.

  Also, the semiconductor device can be manufactured by a method other than the manufacturing method shown in FIGS. 11 to 14 are cross-sectional views showing another method of manufacturing the semiconductor device according to the first embodiment in the order of steps. First, the structure shown in FIG. 4 is manufactured by utilizing a part of the manufacturing method described above. Next, as shown in FIG. 11, an electrode material 104a to be the gate electrodes 11 and 31 is formed on the entire surface. The electrode material 104a is made of, for example, polysilicon, tantalum nitride, titanium nitride, or tungsten. Then, a photoresist 105 covering the region where the NMOS transistor 11 is formed in the thin film region and the region where the NMOS transistor 31 is formed in the thick film region is formed on the electrode material 104a.

  Next, using the photoresist 105 as a mask, dry etching, wet etching, or both are performed on the exposed electrode material 104a and the underlying insulating film material 73 to remove the photoresist 105. To do. Thus, as shown in FIG. 12, the electrode material 104a in the region where the PMOS transistor 21 is formed in the thin film region and the insulating film material 73 therebelow, and the electrode in the region where the PMOS transistor 41 is formed in the thick film region The material 104a and the underlying insulating film material 73 are removed.

  Next, as shown in FIG. 13, the insulating film material 83 is formed on the entire surface of the structure shown in FIG. Then, an electrode material 104 b to be the gate electrodes 24 and 44 is formed on the entire surface of the insulating film material 8.

  Next, the structure shown in FIG. 13 is polished from above by CMP or the like to flatten the surface of the structure. Thereby, as shown in FIG. 14, the unnecessary insulating film material 83 and electrode material 104b in the region where the NMOS transistors 11 and 31 are formed are removed. Thereafter, similarly to the manufacturing method described with reference to FIGS. 9 and 10, the electrode materials 104a and 104b and the insulating film materials 63, 73 and 83 are patterned, and the gate insulating films 13, 23, 33 and 43 and the gate are patterned. The electrodes 14, 24, 34, 44 are formed, and the sidewalls 15, 25, 35, 45, the source / drain regions 12, 22, 32, 42, the interlayer insulating film 50, the contact plug 51, and the wiring 52 are sequentially formed.

  In the manufacturing method as described above, the electrode material 104a is formed on the insulating film material 73 prior to the insulating film material 83. Therefore, after the insulating film material 83 and the electrode material 104b are formed, the NMOS of them is formed. When removing unnecessary portions of the region where the transistors 11 and 31 are formed, the insulating film material 73 in the region where the NMOS transistor 11 is formed in the thin film region and the NMOS transistor 31 is formed in the thick film region. The insulating film material 73 in the region is covered with the electrode material 104a.

  On the other hand, in the manufacturing method shown in FIGS. 2 to 10, the insulating film material 83 is formed on the entire surface of the insulating film material 73 before the electrode material 94 is formed, as shown in FIG. As shown in FIG. 4, when the unnecessary insulating film material 83 in the region where the NMOS transistors 11 and 31 are formed is removed, the necessary insulating film material 73 existing under the insulating film material 83 is damaged. Sometimes. As a result, the performance of the semiconductor device may deteriorate.

  In the manufacturing method shown in FIGS. 11 to 14, when the unnecessary insulating film material 83 and electrode material 104b in the region where the NMOS transistors 11 and 31 are formed are removed, the region where the NMOS transistors 11 and 31 are formed. Since the insulating film material 73 is covered with the electrode material 104a, the insulating film material 73 can be prevented from being damaged. Therefore, the performance degradation of the NMOS transistors 11 and 31 can be suppressed, and as a result, the performance of the semiconductor device can be improved.

Embodiment 2. FIG.
FIG. 15 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment of the present invention. The semiconductor device according to the second embodiment is the same as the semiconductor device according to the first embodiment described above, except that the lower layer film 33c is provided instead of the lower layer film 33a of the gate insulating film 33 in the NMOS transistor 31, and the gate in the PMOS transistor 41 is provided. Instead of the lower layer film 43 a of the insulating film 43, a lower layer film 43 c is provided.

  The lower layer film 33c of the NMOS transistor 31 according to the second embodiment is formed of the same material as the gate insulating film 23 in the PMOS transistor 21 in the thin film region, and the lower layer film 43c of the PMOS transistor 41 is the NMOS transistor in the thin film region. 11 is made of the same material as the gate insulating film 13 in FIG. Therefore, in the semiconductor device according to the second embodiment, the gate insulating film 33 of the NMOS transistor 31 includes the lower layer film 33 c made of the same material as the gate insulating film 23 of the PMOS transistor 21, and the gate insulating film 13 of the NMOS transistor 11. The gate insulating film 43 of the PMOS transistor 41 is composed of the lower layer film 43c made of the same material as the gate insulating film 13 of the NMOS transistor 11 and the gate insulating film 23 of the PMOS transistor 21. And an upper layer film 43b made of the same material. Since other structures are the same as those of the semiconductor device according to the first embodiment, description thereof is omitted.

  Next, a method for manufacturing the semiconductor device shown in FIG. 15 will be described. 16 to 24 are cross-sectional views showing the method of manufacturing the semiconductor device according to the second embodiment in the order of steps. First, as shown in FIG. 16, the element isolation insulating film 2 is formed in the upper surface of the semiconductor substrate 1, and then the well regions 3 to 6 are formed. Then, the above-described insulating film material 73 that becomes the gate insulating film 13 in the NMOS transistor 11 and the lower layer film 43 c of the gate insulating film 43 in the PMOS transistor 41 is formed on the entire upper surface of the exposed semiconductor substrate 1.

  Next, as shown in FIG. 17, the photoresist 110 covering the region where the NMOS transistor 11 is formed in the thin film region and the region where the PMOS transistor 41 is formed in the thick film region is removed from the element isolation insulating film 2 and the insulating film. Using the photoresist 110 as a mask, wet etching or dry etching is performed on the exposed insulating film material 73 using the photoresist 110 as a mask. As a result, the insulating film material 73 in the region where the PMOS transistor 21 is formed in the thin film region and the insulating film material 73 in the region where the NMOS transistor 31 is formed in the thick film region are removed. Then, the photoresist 110 is removed.

  Next, as shown in FIG. 18, the above-described insulation becomes the gate insulating film 23 in the PMOS transistor 21, the lower layer film 33c of the gate insulating film 33 in the NMOS transistor 31, and the upper layer film 43b of the gate insulating film 43 in the PMOS transistor 41. A film material 83 is formed on the entire surface. Then, as shown in FIG. 19, a photoresist 111 is formed on the insulating film material 83 to cover the region where the PMOS transistor 21 is formed and the thick film region in the thin film region, and the photoresist 111 is used as a mask. Wet etching or dry etching is performed on the exposed insulating film material 83. Thereby, the insulating film material 83 in the region where the NMOS transistor 11 is formed in the thin film region is removed. Then, the photoresist 111 is removed.

  Next, as shown in FIG. 20, an electrode material 114a to be the gate electrodes 11, 21, 41 is formed on the entire surface. The electrode material 114a is made of, for example, polysilicon, tantalum nitride, titanium nitride, or tungsten. Next, a photoresist 112 covering the thin film region and the region where the PMOS transistor 41 is formed in the thick film region is formed on the electrode material 114a, and the exposed electrode is used using the photoresist 112 as a mask. Wet etching or dry etching is performed on the material 114a. Then, the photoresist 112 is removed. As a result, as shown in FIG. 21, the electrode material 114a in the region where the NMOS transistor 31 is formed in the thick film region is removed, and the insulating film material 83 in the region is exposed.

  Next, as shown in FIG. 22, an insulating film material 123 to be the upper layer film 33 b of the gate insulating film 33 in the NMOS transistor 31 is formed on the entire surface of the structure of FIG. 21. The insulating film material 123 is made of, for example, hafnium oxide, a silicon compound thereof, or a nitride thereof. Then, an electrode material 114 b to be the gate electrode 34 is formed on the entire surface of the insulating film material 123.

  Next, the structure shown in FIG. 22 is polished from above by CMP or the like to flatten the surface of the structure. Thus, as shown in FIG. 23, the unnecessary insulating film material 123 and electrode material 114b in the thin film region and the region where the PMOS transistor 41 is formed are removed.

  Next, as shown in FIG. 24, similarly to the manufacturing method according to the first embodiment, the electrode materials 114a and 114b and the insulating film materials 73, 83, and 123 are patterned, and the gate insulating films 13, 23, 33, 43 and gate electrodes 14, 24, 34, 44 are formed. Thereafter, sidewalls 15, 25, 35, 45, source / drain regions 12, 22, 32, 42, interlayer insulating film 50, contact plug 51, and wiring 52 are sequentially formed. Thereby, the semiconductor device shown in FIG. 15 is completed.

  As described above, in the semiconductor device according to the second embodiment, the gate insulating film 33 of the NMOS transistor 31 in the thick film region is a stack of a high dielectric film having a dielectric constant higher than that of the silicon oxide film and the silicon nitride oxide film. Due to the structure, the effective film thickness of the gate insulating film 33 can be further reduced. As a result, the driving capability of the NMOS transistor 31 can be improved, and the speed of the circuit including the NMOS transistor 31 can be increased.

  Further, the gate insulating film 33 of the NMOS transistor 31 includes an upper film 33 b made of the same material as the gate insulating film 13 of the NMOS transistor 11 and a lower film 33 c made of the same material as the gate insulating film 23 of the PMOS transistor 21. Therefore, the manufacturing cost can be further reduced.

  In the semiconductor device according to the second embodiment, the gate insulating film 43 of the PMOS transistor 41 in the thick film region has a stacked structure of a high dielectric film having a dielectric constant higher than that of the silicon oxide film and the silicon oxynitride film. Therefore, the effective film thickness of the gate insulating film 43 can be further reduced. As a result, the driving capability of the PMOS transistor 41 can be improved, and the speed of the circuit including the PMOS transistor 41 can be increased.

  Further, the gate insulating film 43 of the PMOS transistor 41 includes a lower layer film 43 c made of the same material as the gate insulating film 13 of the NMOS transistor 11 and an upper layer film 43 b made of the same material as the gate insulating film 23 of the PMOS transistor 21. Therefore, the manufacturing cost can be further reduced.

It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in process order. It is sectional drawing which shows the modification of the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the modification of the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the modification of the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the modification of the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention in order of a process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 11, 31 NMOS transistor, 21, 41 PMOS transistor, 13, 23, 33, 43 Gate insulating film, 33a, 33c, 43a, 43c Lower layer film, 33b, 43b Upper layer film, 73, 83 Insulating film material, 104a, 104b Electrode material.

Claims (7)

A first NMOS transistor;
A second NMOS transistor having a gate insulating film thicker than the gate insulating film of the first NMOS transistor;
A PMOS transistor,
Each gate insulating film of the first NMOS transistor and the PMOS transistor includes a film in contact with the gate electrode having a higher dielectric constant than the silicon oxide film and the silicon oxynitride film,
The gate insulating film of the second NMOS transistor includes a first film and a second film stacked on the first film and in contact with the gate electrode,
The film of the first NMOS transistor and the film of the PMOS transistor are made of different materials,
The semiconductor device, wherein the film of the first NMOS transistor and the second film of the second NMOS transistor are made of the same material. A first NMOS transistor;
A first PMOS transistor;
A second PMOS transistor having a gate insulating film thicker than a gate insulating film of the first PMOS transistor;
Each of the gate insulating films of the first NMOS transistor and the first PMOS transistor includes a film in contact with the gate electrode having a higher dielectric constant than the silicon oxide film and the silicon oxynitride film,
The gate insulating film of the second PMOS transistor includes a first film and a second film stacked on the first film and in contact with the gate electrode,
The film of the first NMOS transistor and the film of the first PMOS transistor are made of different materials,
The semiconductor device, wherein the film of the first PMOS transistor and the second film of the second PMOS transistor are made of the same material. The semiconductor device according to claim 2,
A second NMOS transistor having a gate insulating film thicker than a gate insulating film of the first NMOS transistor;
The gate insulating film of the second NMOS transistor includes a first film and a second film stacked on the first film and in contact with the gate electrode,
The semiconductor device, wherein the film of the first NMOS transistor and the second film of the second NMOS transistor are made of the same material. The semiconductor device according to claim 1,
The semiconductor device, wherein the first film of the second NMOS transistor is made of the same material as the film of the PMOS transistor. The semiconductor device according to claim 2,
The semiconductor device, wherein the first film of the second PMOS transistor is made of the same material as the film of the first NMOS transistor. The semiconductor device according to claim 3,
The first film of the second PMOS transistor is made of the same material as the film of the first NMOS transistor, and the first film of the second NMOS transistor is the first film of the first PMOS transistor. A semiconductor device made of the same material as the film. A method of manufacturing a semiconductor device comprising first and second regions in which first and second MOS transistors are formed, respectively,
(A) forming a first insulating film material to be a gate insulating film of the first MOS transistor over the entire surface of the semiconductor substrate;
(B) forming a first electrode material to be a gate electrode of the first MOS transistor on the entire surface of the first insulating film material;
(C) removing the first electrode material and the first insulating film material in the second region while leaving the first electrode material and the first insulating film material in the first region. When,
(D) On the structure obtained by executing the step (c), a second insulating film material that becomes the gate insulating film of the second MOS transistor and a second electrode that becomes the gate electrode of the second MOS transistor A step of depositing the electrode material on the entire surface in this order;
(E) removing the second insulating film material and the second electrode material in the first region while leaving the second insulating film material and the second electrode material in the second region. A method for manufacturing a semiconductor device.

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