JP2006228829A - Semiconductor device with capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the structure of a capacitor which provides a large capacitance value to the capacitor without increasing the size of a semiconductor device. <P>SOLUTION: In the semiconductor device, a plurality of LOCOS element isolation regions 2a, 2b, 2c, and 2d and conductive diffusion layers 3a, 3b, and 3c are formed on a silicon substrate 1 in the stripe geometry so as to be adjacent to each other to form an uneven surface on the silicon substrate 1. The diffusion layers 3a, 3b, and 3c are common-connected, and a first insulation layer 4, a lower-layer conductive layer 5, a second insulation layer 6, and an upper-layer conductive layer 7 are stacked in order on the uneven surface. Using these layers, two capacitors are fabricated. One capacitor uses the diffusion layers 3a, 3b, and 3c and the lower-layer conductive layer 5 as a pair of electrodes, and uses the first insulation layer 4 as a dielectric layer; while the other capacitor uses the lower-layer conductive layer 5 and the upper-layer conductive layer 7 as a pair of electrodes, and uses the second insulation layer 6 as a dielectric layer. The upper-layer conductive layer 7 and the common-connected diffusion layers 3a, 3b, and 3c are electrically connected. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The present invention relates to a semiconductor device having a capacitor, and more particularly to the structure of the capacitor.

A capacitor in a conventional semiconductor device generally has a structure in which a conductive layer constituting a pair of electrodes is formed in a planar shape above and below an insulating layer constituting a dielectric layer in a flat region. The capacitance value of the capacitor is determined by the dielectric constant of the dielectric layer and the size of the opposing area of each conductive layer sandwiching the dielectric layer.
Japanese Patent Laid-Open No. 5-190766

Therefore, in the conventional capacitor described above, if the dielectric constant is the same, the capacitance value cannot be increased unless the opposing area of each conductive layer is increased. Was necessary. For this reason, in order to form a capacitor having a large capacitance value, there has been a problem that an increase in the size of the semiconductor device cannot be avoided. An object of the present invention is to solve this problem and to provide a capacitor structure capable of obtaining a large capacitance value without increasing the size of a semiconductor device.

  In order to achieve this object, a capacitor structure according to claim 1 of the present invention is a semiconductor device in which a concavo-convex surface is formed by a plurality of LOCOS element isolation regions formed on a silicon substrate, and on the concavo-convex surface, A capacitor is configured by superposing and forming a conductive layer as a lower electrode, an insulating layer as a dielectric layer, and a conductive layer as an upper electrode.

  Similarly, in order to achieve this object, a capacitor structure according to claim 2 of the present invention is a semiconductor device in which a plurality of LOCOS element isolation regions and a diffusion layer as a conductive layer are adjacent to each other on a silicon substrate. For example, it is formed in a striped pattern to form an uneven surface, and the diffusion layers are connected in common, while an insulating layer and a conductive layer are alternately stacked on the uneven surface to form each insulating layer. A plurality of capacitors having a dielectric layer and a pair of electrodes, each conductive layer including the upper and lower diffusion layers sandwiching each insulating layer, and every other conductive layer electrically connected is there.

  Similarly, in order to achieve this object, a capacitor structure according to claim 3 of the present invention is a semiconductor device in which a plurality of LOCOS element isolation regions and a diffusion layer as a conductive layer are adjacent to each other on a silicon substrate. For example, a concavo-convex surface is formed by forming a stripe shape, and the diffusion layers are connected in common, while a first insulating layer, a lower conductive layer, a second insulating layer, and an upper conductive layer are formed on the concavo-convex surface. Are formed in such a manner that each diffusion layer and the lower conductive layer are a pair of electrodes and the first insulating layer is a dielectric layer, and the lower conductive layer and the upper conductive layer are formed. A capacitor having a pair of electrodes and a dielectric layer as the second insulating layer is formed, and the upper conductive layer and each diffusion layer are electrically connected.

  Similarly, in order to achieve this object, a capacitor structure according to claim 4 of the present invention is a semiconductor device in which a plurality of LOCOS element isolation regions and a diffusion layer as a conductive layer are adjacent to each other on a silicon substrate. For example, a concavo-convex surface is formed by forming a stripe shape, and a plurality of insulating layers and conductive layers are alternately stacked on the concavo-convex surface, and each of the insulating layers serves as a dielectric layer, and each of the insulating layers A plurality of capacitors each having a pair of electrodes, each of the conductive layers including the upper and lower diffusion layers sandwiching the substrate, and a transistor having the diffusion layers as source / drain electrodes are formed on the silicon substrate, and gates of these transistors are formed. The electrode is formed so as to divide each diffusion layer at a position not corresponding to the conductive layer immediately above, and an electrode opposite to the conductive layer corresponding side of the source / drain electrode of each diffusion layer is formed. While passing connection is obtained by electrically connecting the conductive layer including a diffusion layer which is the commonly connected every other.

  Similarly, in order to achieve this object, the capacitor structure according to claim 5 of the present invention is a semiconductor device, wherein a plurality of LOCOS element isolation regions and a diffusion layer as a conductive layer are adjacent to each other on a silicon substrate. For example, by forming a concavo-convex surface by forming a striped shape, and forming a first insulating layer, a lower conductive layer, a second insulating layer, and an upper conductive layer on the concavo-convex surface in this order, A capacitor having each diffusion layer and the lower conductive layer as a pair of electrodes and the first insulating layer as a dielectric layer, and a capacitor having the lower conductive layer and the upper conductive layer as a pair of electrodes, and the second insulating layer as a dielectric While forming a capacitor as a body layer, a transistor having each diffusion layer as a source / drain electrode is formed on the silicon substrate, and the gate electrode of each of the transistors has the diffusion layer as a pair with the lower conductive layer. The electrode on the opposite side of the source / drain electrode corresponding to the lower conductive layer corresponding to the source / drain electrode is commonly connected and electrically connected to the upper conductive layer. It is a thing.

  Similarly, in order to achieve this object, the capacitor structure according to claim 6 of the present invention is the semiconductor device according to any one of claims 2 to 5 described above, wherein the common connection of each diffusion layer is: The diffusion layers are integrally connected at one end side.

  According to the invention of claim 1 of the present application, since the capacitor is formed on the concavo-convex surface, the conductive layers as a pair of electrodes facing each other across the dielectric layer are curved, and the facing area is planar. Compared to the case of facing each other, the capacitance can be increased, and a capacitor having a large capacitance value can be obtained without increasing the size of the semiconductor device.

  According to the invention according to claim 2 and claim 3 of the present application, a plurality of capacitors are provided on the concavo-convex surface, so that the facing area of the electrodes of the capacitor is further increased as compared with the invention according to claim 1. Can do.

  According to the invention according to claim 4 and claim 5 of the present application, a plurality of capacitors are provided on the concavo-convex surface, and the capacitor in the lowermost layer is commonly connected via the transistor. In addition to the effect of the invention according to No. 3, the capacitance value of the capacitor can be changed by the on / off control of the transistor.

  According to the invention of claim 6 of the present application, since the respective diffusion layers can be connected in common without using other components such as metal wiring, the configuration can be simplified.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the accompanying drawings. 1 to 3 show the first embodiment. FIG. 1 is a schematic sectional view of a semiconductor device having a capacitor, FIG. 2 is a plan view of the same, and FIG. 3 is a circuit for explaining the structure of the capacitor. FIG. FIG. 4 is a schematic plan view showing a semiconductor device having a capacitor according to the second embodiment. 5 and 6 show a third embodiment. FIG. 5 is a schematic plan view of a semiconductor device having a capacitor. FIG. 6 is a circuit diagram for explaining the configuration of the capacitor. FIG. 7 is a schematic plan view showing a semiconductor device having a capacitor according to the fourth embodiment.

  First, the first embodiment will be described. As shown in FIG. 1, a plurality of LOCOS element isolation regions 2a, 2b, 2c and 2d and a plurality of diffusion layers 3a and 3b which are conductive layers are formed on a silicon substrate 1 of a semiconductor device. , 3c are formed adjacent to each other in a striped pattern. Each of these LOCOS element isolation regions 2a, 2b, 2c, 2d and each diffusion layer 3a, 3b, 3c is formed by a known method, and each LOCOS element isolation region 2a, 2b, 2c, 2d and each diffusion layer are formed. The uneven surface is formed by the steps with the layers 3a, 3b, 3c.

  On each of the LOCOS element isolation regions 2a, 2b, 2c, 2d and the diffusion layers 3a, 3b, 3c forming the uneven surface, the first insulating layer 4 is formed using, for example, silicon oxide. A lower conductive layer 5 is formed on the first insulating layer 4 using, for example, polysilicon or molybdenum. Thus, a capacitor is formed in which the first insulating layer 4 is a dielectric layer, and the diffusion layers 3a, 3b, 3c and the lower conductive layer 5 are a pair of electrodes.

  Further, the second insulating layer 6 is formed on the lower conductive layer 5 using, for example, silicon oxide. An upper conductive layer 7 is formed on the second insulating layer 6 using, for example, polysilicon or molybdenum. Thus, a capacitor is formed in which the second insulating layer 6 is a dielectric layer, and the lower conductive layer 5 and the upper conductive layer 7 are a pair of electrodes. The lower conductive layer 5 is an electrode common to the upper and lower capacitors.

As shown in FIG. 2, the diffusion layers 3a, 3b, 3c are electrically connected in common by a metal wiring 8 such as aluminum, and the diffusion layers 3a, 3b, 3c connected in common are connected to the upper conductive layer by the metal wiring 8. 7 is electrically connected. Although not shown, it is preferable that the contact region with the metal wiring 8 in the diffusion layers 3a, 3b, 3c is a high impurity concentration region. As a result, as shown in FIG. 3, a capacitor having the lower conductive layer 5 as one common electrode and the other electrode opposite thereto as the diffusion layers 3a, 3b, 3c and the upper conductive layer 7 is connected in parallel. Configured. Further, the lower conductive layer 5 is electrically connected to an electrode of a MOS transistor (not shown) formed on the silicon substrate 1 by a metal wiring 9 such as aluminum.

  In the present embodiment, as described above, each of the diffusion layers 3a, 3b, 3c and the lower conductive layer 5 has a pair of electrodes, and the capacitor has the lower conductive layer 5 and the upper conductive layer 7 as a pair of electrodes. And the diffusion layers 3a, 3b, 3c and the upper conductive layer 7 are electrically connected to each other, and the lower conductive layer 5 and the upper conductive layer 7 are connected to a pair of electrodes. Capacitors to be formed on the concavo-convex surface formed by the LOCOS element isolation regions 2a, 2b, 2c, and 2d, so that the conductive layers 5 and 7 that are a pair of electrodes face each other in a curved shape. Without increasing the size in the horizontal direction, the facing area can be increased, and a capacitor having a capacitance value of approximately 1.4 times that of the same electrode in the horizontal direction can be obtained.

  FIG. 4 shows the second embodiment, which is different from the first embodiment described above in the configuration relating to the common connection of the diffusion layers 3a, 3b, 3c, not by the metal wiring 8 as described above, The diffusion layers 3a, 3b, and 3c are integrally connected at one end not corresponding to the lower portion of the lower conductive layer 5 and commonly connected. Therefore, the circuit configuration is the same as that of the first embodiment shown in FIG.

  Next, a third embodiment of the present invention will be described with reference to FIG. 1 based on FIG. 5 and FIG. A plurality of LOCOS element isolation regions 12a, 12b, 12c, and 12d and a plurality of diffusion layers 13a, 13b, and 13c, which are conductive layers, are formed in stripes on the silicon substrate 11 so as to be adjacent to each other, thereby forming an uneven surface. The first insulating layer 14, the lower conductive layer 15, the second insulating layer 16, and the upper conductive layer 17 are sequentially stacked on the uneven surface (see FIG. 1).

  Thus, each of the diffusion layers 13a, 13b, 13c, 13d and the lower conductive layer 15 as a pair of electrodes and a capacitor having the first insulating layer 14 as a dielectric layer, the lower conductive layer 15 and the upper conductive layer 17, And a capacitor having the second insulating layer 16 as a dielectric layer (see FIG. 1). In addition, since the above structure is the same as the structure of 1st Embodiment mentioned above, in FIG. 1, each code | symbol is attached | subjected with the code | symbol to the corresponding component.

As shown in FIG. 5, each diffusion layer 13a, 13b, 13c is divided at a position not corresponding to the lower conductive layer 15, and the gate electrodes 20a, 20b, 20c of the transistor are divided into the respective diffusion layers 13a, 13b, 13c is formed in an insulating state. These gate electrodes 20a, 20b, and 20c are formed of, for example, a refractory metal such as molybdenum, polysilicon, or the like. Then, portions 13a ₁ , 13a ₂ , 13b ₁ , 13b ₂ , 13c ₁ , 13c ₂ of the respective diffusion layers 13a, 13b, 13c, which are respectively located across the respective gate electrodes 20a, 20b, 20c, are connected to the source / drain. Each of the transistors is configured as an electrode. Further, the electrodes 13a ₁ , 13b ₁ , 13c ₁ on the opposite side to the lower conductive layer 15 side of the transistors are commonly connected by a metal wiring 18 and electrically connected to the upper conductive layer 17.

  In the present embodiment, as described above, each of the diffusion layers 13a, 13b, 13c and the lower conductive layer 15 has a pair of electrodes, and the capacitor has the lower conductive layer 15 and the upper conductive layer 17 as a pair of electrodes. Are superimposed on each other, and the capacitor having each diffusion layer 13a, 13b, 13c as one electrode is electrically connected to the upper conductive layer 17 via a transistor. By performing the off control, the capacitance value of the capacitor can be changed in four stages.

  The capacitor having the lower conductive layer 15 and the upper conductive layer 17 as a pair of electrodes is a pair of electrodes formed on the concavo-convex surface formed by the LOCOS element isolation regions 12a, 12b, 12c, and 12d. Since the conductive layers 15 and 17 are opposed to each other in a curved shape, the facing area is increased without expanding the electrodes in the horizontal direction, and the capacitance is larger than that of the same occupied area in the horizontal direction of the electrodes. A capacitor having a value of about 1.4 times can be obtained.

FIG. 7 shows the fourth embodiment, which is different from the third embodiment described above in the configuration related to the common connection of the electrodes 13a ₁ , 13b ₁ , 13c ₁ of each transistor. Instead, the electrodes 13a ₁ , 13b ₁ , 13c ₁ which are one end sides of the respective diffusion layers 13a, 13b, 13c are integrally connected and connected in common. Therefore, the circuit configuration is the same as that of the third embodiment shown in FIG. These third and fourth embodiments can be applied to a capacitor array in a radio wave receiver of a radio timepiece in view of its circuit configuration (see FIG. 6).

  The present invention is not limited to the above-described embodiments. For example, the electrical connection between the diffusion layers 3a, 3b, 3c, 13a, 13b, and 13c and the upper conductive layers 7 and 17 is the metal wiring 8. , 18 may be directly connected. Further, the number of capacitors formed in an overlapping manner is not limited to two, but may be three or more. In this case, as shown in FIG. 8, every other conductive layer C1 to Cn positioned above and below is electrically connected. It is good.

1 is a schematic cross-sectional view of a semiconductor device having a capacitor according to an embodiment of the present invention. FIG. The circuit diagram explaining the structure of a capacitor similarly. FIG. 6 is a schematic plan view of a semiconductor device having a capacitor according to a second embodiment. FIG. 6 is a schematic plan view of a semiconductor device having a capacitor according to a third embodiment. The circuit diagram explaining the structure of a capacitor similarly. FIG. 6 is a schematic plan view of a semiconductor device having a capacitor according to a fourth embodiment. The circuit diagram explaining the structure of the capacitor in further another embodiment of this invention.

Explanation of symbols

1,11 Silicon substrate 2a, 2b, 2c, 2d, 12a, 12b, 12c, 12d LOCOS element isolation region 3a, 3b, 3c, 13a, 13b, 13c Diffusion layer 4, 14 First insulating layer 5, 15 Lower conductive layer 6, 16 Second insulating layer 7, 17 Upper conductive layer 8, 9, 18, 19 Metal wiring 13a ₁ , 13a ₂ , 13b ₁ , 13b ₂ , 13c ₁ , 13c ₂ Source / drain electrode 20a, 20b, 20c Gate electrode C1-Cn conductive layer

Claims (6)

An uneven surface is formed by a plurality of LOCOS element isolation regions formed on a silicon substrate, and a conductive layer as a lower electrode, an insulating layer as a dielectric layer, and a conductive layer as an upper electrode are stacked on the uneven surface. A semiconductor device having a capacitor, wherein the capacitor is formed. A plurality of LOCOS element isolation regions and a diffusion layer as a conductive layer are formed on a silicon substrate so as to be adjacent to each other to form an uneven surface, and the diffusion layers are connected in common, while insulating on the uneven surface. A plurality of capacitors are formed by alternately stacking layers and conductive layers, using each insulating layer as a dielectric layer, and each conductive layer including the upper and lower diffusion layers sandwiching each insulating layer as a pair of electrodes. A semiconductor device having a capacitor, characterized in that every other conductive layer is electrically connected to each other. A plurality of LOCOS element isolation regions and a diffusion layer, which is a conductive layer, are formed on a silicon substrate so as to be adjacent to each other to form an uneven surface, and the diffusion layers are connected in common. A first insulating layer, a lower conductive layer, a second insulating layer, and an upper conductive layer are sequentially stacked to form each diffusion layer and the lower conductive layer as a pair of electrodes. A capacitor that is a dielectric layer, and a capacitor that includes the lower conductive layer and the upper conductive layer as a pair of electrodes and the second insulating layer as a dielectric layer, and the upper conductive layer and each diffusion layer A semiconductor device having a capacitor, wherein the capacitor is electrically connected to each other. A concavo-convex surface is formed by forming a plurality of LOCOS element isolation regions and conductive layers as diffusion layers adjacent to each other on a silicon substrate, and a plurality of insulating layers and conductive layers are alternately stacked on the concavo-convex surface. Forming a plurality of capacitors each having a dielectric layer as each insulating layer and a pair of electrodes each having a conductive layer including the upper and lower diffusion layers sandwiching each insulating layer. A transistor having each diffusion layer as a source / drain electrode is formed, and each diffusion layer is commonly connected to one of the source / drain electrodes, and every other conductive layer including the commonly connected diffusion layer is electrically connected. A semiconductor device having a capacitor characterized in that the capacitor is connected. A plurality of LOCOS element isolation regions and a diffusion layer as a conductive layer are formed on a silicon substrate so as to be adjacent to each other to form a concavo-convex surface, and on the concavo-convex surface, a first insulating layer, a lower conductive layer, The second insulating layer and the upper conductive layer are sequentially stacked to form a capacitor having each diffusion layer and the lower conductive layer as a pair of electrodes and the first insulating layer as a dielectric layer, and the lower layer A transistor having a conductive layer and the upper conductive layer as a pair of electrodes and a capacitor having the second insulating layer as a dielectric layer, and a transistor having each diffusion layer as a source / drain electrode is formed on the silicon substrate. Then, each of the diffusion layers is commonly connected to one of the source / drain electrodes and electrically connected to the upper conductive layer. A semiconductor device having a capacitor. 6. The semiconductor device having a capacitor according to claim 2, wherein the common connection of each diffusion layer is formed by integrally connecting the diffusion layers at one end side.

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