JP4711620B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a vertical MOSFET semiconductor device having a trench gate and a method for manufacturing the same.

  2. Description of the Related Art Conventionally, in a vertical MOSFET semiconductor device having a trench gate (hereinafter simply referred to as a MOSFET), the structure of a portion where polysilicon is overlapped as a gate lead electrode (end portion of a trench gate) is configured as shown below. It had been.

  FIGS. 17 to 19 and FIGS. 20 to 22 illustrate the structure of a conventional general MOSFET in the order of steps. In particular, a cross-sectional view of a termination portion of a gate trench in an Nch power MOSFET is shown. FIG. 23 is a plan view of the MOSFET corresponding to each of the cross-sectional views shown in FIGS. 17 to 19 and FIGS. 20 to 22. First, briefly describing FIG. 7, the gate trench 304 is provided vertically and horizontally in the semiconductor substrate 301, and the end portion of the gate trench 304 is overlapped by the polysilicon 306, and the PAD portion 303 is formed at the end thereof. Is provided. 17 to 19 are A-A ′ cross-sectional views of FIG. 23, and FIGS. 20 to 22 are B-B ′ cross-sectional views of FIG. 23.

  First, a P-well layer 302 is formed on a semiconductor substrate 301 by selective boron ion implantation and heat treatment using a photolithography technique (FIGS. 17A and 20A). Next, a PAD portion 303 which becomes a wire arrangement region for the gate lead electrode is formed by local oxidation of silicon (FIGS. 17B and 20B).

  Next, the gate trench 304 is formed by selective etching using a photolithography technique (FIGS. 17C and 20C). Subsequently, a gate oxide film 305 is formed on the entire surface by a thermal oxidation method (FIGS. 18A and 21A). Next, polysilicon 306 for the gate lead electrode is formed on the entire surface by the CVD method (FIGS. 18B and 21B). The polysilicon 306 is selectively etched by photolithography so that the polysilicon 306 partially overlaps the gate trench 304. At this time, the surface of the gate oxide film 305 that is not in contact with the polysilicon 306 is removed (FIGS. 18C and 21C). Subsequently, the base region 307 for the active cell is formed by boron ion implantation and heat treatment, and then the source region 308 is formed by arsenic ion implantation and heat treatment (FIGS. 19A and 22A).

  Next, BPSG (boron phosphorus doped oxide film) is formed by CVD method, an interlayer insulating film 309 is formed, contact holes are formed by selectively etching BPSG by photolithography technology, and finally aluminum is formed on the surface. The source electrode 310 is formed by sputtering (FIGS. 19B and 22B). A power MOSFET can be manufactured by the process described above.

  24 to 26 show the structure disclosed in Patent Document 1, and show the cross sections in the order of steps. A feature is that a two-layer structure of silicon nitride film / silicon insulating film is formed on the entire substrate including the trench.

  A trench 402 is formed on the semiconductor substrate 401 (FIG. 24A). Subsequently, an oxide film 403 of about 100 及 び and a nitride film 404 of about 200 Å are formed on the entire surface of the semiconductor substrate 401 including the inside of the trench 402 (FIG. 24B). Subsequently, a first polysilicon 405 having a thickness of about 4000 mm is formed on the entire surface. The first polysilicon 405 is doped with a high concentration of phosphorus (FIG. 24C). On top of that, an intermediate layer 407 made of an oxide film of about 1000 mm is formed (FIG. 25A). As long as the etching rate is slower than that of the first polysilicon 405, another material can be substituted.

  On the intermediate layer 407, a second polysilicon 408 of about 4000 mm is further formed (FIG. 25B). Thereby, the recess 406 in the trench 402 is buried. The second polysilicon 408 etches back the intermediate layer 407 as detection of the end of etching, leaving only the recess 406 (FIG. 25C). Next, the intermediate layer 407 is removed by etching to expose the first polysilicon 405 (FIG. 26A). Finally, the first polysilicon 405 is selectively etched to form the cell plate 409 (FIG. 26B).

  27A and 27B show the structure disclosed in Patent Document 2, wherein FIG. 27A is a plan view of a vertical power MOSFET, FIG. 27B is its BB cross-sectional view, and FIG. 27C is its CC cross-sectional view. It is. A three-layer structure of a first oxide film 515 / a silicon nitride film 516 / a second dioxide film 517 is formed on the entire semiconductor substrate 511 including the trench 514a. However, in FIG. 9C, the portion of the trench 514b is composed of the gate insulating film 520 and the gate electrode wiring 521, and other than the trench 514b, the first oxide film 515 / silicon nitride film 516 / second oxide film. It has a three-layer structure of 517.

JP 63-023325 JP-A-8-97412

  In the conventional general structure, the end portion of the gate trench for connecting to the gate lead electrode (the portion where polysilicon is overlapped on the trench gate) is a two-layer structure comprising polysilicon and a gate oxide film. Due to differences in structure and pattern from the active cell portion, shape differences are likely to occur. As a result, there is a problem that the withstand capability of the gate lead-out electrode portion is lowered.

  In addition, in this structure, if the structure of the overlap portion is a MOS transistor structure having the same base region and source region as the cell portion, an inversion layer is generated in that portion, causing a change in the characteristics of the MOS transistor, which makes design difficult. There was a case.

  In Patent Documents 1 and 2, a nitride film is formed on the entire substrate including the gate trench, and the insulating film has a two-layer structure as a polysilicon / nitride film / oxide film structure. However, since this method is applied to the entire substrate including the gate trench, the active cell portion has the same structure, and there is a problem that the characteristics of the active cell are deteriorated. Specifically, there are problems such as an increase in threshold voltage and an increase in on-resistance.

  An object of the present invention is to solve such problems of the prior art, and to provide a semiconductor device having a good gate lead-out electrode portion with no deterioration in characteristics and a method for manufacturing the same.

The semiconductor device of the present invention, for achieving the above object, the vertical MOS semiconductor device having a trench gate composed of two layer structure consisting of polysilicon and gate oxide film, the gate lead-out electrode of the trench gate The portion connected to is characterized by having a three-layer structure comprising polysilicon, a nitride film, and a gate oxide film . Configuration order of the port Rishirikon nitride film and the gate oxide film, the semiconductor device substrate, a gate oxide film, then a nitride film, and then be polysilicon desirable.

  Therefore, according to the semiconductor device of the present invention, an additional nitride film is formed on the trench gate where the polysilicon serving as the gate lead electrode overlaps, and no additional nitride film is formed on the active cell portion. Therefore, it is possible to provide a semiconductor device in which the gate lead-out electrode portion has a good withstand and no deterioration in characteristics.

In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention manufactures a vertical MOS semiconductor device having a trench gate having a two-layer structure in which an active cell portion is composed of polysilicon and a gate oxide film. in the method, the portion connected to the gate lead-out electrode of said trench gate comprises the steps of depositing a gate oxide film on a semiconductor device substrate formed with a trench, depositing a nitride film on a gate oxide film deposited by the process And a step of depositing polysilicon on the nitride film deposited by the step.

  Therefore, according to the method of manufacturing a semiconductor device of the present invention, since a step of additionally forming a nitride film is added to the portion where the polysilicon serving as the gate lead electrode is overlapped on the trench gate, the gate lead electrode portion It is possible to provide a semiconductor device with good withstand capability and no deterioration in characteristics.

  According to the semiconductor device of the present invention, only the structure of the connection portion of the gate extraction electrode having the trench gate (the end portion of the trench gate) is changed from the conventional gate extraction electrode (polysilicon) / gate oxide film structure. Electrode (polysilicon) / nitride film / gate oxide film or gate lead electrode (polysilicon) / gate oxide film / oxide film structure by CVD method, active cell portion is gate lead electrode (polysilicon) / gate oxide film Because of this structure, the active cell portion does not cause an increase in threshold voltage, an increase in on-resistance, etc., improving the withstand capability of the gate lead-out electrode portion, and preventing the formation of an inversion layer in the portion where polysilicon is overlapped Is possible at the same time.

Hereinafter, the best mode of the present invention will be described as a first embodiment and a second embodiment.
(Embodiment 1)
1 to 4 and FIGS. 5 to 8 are cross-sectional views in the order of steps according to the semiconductor device of the first embodiment. However, FIGS. 1-4 are AA 'sectional drawings of FIG. 23, FIGS. 5-8 is BB' sectional drawing of FIG. However, the end portion of the gate trench is shown in the Nch power MOSFET.

  First, the P well layer 102 is selectively formed on the semiconductor substrate 101 by boron ion implantation and heat treatment by a photolithography technique (FIGS. 1A and 5A). Next, the PAD portion 103 that becomes the wire arrangement region for the gate lead electrode is formed by LOCOS oxidation (FIG. 1B, FIG. 5B). Next, the gate trench 104 is formed by selective etching using a photolithography technique (FIGS. 1C and 5C). Subsequently, a gate oxide film 105 is formed on the entire surface by thermal oxidation (FIGS. 2A and 6A). Next, an insulating nitride film 111 is formed on the entire surface by a CVD method (FIGS. 2B and 6B). The nitride film 111 is selectively etched by photolithography so as to leave only a predetermined region (FIGS. 2C and 6C).

  Next, polysilicon 106 for a gate lead electrode is formed on the entire surface by the CVD method (FIGS. 3A and 7A). The polysilicon 106 is selectively etched so as to leave the same pattern as the nitride film 111 described above. At this time, the surface of the gate oxide film 105 that is not in contact with the polysilicon 106 is removed (FIGS. 3B and 7B).

  Subsequently, the base region 107 for the active cell is formed by boron ion implantation and heat treatment, and then the source region 108 is formed by arsenic ion implantation and heat treatment (FIGS. 3C and 7C). Next, BPSG is formed by a CVD method, an interlayer insulating film 109 is formed, a contact hole is formed by selectively etching BPSG by a photolithography technique, and finally aluminum is sputtered on the surface to form a source electrode 110 is formed (FIGS. 4 and 8). A power MOSFET can be manufactured by the process described above.

  4 and 8, in the region where the nitride film 111 is formed on the gate oxide film 105, the insulating film is thicker than the active cell region without the nitride film 111, and the dielectric strength is higher. Accordingly, it is possible to avoid a reduction in the resistance of the gate lead electrode portion.

Further, since the active cell portion has a polysilicon / gate oxide structure, it does not cause deterioration of characteristics. Further, the region where the nitride film 111 is formed on the gate oxide film 105 increases the thickness of the insulating film even when a voltage for forming an inversion layer in the active cell portion and applying an on state is applied. Therefore, if the voltage is not higher than that of the active cell portion, the inversion layer is not formed in the polysilicon portion 106 for the gate lead electrode. Therefore, the threshold voltage as designed depends on the formation of the base region 107. Setting is possible, and it is possible to avoid occurrence of a threshold voltage and a leak that are out of design.
(Embodiment 2)

  9 to 12 and FIGS. 13 to 16 are cross-sectional views for each process order illustrating the second embodiment of the present invention. However, a cross-sectional view of the terminal portion of the gate trench in the Nch power MOSFET is shown. 9 to 12 are A-A ′ cross-sectional views of FIG. 23, and FIGS. 13 to 16 are B-B ′ cross-sectional views of FIG. 23.

  First, a P well layer 202 is selectively formed on a semiconductor substrate 201 by photolithography technique by boron ion implantation and heat treatment (FIGS. 9A and 13A). Next, a PAD portion 203 that becomes a wire arrangement region for the gate lead electrode is formed by LOCOS oxidation (FIGS. 9B and 13B). Next, the gate trench 204 is formed by selectively performing an etching process using a photolithography technique (FIGS. 9C and 13C). Subsequently, an oxide film 211 by a CVD method is formed on the front surface (FIGS. 10A and 14A). Next, the oxide film 211 by the CVD method is selectively etched by a photolithography technique to obtain a target shape (FIGS. 10B and 14B). Subsequently, a gate oxide film 205 is formed on the entire surface by thermal oxidation (FIGS. 10C and 14C).

  Next, polysilicon 206 for the gate lead electrode is formed on the entire surface by the CVD method (FIGS. 11A and 15A). A selective etching process is performed so that the polysilicon 206 is left in the same pattern as the oxide film 211 formed by the above-described CVD method. At this time, the surface portion of the gate oxide film 205 that is not in contact with the polysilicon 206 is removed (FIGS. 11B and 15B).

  Subsequently, the base region 207 for the active cell is formed by boron ion implantation and heat treatment, and then the source region 208 is formed by arsenic ion implantation and heat treatment (FIGS. 11C and 15C). Next, BPSG is formed by a CVD method, an interlayer insulating film 209 is formed, and a contact hole is formed by selectively etching BPSG by a photolithography technique. Finally, aluminum is sputtered on the surface to form a source. The electrode 210 is formed (FIGS. 12 and 16). A power MOSFET can be manufactured by the process described above.

  The second embodiment is the same as that of the first embodiment except that a three-layer structure consisting of a gate lead electrode (polysilicon) / nitride film / gate oxide film is formed by a gate lead electrode (polysilicon) / gate oxide film / CVD method. This is a three-layer structure made of an oxide film. The active cell portion is a gate extraction electrode (polysilicon) / gate oxide film. Also in this method, as in the first embodiment, the structure of the active cell portion is not changed, so that the trench by the improvement of the insulating property is not caused without causing an increase in threshold voltage or an increase in on-resistance. It is possible to improve the resistance of the gate lead-out portion and prevent the formation of the inversion layer in the portion where the polysilicon is overlapped by adding an insulating film.

  It can be widely used for products using power MOSFETs, such as DRAM capacitors, flash memories, FeRAM cells, switches, converters, and the like.

It is sectional drawing for every manufacturing process explaining the semiconductor device of 1st Embodiment of this invention. However, it is A-A 'sectional drawing of FIG. It is sectional drawing for every manufacturing process explaining the semiconductor device of 1st Embodiment of this invention. However, it is A-A 'sectional drawing of FIG. It is sectional drawing for every manufacturing process explaining the semiconductor device of 1st Embodiment of this invention. However, it is A-A 'sectional drawing of FIG. It is sectional drawing for every manufacturing process explaining the semiconductor device of 1st Embodiment of this invention. However, it is A-A 'sectional drawing of FIG. It is sectional drawing for every manufacturing process explaining the semiconductor device of 1st Embodiment of this invention. However, it is a B-B ′ cross-sectional view of FIG. 23. It is sectional drawing for every manufacturing process explaining the semiconductor device of 1st Embodiment of this invention. However, it is a B-B ′ cross-sectional view of FIG. 23. It is sectional drawing for every manufacturing process explaining the semiconductor device of 1st Embodiment of this invention. However, it is a B-B ′ cross-sectional view of FIG. 23. It is sectional drawing for every manufacturing process explaining the semiconductor device of 1st Embodiment of this invention. However, it is a B-B ′ cross-sectional view of FIG. 23. It is sectional drawing for every manufacturing process explaining the semiconductor device of 2nd Embodiment of this invention. However, it is A-A 'sectional drawing of FIG. It is sectional drawing for every manufacturing process explaining the semiconductor device of 2nd Embodiment of this invention. However, it is A-A 'sectional drawing of FIG. It is sectional drawing for every manufacturing process explaining the semiconductor device of 2nd Embodiment of this invention. However, it is A-A 'sectional drawing of FIG. It is sectional drawing for every manufacturing process explaining the semiconductor device of 2nd Embodiment of this invention. However, it is A-A 'sectional drawing of FIG. It is sectional drawing for every manufacturing process explaining the semiconductor device of 2nd Embodiment of this invention. However, it is a B-B ′ cross-sectional view of FIG. 23. It is sectional drawing for every manufacturing process explaining the semiconductor device of 2nd Embodiment of this invention. However, it is a B-B ′ cross-sectional view of FIG. 23. It is sectional drawing for every manufacturing process explaining the semiconductor device of 2nd Embodiment of this invention. However, it is a B-B ′ cross-sectional view of FIG. 23. It is sectional drawing for every manufacturing process explaining the semiconductor device of 2nd Embodiment of this invention. However, it is a B-B ′ cross-sectional view of FIG. 23. It is sectional drawing for every manufacturing process explaining a general semiconductor device. However, it is A-A 'sectional drawing of FIG. It is sectional drawing for every manufacturing process explaining a general semiconductor device. However, it is A-A 'sectional drawing of FIG. It is sectional drawing for every manufacturing process explaining a general semiconductor device. However, it is A-A 'sectional drawing of FIG. It is sectional drawing for every manufacturing process explaining a general semiconductor device. However, it is a B-B ′ cross-sectional view of FIG. 23. It is sectional drawing for every manufacturing process explaining a general semiconductor device. However, it is a B-B ′ cross-sectional view of FIG. 23. It is sectional drawing for every manufacturing process explaining a general semiconductor device. However, it is a B-B ′ cross-sectional view of FIG. 23. It is a partial top view of a common semiconductor device. 10 is a cross-sectional view for each manufacturing process illustrating the semiconductor device of Patent Document 1. FIG. 10 is a cross-sectional view for each manufacturing process illustrating the semiconductor device of Patent Document 1. FIG. 10 is a cross-sectional view for each manufacturing process illustrating the semiconductor device of Patent Document 1. FIG. 10 is a cross-sectional view illustrating a semiconductor device of Patent Document 2. FIG.

Explanation of symbols

511, 101, 201, 301, 401 Semiconductor substrate 102, 202, 302 P well layer 103, 203, 303 PAD portion 104, 204, 304 Gate trench 105, 205, 305 Gate oxide film 106, 206, 306 Polysilicon 107, 207, 307 Base region 108, 208, 308 Source region 109, 209, 309 Interlayer insulating film 110, 210, 310 Source electrode 111 Nitride film 211 Oxide film by CVD method 402 Trench 403 Oxide film 404 Nitride film 405 First polysilicon 406 Recess 407 Intermediate layer 408 Second polysilicon 409 Cell plate 512 Base layer 513 Emitter layer 514a, 514b Trench 515 First oxide film 516 Silicon nitride film 517 First oxide film 518, 520 Gate Insulating film 519 gate 521 gate electrode wirings

Claims (3)

In the vertical MOS semiconductor device having a trench gate composed of two layer structure consisting of polysilicon and gate oxide film, the portion connected to the gate lead-out electrode of the trench gate, polysilicon and nitride film and the gate oxide film A semiconductor device characterized by having a three-layer structure comprising: The arrangement order of the polysilicon and the nitride film and the gate oxide film, the gate oxide film from the semiconductor device substrate, the nitride film, the semiconductor device according to claim 1, characterized in that said polysilicon. The method of manufacturing a vertical type MOS semiconductor device having a trench gate composed of two layer structure consisting of polysilicon and gate oxide film, the portion connected to the gate lead-out electrode of the trench gate, the semiconductor device substrate having a trench Depositing a gate oxide film on the gate oxide film; depositing a nitride film on the gate oxide film deposited in the process; and depositing polysilicon on the nitride film deposited in the process. A method for manufacturing a semiconductor device.

Images