JP2006222714A - Test pattern generator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a test pattern generator capable of displaying a plurality of test patterns on one screen by changing combination of test patterns and a split position for the screen in various ways, when the generator is applied to a test for devices such as a television receiver, a color monitor, a liquid crystal display panel etc.. <P>SOLUTION: The test pattern generator records an image data of a plurality of test patterns for one line, respectively, and holds the data in a pattern data memory 5. According to a counted value by a vertical address counter 2, selected data SEL1 are output from a selection data memory 3. The image data of the test patterns held in the pattern data memory 5 is output selectively so as to rewrite a selected data SEL held in the selection data memory 3. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a test pattern generator, and can be applied to tests of, for example, a television receiver, a color monitor, a liquid crystal display panel, and the like. According to the present invention, image data of a plurality of test patterns is recorded for each line and held in the pattern data memory, and the selection data is output from the selection data memory in accordance with the count value of the vertical address counter to be stored in the pattern data memory. By selecting and outputting the image data of the held test pattern and rewriting the selection data held in the selection data memory, when a plurality of test patterns are displayed on one screen, the combination of test patterns and the division of the screen The position and the like can be changed variously.

  Conventionally, various display devices such as a television receiver, a color monitor, and a liquid crystal display panel are connected to a test pattern generator disclosed in, for example, Japanese Patent Laid-Open No. 6-14349 at the time of shipment from a factory, and gray scales, color bars, etc. Various test patterns are displayed, thereby testing the characteristics of the display.

  For this reason, the test pattern generator records and holds test pattern image data in an image memory of a read-only memory, and reads and outputs the image data.

  By the way, in this type of display device test, for example, a plurality of tests may be executed at a time by dividing the screen vertically and displaying a plurality of test patterns on one screen, thereby improving the efficiency of the test. When displaying a plurality of test patterns on such a single screen, it is required to variously change the combination of the test patterns, the division position of the screen, and the like according to the test target.

However, the conventional test pattern generator can only display an image based on the fixed pattern recorded in the image memory. Thus, when displaying a plurality of test patterns on one screen in this way, the combination of test patterns, the screen There is a problem that it is difficult to change the division position and the like in various ways.
JP-A-6-14349

  The present invention has been made in consideration of the above points, and in the case where a plurality of test patterns are displayed on one screen, a test pattern generating apparatus capable of variously changing the combination of test patterns, the division position of the screen, and the like. Is to try to propose.

  In order to solve such a problem, the invention of claim 1 is applied to a test pattern generator, a vertical address counter for resetting a count value by a horizontal synchronizing signal and counting a vertical synchronizing signal, and a selection for selecting a test pattern A selection data memory that holds data and outputs the selection data according to a count value of the vertical address counter; a horizontal address counter that resets the count value by the horizontal synchronization signal and counts a clock; and a plurality of test patterns The image data of one line is recorded and held for each line, and the test pattern image data specified by the selection data is output according to the count value of the horizontal address counter, and recorded in the selection data memory Update circuit to rewrite the selected data Obtain so.

  According to a second aspect of the present invention, in the configuration of the first aspect, the update circuit rewrites the selection data loaded in the work memory after loading the selection data recorded in the selection data memory into the work memory. From the working memory according to the count value of the vertical address counter until the data is recorded again in the selected data memory, loaded into the working memory, and re-recorded in the selected data memory. The selection data is output, and image data is output from the pattern data memory according to selection data output from the working memory instead of the selection data from the selection data memory.

  According to the configuration of the first aspect of the present invention, the present invention is applied to a test pattern generation device, resets a count value by a vertical synchronization signal, holds a vertical address counter for counting a horizontal synchronization signal, and selection data for selecting a test pattern, and A selection data memory that outputs the selection data according to the count value of the address counter, a horizontal address counter that resets the count value by the horizontal synchronization signal and counts the clock, and one line each of image data of a plurality of test patterns A pattern data memory for recording and holding the data, and outputting image data of a test pattern specified by the selection data in accordance with a count value of the horizontal address counter, and an update circuit for rewriting the selection data recorded in the selection data memory If you prepare It is possible to display a plurality of test patterns on one screen by setting the selected data recorded in the memory. In addition, by rewriting the selection data recorded in the selection data memory by the update circuit as necessary, a plurality of test patterns can be displayed on one screen in this way, and various combinations of test patterns, division positions of the screen, etc. Can be changed.

  According to the configuration of claim 2, in the configuration of claim 1, the update circuit rewrites the selection data loaded in the working memory after loading the selection data recorded in the selection data memory into the working memory. After the data is re-recorded in the selection data memory, the selection data is loaded into the work memory, and is recorded again in the selection data memory, the work memory stores the selection data according to the count value of the vertical address counter. If selection data is output and image data is output from the pattern data memory in accordance with selection data output from the working memory instead of selection data from the selection data memory, a combination of test patterns and screen division While confirming the position, etc., these can be changed in various ways, and the work efficiency can be improved accordingly. It can be.

  According to the present invention, when a plurality of test patterns are displayed on one screen, the combination of test patterns, the division position of the screen, and the like can be variously changed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings as appropriate.

(1) Configuration of Embodiment FIG. 1 is a block diagram showing a test pattern generator according to an embodiment of the present invention. In the test pattern generator 1, the vertical address counter 2 resets the count value by the vertical synchronization signal of the intra-station synchronization signal, and counts the horizontal synchronization signal of the intra-station synchronization signal.

  The selection data memory 3 is a rewritable memory that holds selection data SEL for selecting a test pattern for display, and is formed by, for example, a flash ROM. The selection data memory 3 outputs selection data SEL1 held according to the count value of the vertical address counter 2.

  The selector 4 outputs the selection data SEL1 output from the selection data memory 3 to the pattern data memory 5 in the normal operation mode. Under the control of the test pattern update circuit 6, the selector 4 patterns the selection data SEL2 output from the test pattern update circuit 6 instead of the selection data SEL1 output from the selection data memory 3 in the test pattern update mode. Output to the data memory 5.

  The horizontal address counter 7 resets the horizontal synchronization signal count value of the intra-station synchronization signal and counts the clock of the intra-station synchronization signal.

  The pattern data memory 5 is a memory that holds image data of a plurality of types of test patterns for each line, and is formed by a flash ROM, for example. The pattern data memory 5 sequentially outputs the image data of the test pattern selected by the selection data SEL output from the selector 4 according to the count value of the horizontal address counter 7.

  As a result, the test pattern generator 1 can display a desired test pattern according to the selection data SEL1 held in the selection data memory 3 in the normal operation mode. The selection data SEL1 is set in the selection data memory 3 so as to select the color bar and grayscale image data held in the pattern data memory 5 in half, and a plurality of test patterns by these color bars and grayscale are set to 1 It can be displayed on the screen.

  The test pattern update circuit 6 switches the entire operation mode to the update mode in response to an operation by the operator, and updates the selection data SEL1 held in the selection data memory 3.

  That is, in the test pattern update circuit 6, the working memory 12 is formed by a rewritable memory having a high writing / reading speed, and is formed by a DPRAM in this embodiment. The working memory 12 outputs selection data SEL2 held in accordance with the count value of the vertical address counter 2.

  The controller 11 is a control means for controlling the entire operation of the test pattern generator 1 and switches the entire operation mode to the update mode in response to an operation by the operator, and selects the selection data SEL1 recorded in the selection data memory 3. Update.

  Here, FIG. 2 is a flowchart showing a processing procedure of the controller 11 in the update mode. When the controller 11 switches the operation mode to the update mode, the controller 11 starts this processing procedure and proceeds from step SP1 to step SP2. Here, the controller 11 loads the selection data SEL1 recorded in the selection data memory 3 into the work memory 12, and then starts up the operation of the work memory 12.

  In the subsequent step SP3, the setting of the selector 4 is switched so that, instead of the selection data SEL1 recorded in the selection data memory 3, the image held in the pattern data memory 5 by the selection data SEL2 stored in the work memory 12 Select the data and display the test pattern.

  Subsequently, the controller 11 proceeds to step SP4, where the selection data SEL2 stored in the work memory 12 is updated according to the operation of the operator. Specifically, when the operator instructs to display one test pattern on the entire screen, the image data of this one test pattern is selected with all the count values output from the vertical address counter 2. Selection data SEL2 is set. In addition, when instructed to display the first and second test patterns in the upper half and the lower half of one screen, respectively, the upper half and the lower half of one screen are respectively displayed according to the count value output from the vertical address counter 2. Selection data SEL2 is set so as to select the image data of the first and second test patterns. When the user instructs display of a plurality of types of test patterns in which one screen is divided into four for the vertical direction, the selection data SEL2 is set in the same manner. Further, when the change of the boundary relating to the display of the plurality of test patterns is instructed, the selection data SEL2 is updated so as to correspond to the instruction of the change.

  When the controller 11 updates the selection data SEL2 in this way, the process proceeds to step SP5, where it is determined whether or not the operator has instructed the end of the update mode. If a negative result is obtained here, the process returns to step SP4. . On the other hand, if an affirmative result is obtained in step SP5, the process proceeds from step SP5 to step SP6, and the selection data recorded in the working memory 12 is uploaded to the selection data memory 3, whereby the contents of the selection data memory 3 are updated. Update.

  In subsequent step SP7, the setting of the selector 4 is returned to the original state, and the process proceeds to step SP8 to end the processing procedure.

(2) Operation of the embodiment In the above-described configuration, in the test pattern generator 1, the horizontal address signal is counted by the vertical address counter 2, and the selection for specifying the test pattern from the selection data memory 3 according to the count value Data SEL1 is output. Further, the horizontal address counter 7 counts the clock, and the image data of the test pattern specified by the selection data SEL is received from the pattern data memory 5 holding image data of a plurality of types of test patterns for each line. Are sequentially output according to the count value.

  Thereby, in this test pattern generation device 1, for example, by selecting the selection data SEL1 of the selection data memory 3 for all count values by the vertical address counter 2 so as to specify one test pattern, one test pattern is displayed on one screen. One desired test pattern can be displayed. Instead of this, the selection data SEL1 of the selection data memory 3 is set for the count value by the vertical address counter 2 so that the first and second test patterns are specified in the upper half and the lower half of the screen, respectively. Thus, the first and second test patterns can be displayed at the top and bottom of the screen, respectively, and the boundary between the first and second test patterns can be set at a desired location.

  Thus, in the test pattern generator 1, when the operation mode is switched to the update mode by the operator, the selection data SEL1 held in the selection data memory 3 is rewritten by the test pattern update circuit 6. Thereby, in this test pattern generator 1, when a plurality of test patterns are displayed on one screen, the combination of test patterns, the division position of the screen, and the like can be variously changed.

  In the test pattern generation device 1, in this update mode, the selection data SEL 1 held in the selection data memory 3 is temporarily loaded into the work memory 12 having an operation speed higher than that of the selection data memory 3. After the selection data SEL1 is updated, it is uploaded to the selection data memory 3 and updated. In the series of operations, the selector 4 switches the input of the pattern data memory 5 so that the test pattern is displayed by the selection data SEL2 loaded in the working memory 12.

  As a result, the test pattern generator 1 can update the selection data while checking the update result of the selection data on the display device, and can efficiently perform the work related to the update of the selection data accordingly. .

(3) Advantages of the embodiment According to the above configuration, the image data of a plurality of test patterns is recorded for one line, held in the pattern data memory, and selected from the selection data memory according to the count value of the vertical address counter. When a plurality of test patterns are displayed on one screen by rewriting the selection data held in the selection data memory by outputting the data and selectively outputting the test pattern image data held in the pattern data memory In addition, combinations of test patterns, screen division positions, and the like can be variously changed.

  In updating the selection data, after the selection data recorded in the selection data memory is loaded into the working memory, the selection data is rewritten on the working memory and re-recorded in the selection data memory. In the meantime, by displaying the test pattern with the selection data of the working memory, it is possible to change the selection data in various ways while confirming the combination of the test patterns, the division position of the screen, and so on. The work efficiency can be improved.

  In the above-described embodiment, the case has been described in which the update data can be monitored in real time by loading the selection data recorded in the selection data memory into the working memory and updating it. Not limited to this, a memory having a high operating speed may be applied to the selected data memory, and the update result may be directly updated on the selected data memory while being monitored in real time.

  The present invention can be applied to a test of, for example, a television receiver, a color monitor, a liquid crystal display panel, and the like.

It is a block diagram which shows the test pattern generator which concerns on the Example of this invention. It is a flowchart which shows the process sequence of the controller of the test pattern generator of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Test pattern generator, 2 ... Vertical address counter, 3 ... Selection data memory, 4 ... Selector, 5 ... Pattern data memory, 6 ... Test pattern update circuit, 7 ... Horizontal address counter, 11 ...... Controller, 12 ... Work memory

Claims (2)

A vertical address counter that resets a count value by a vertical synchronization signal and counts a horizontal synchronization signal;
A selection data memory for holding selection data for selecting a test pattern and outputting the selection data in accordance with a count value of the vertical address counter;
A horizontal address counter that resets a count value by the horizontal synchronization signal and counts a clock;
A pattern data memory that records and holds image data of a plurality of test patterns for one line, and outputs image data of the test pattern specified by the selection data in accordance with a count value of the horizontal address counter;
An update circuit for rewriting selection data recorded in the selection data memory. The update circuit includes:
After loading the selection data recorded in the selection data memory into the working memory, rewriting the selection data loaded in the working memory and re-recording in the selection data memory,
After loading the selection data into the working memory and before re-recording in the selection data memory,
The selection data is output from the working memory in accordance with the count value of the vertical address counter, and the pattern data memory is replaced with the selection data output from the working memory instead of the selection data from the selection data memory. The test pattern generator according to claim 1, wherein image data is output from

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