JP4455409B2 - Scanning circuit and control method thereof - Google Patents

Description

  The present invention relates to a scanning circuit and a control method thereof, and more particularly, to a scanning circuit suitable for use in an imaging system and a control method thereof.

  The CMOS image sensor has an advantage over the CCD in that random access is possible. For example, in the following Patent Document 1, random access is realized by using a decoder for row access.

  However, in order to actually enable random access, it is necessary to configure the address decoder 101 as shown in FIG. However, when configured with a decoder, for example, when selecting a pixel group row or row indicated by a square for an image sensor of 2000 rows and 2000 columns, a decoder circuit 102 that decodes a signal of 11 bits each is provided. It is necessary to prepare, and it is not realistic as a circuit scale. In addition, peripheral circuits such as a counter 103 for controlling the decoder and an address pointer 104 for random addresses are required, leading to an increase in chip area.

US Pat. No. 5,841,126 JP-A-5-227486

  In actual use, there are almost no scenes where the image sensor requires random access. In the act of photographing, since the order of acquiring and outputting data is almost determined, such as from top to bottom and from right to left, the operation of “scanning” is preferred instead of random access. For example, as described in Patent Document 2 above, scanning in the vertical direction and the horizontal direction is performed using a shift register using the configuration shown in FIG.

  Since a shift register is used, after accessing a certain row / column, it is necessary to access the next row / column. For example, in FIG. 2, Scan2 is output at the second stage 201 of the shift register, and after accessing the block, the shift pulse is input at the shift pulse input 202 and Scan3 is output from the third stage 203 of the shift register.

  Here, for example, if you want to skip every other row and access, if you skip one column, you want to skip the next two columns. Or, even if there is a request to read the upper quarter and lower quarter, the current problem is that all rows or columns must be accessed. .

  SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to propose a scanning circuit capable of skipping an arbitrary row and column and a control method thereof, while incorporating a means suitable for imaging called “scanning” of a shift register. To do.

The scanning circuit of the present invention includes a plurality of registers connected in series to form a shift register, a plurality of state memories that store states corresponding to each of the plurality of registers, and the plurality of registers. A plurality of bypass circuits for bypassing, each bypass circuit bypassing the corresponding register according to the storage state of the state memory of the corresponding register, and the state memory And a selection circuit for selecting one output from the plurality of state memories .

The scanning circuit control method of the present invention includes a plurality of registers connected in series to form a shift register, a plurality of state memories storing states corresponding to each of the plurality of registers, and the plurality of the plurality of registers. have a plurality of bypass circuits to bypass the register respectively, the state memory, a control method of a scanning circuit for chromatic two or more per the register one, the one of the plurality of status memory selecting an output, each of the bypass circuits according to the storage state of state memory of the corresponding registers thereto, characterized by a step of bypassing the register corresponding thereto.

  Arbitrary rows or columns can be skipped while adopting a means suitable for imaging called shift register scanning.

(First embodiment)
A first embodiment of the present invention will be described. FIG. 3 is a circuit in which one stage of the register of the shift register is extracted as an example constituting the scanning circuit of this embodiment. Reference numeral 301 denotes a main flip-flop that constitutes a register that controls scanning. Reference numeral 302 denotes a flip-flop for state storage that stores the state and function of the stage. Reference numerals 303 and 304 denote combinational logic circuits for switching paths, which respectively input values from the circuit 309 and values from the logic circuits 305 and 306. The circuit 309 outputs the output signal Q of the flip-flop 302 when 1 is input, and outputs 1 (high level) when 0 is input. The flip-flop 302 outputs the value of its own state storage element. The logic circuits 305 and 306 receive the output from the adjacent state storage element and the output of its own state storage element and detect a change in the memory value of the state storage element. Here, reference numeral 303 denotes a circuit that controls the input of the register 301. The input of the register 301 is fixed to a low level, the output 307 from the previous shift register is received, or the output 308 that bypasses the previous shift register. Control what you receive. In addition, 304 selects whether to connect the output 307 from the preceding shift register to the bypass input unit in the next stage or to receive the value 308 from the bypass in the previous stage.

  Reference numeral 309 denotes a circuit for taking over the output at a high level while retaining the contents of the state storage element. This circuit operates as a normal shift register when all the outputs of the state storage elements are at a high level. For example, when switching to normal shift register operation, the equivalent function can be realized instantaneously by controlling 309 and handling as if a high level is output from the state storage element without clearing the state memory. Become.

  When a plurality of stages of the shift register in FIG. 3 are connected, the shift register scanning circuit in FIG. 4 is configured. In FIG. 3, the flip-flop 302 means that the shift of the shift register 301 is invalidated and skipped when storing 0, and the shift of the shift register 301 is enabled when 1 is stored. When 1 is input to the circuit 309, the shift register 301 is shifted according to the storage state of the flip-flop 302, and when 0 is input, the shift register 301 is always shifted regardless of the storage state of the flip-flop 302. That is, when 0 is input to the circuit 309, the shift register in FIG. 4 operates as a normal shift register. The circuit 309 outputs the output signal Q of the flip-flop 302 when 1 is input, and outputs 1 (high level) when 0 is input. As shown in FIG. 4, the 10 detection circuit 306 detects that “10” is detected when the output signal of the preceding stage circuit 309 is “1” and the output signal of the circuit 309 of its own stage is “0”. Is output. As shown in FIG. 4, the 01 detection circuit 305 detects that “01” is detected when the output signal of the previous stage circuit 309 is 0 and the output signal of its own stage circuit 309 is “1”. Is output. A signal 307 is an output signal of the preceding flip-flop 301. A signal 308 is an output signal of the circuit 304 in the previous stage. The logic circuit 304 outputs a signal 307 when a high level is input from the 10 detection circuit 306, otherwise outputs a signal 308 when the output signal of the circuit 309 is 0, and outputs a signal 308 when the output signal of the circuit 309 is 1. Put the output in a high impedance state. The logic circuit 303 outputs a signal 308 when a high level is input from the 01 detection circuit 305, otherwise outputs a signal 307 when the output signal of the circuit 309 is 1, and outputs a signal 307 when the output signal of the circuit 309 is 0. Outputs 0 (ground: low level). The flip-flop 301 latches and stores the input signal D in synchronization with the clock, and outputs the stored signal as the output signal Q.

  Next, an example of a specific operation will be described with reference to FIG. A shift register start signal is given from 401, and it is assumed that a pattern such as “01101” is given to the state memory group 402 at that time. Here, 0 is “skip”, and 1 is “shift by shift register”. The state memory group 402 is a shift register. First, the circuit 403 detects zero from the state memory 302 and allows data to pass through the bypass. At that time, in the circuit 404, a low level is input to the flip-flop 301 in order to deactivate the input of the shift register 301. The output signal Q of the flip-flop 301 becomes zero.

  Next, in the next-stage circuit 405, the output of the high-impedance state is detected in order to detect 0 in the previous-stage state memory 302 and 1 in its own state memory 302 and connect the skip path to the original path. To. The circuit 406 detects 0 in the previous state memory 302 and 1 in its own state memory, and outputs a signal 308 from the previous bypass.

  In the next-stage shift register circuit 407, 1 in its own state memory 302 is detected, the bypass path is cut off, and the output becomes high impedance. The circuit 408 detects 1 in its own state memory 302 and changes the connection so as to output the signal 307 of the preceding shift register.

  In the next stage circuit 409, 1 in the previous state memory 302 and 0 in its own state memory 302 are detected, and in order to validate the path from the shift register to the bypass, the signal 307 of the previous stage shift register is used. Output. At the same time, the circuit 410 detects 0 in its own state memory 302, and the shift register 301 is no longer operated, so its output is fixed at a low level. The output signal Q of the shift register 301 becomes 0 (low level).

  In the last stage, detection of 0 in the state memory 302 in the previous stage and detection of 1 in its own state memory 302 is the same as the above-described operation, and therefore the description thereof is omitted. The output of the special shift register 301 becomes the output of the scanning circuit.

  309 in FIG. 3 is a circuit for taking over (invalidating) the output of the status register 302. When 0 is input to the circuit 309, all stages of the circuit 309 output 1. Then, the circuits 304 in all stages set the output to a high impedance state, and the circuits 303 in all stages output the signal 307 of the preceding shift register. As a result, the shift registers 301 at all stages are enabled and operate as normal shift registers. That is, the shift register 301 group shifts the output to the next stage in synchronization with the clock.

  As described above, the plurality of registers 301 are connected in series to form a shift register. The plurality of state memories 302 store a state corresponding to each of the plurality of registers 301. The circuits 303 to 306 constitute a bypass circuit. The plurality of bypass circuits 303 to 306 are circuits for bypassing the plurality of registers 301 respectively. Each bypass circuit 303 to 306 bypasses the corresponding register according to the storage state of the state memory 302 of the register 301 corresponding thereto.

  When each bypass circuit 303 to 306 bypasses the corresponding register 301, the output Q of the corresponding register 301 is set to a fixed value (for example, 0) while holding the storage state of the corresponding state memory 302 of the register 301. To.

  The state memory 301 stores a state as to whether or not the corresponding register 301 is bypassed. 1 indicates a state in which bypassing is not performed, and 0 indicates a state in which bypassing is performed. Each bypass circuit 303 to 306 bypasses the corresponding register 301 and sets the output of the corresponding register 301 to a fixed value when the state memory 302 of the corresponding register 301 stores a bypass state.

  Each of the bypass circuits 303 to 306 stores a state in which the state memory 302 of the register 301 corresponding thereto does not bypass, and stores a state in which the state memory 302 of the preceding register 301 does not bypass, The output 307 of the preceding register 301 is input.

  Each of the bypass circuits 303 to 306 stores a state in which the state memory 302 of the register 301 corresponding to the bypass circuit 303 does not bypass and stores a state in which the state memory 302 of the register 301 in the previous stage bypasses the register 301 corresponding thereto. A signal 308 that bypasses the preceding register 301 is input.

  Each of the plurality of state memories 302 has a shift register configuration connected in series, and sets a state in synchronization with one scanning cycle and sets a state in a non-scanning period.

  The effect of the present embodiment is obvious, and a circuit that can freely set which path the data passes through by arranging the bypass and the original path in parallel, and instructing the state storage element 302 to perform the instruction. This makes it possible to skip and cut out in arbitrary patterns using shift registers, which was impossible until now.

  Here, in this circuit example, the example in which the number of stages is five has been described, but the present invention is not limited to this example, and any number of stages may be provided.

  In the present circuit example, the state storage element 302 is constituted by a shift register. A value can be written to the shift register at a timing desired by the user, for example, at the time of initialization of the shift register or once after scanning. It is also possible to shift the selected window and skip pattern by using a value shift function which is a feature of the shift register. Although this circuit example can only shift in one direction, a shift register capable of shifting in both directions existing in the world may be used.

  In addition, when the area allocated to the state memory element is small, or when the frequency of rewriting the state memory element may be small, an SRAM or a nonvolatile memory may be used instead of the shift register. There are many means for transmitting the write control signal to the SRAM or the nonvolatile memory. However, in the present invention, the value to be written to the SRAM or the nonvolatile memory is stored in the shift register used for the scanning operation, and then the stored data is stored. By storing the data in the SRAM or the nonvolatile memory, a decoder dedicated to the state storage element can be omitted, and the area can be saved.

  In addition, when it is not necessary to rewrite the state memory element, that is, when only the entire row scan and switching of a certain pattern are performed, the area of the circuit can be reduced by making the state memory element ROM. . In addition, when there are a plurality of the aforementioned predetermined patterns, a plurality of ROMs are provided for each stage of the shift register, and by controlling from the outside which ROM controls the skip operation of the shift register, a plurality of the predetermined patterns can be obtained. Scanning can be realized.

  Even when a rewritable state memory element such as a shift register, SRAM, or non-volatile memory is used, a plurality of state memory elements are provided for each stage of the shift register to determine which element operates. By controlling, the skip pattern can be changed instantaneously, and the pattern can be changed even when there is no rewriting time of the skip pattern.

  Further, the circuit 309 can be omitted when the operation for taking over the output of the status register 302 is not required.

  It should also be noted here that the information “01101” stored in the state memory element group 402 is information that is skipped or not. Therefore, for example, by decoding the value of zero in the status register and using that value for control, special processing limited to skipped blocks can be performed.

(Second Embodiment)
A second embodiment of the present invention will be described with reference to FIG. The flip-flop group 402 including a plurality of state memories 302 is connected to a common bus line via a plurality of selection switches 501. The first embodiment has a shift register configuration, and a predetermined shift is required for initialization. In the present embodiment, since the flip-flop group 402 can be randomly accessed via the selection switch 501, a part of the flip-flop group 402 can be rewritten at once.

  According to the present embodiment, in addition to the effect that arbitrary skipping is possible, the effect that the degree of freedom of the state register initialization method is increased can be obtained.

  As described above, according to the first and second embodiments, in the scanning circuit that controls the scanning by the shift register, each register constituting the shift register is a state memory and a circuit that bypasses each register. And a circuit for changing the input / output of each register and the input / output of the bypass according to the contents of the state memory and the contents of the state memory of an adjacent register.

  A scanning circuit capable of skipping an arbitrary row and column while incorporating a means suitable for imaging called “scanning” of a shift register is realized. In other words, the path bypass at any position of the shift register and the bypass release can be performed, and a scanning circuit capable of any skipping requested by the user can be realized.

  The scanning circuit is characterized in that it has a circuit that changes the output to a specified value while retaining the contents of the state memory. According to such a scanning circuit, for example, when the skip is canceled for a moment and it is desired to perform the skip immediately thereafter, it is not necessary to clear the state memory, so that a high-speed state change and a state return are possible.

  Further, according to the scanning circuit, each register of the shift register is connected to a decoder circuit, and an output of the state memory is connected to the decoder circuit. According to such a scanning circuit, a scanning signal can be generated using not only the shift signal but also the value of the state memory. For example, a circuit that performs control peculiar to a row / column to be skipped and a row / column to be skipped Can be realized.

  Further, according to the scanning circuit, the state memory constituting each register has a shift register configuration. According to such a scanning circuit, the circuit required for initializing the state memory can be drastically reduced, leading to a reduction in chip area.

  According to the scanning circuit, the shift register constituting the state memory is controlled in synchronization with one scanning cycle of the scanning circuit. According to such a scanning circuit driving method, the skip pattern can be changed every other scan, and can be used, for example, for moving the scanning window.

  Further, according to the above scanning circuit, the input of the state memory constituting each of the registers is connected to a common bus line. According to such a scanning circuit, an arbitrary state memory can be changed in an arbitrary order, and flexible setting becomes possible.

  According to the scanning circuit driving method, the shift register constituting the state memory is initially set in a non-scanning period. According to such a driving method of the scanning circuit, the state memory can be initialized without affecting the present operation such as imaging.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

It is a figure for demonstrating a prior art example. It is a figure for demonstrating a prior art example. It is a figure explaining the shift register stage by 1st Embodiment. It is a figure explaining the scanning circuit by 1st Embodiment. It is a figure explaining the scanning circuit by 2nd Embodiment.

Explanation of symbols

301 Register 302 State Memory 303, 304, 309 Switching Circuit 305 01 Detection Circuit 306 10 Detection Circuit 307 Register Output Signal 308 Bypass Signal 401 Shift Register Start Signal Terminal 402 State Memory Group 403-410 Bypass Circuit

Claims (14)

A plurality of registers connected in series to form a shift register;
A plurality of state memories storing states corresponding to each of the plurality of registers;
A plurality of bypass circuits for bypassing each of the plurality of registers,
Each of the bypass circuits bypasses the corresponding register according to the storage state of the corresponding state memory of the register ,
2. A scanning circuit comprising two or more state memories per register and a selection circuit for selecting one output of the plurality of state memories .   2. The bypass circuit according to claim 1, wherein when each of the bypass circuits bypasses the corresponding register, the output of the corresponding register is set to a fixed value while holding the storage state of the corresponding state memory of the register. Scanning circuit. The state memory stores a state whether or not to bypass the corresponding register,
3. The bypass circuit according to claim 2, wherein when the state memory of the corresponding register stores a state to be bypassed, the bypass circuit bypasses the corresponding register and sets the output of the corresponding register to a fixed value. Scanning circuit.   Each bypass circuit stores a state in which the state memory of the corresponding register does not bypass, and when the state memory of the register in the previous stage stores a state in which it does not bypass, the output of the register in the previous stage is stored in the corresponding register. 4. The scanning circuit according to claim 3, wherein the scanning circuit is inputted.   Each bypass circuit stores a state in which the state memory of the corresponding register does not bypass, and when the state memory of the register in the previous stage stores a state in which it bypasses, the register in the previous stage is bypassed to the corresponding register. 5. The scanning circuit according to claim 4, wherein a signal is input.   6. The scanning circuit according to claim 1, wherein each of the plurality of state memories has a shift register configuration connected in series.   The scanning circuit according to claim 1, wherein the state memory includes an SRAM.   The scanning circuit according to claim 1, wherein the state memory is configured by a nonvolatile memory.   9. The scanning circuit according to claim 7, wherein the same shift register is used for an operation of transmitting data to be written to the state memory and a normal scanning operation.   7. The scanning circuit according to claim 6, wherein the plurality of state memories set states in synchronization with one scanning cycle.   The scanning circuit according to claim 6, wherein the plurality of state memories set states in a non-scanning period.   6. The scanning circuit according to claim 1, wherein inputs of the plurality of state memories are connected to a common bus line through a plurality of switches, respectively.   The scanning circuit according to claim 1, wherein the state memory includes a ROM. A plurality of registers connected in series to form a shift register, a plurality of state memories for storing states corresponding to each of the plurality of registers, and a plurality of bypasses for bypassing each of the plurality of registers possess a circuit, the state memory, a control method of a scanning circuit for chromatic two or more per the register one,
Selecting one output of the plurality of state memories;
Wherein each bypass circuit, according to the storage state of the state memory of the corresponding register therewith, the control method of the scanning circuit, characterized in that it comprises a <br/> the step of bypassing the register corresponding thereto.

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