JP2006221579A - Reference current generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To generate accurate reference current, without using external resistors in a reference current generation circuit. <P>SOLUTION: Current ratio is amplified by connecting current mirror circuits in multiple stages. A transistor Q1 supplies a collector current I<SB>CQ1</SB>to the input side transistor Q2 of a current mirror circuit of a 1st stage. The current, inputted into an emitter of Q1, suffers a loss in the base current I<SB>BQ1</SB>of Q1 and the remainder becomes I<SB>CQ1</SB>. The base of transistor Q12, in which a current according to I<SB>CQ1</SB>flows, is connected to a collector of Q2, a collector current I<SB>CQ2</SB>of Q2 is compensated by its base current I<SB>BQ12</SB>and fluctuation is suppressed. Here, h<SB>FE</SB>of the Q12 is constituted identical to that of Q1. Accordingly, I<SB>BQ12</SB>can suitably compensate for the fluctuations in I<SB>CQ1</SB>, corresponding to the variations in h<SB>FE</SB>. Q11 is set to pass the current which is obtained by multiplying I<SB>CQ1</SB>by an appropriate scale factor by means of a current mirror circuit structure, and the current is supplied to Q12. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a reference current generation circuit that generates a predetermined current as a reference, and more particularly to improvement in accuracy thereof.

  FIG. 3 is a circuit diagram showing a configuration of a conventional circuit that generates a predetermined current (reference current) that is used as a reference in the operation of the electronic circuit. The main part of this circuit constitutes a semiconductor element integrated on a semiconductor substrate. The circuit includes a ground GND that supplies a ground potential and Vcc that supplies a positive voltage as a power source. The voltage is divided by resistors R1 and R2 connected in series between Vcc and GND, and the voltage at the connection point of these resistors is set as the input voltage Vin. The input voltage Vin is applied to the base of the transistor Q1 through the operational amplifier A. The operational amplifier A is provided for impedance conversion. The emitter of the transistor Q1 is connected to a terminal (pin) N of the semiconductor element. A resistor Rr is connected between the terminal N and GND. A collector current I determined by Vin and the external resistor Rr flows through the transistor Q1.

  The transistor Q2 whose channel is connected between the collector of Q1 and Vcc constitutes a current mirror circuit together with the transistor Q3. Q3 has its emitter connected to Vcc. A transistor Q4 having a channel connected between the collector of Q3 and GND forms a current mirror circuit together with the transistor Q5. Q5 has an emitter connected to GND and a collector connected to an output terminal OUT, from which an output current is taken. For example, these current mirror circuits can amplify the collector current I of Q1 at a predetermined current ratio.

  In the conventional circuit described above, the current I is determined according to the resistor Rr externally attached to the terminal N. Therefore, the accuracy of the reference current is affected according to the accuracy of the resistor Rr. The external resistor Rr has a relatively large variation, and it is difficult to set the resistance value with high accuracy. Therefore, it is difficult to generate a reference current with high accuracy.

  Further, there is a problem that the number of terminals of the semiconductor element is increased by the number of terminals of the external resistor, and the size reduction of the semiconductor element is restricted.

  The present invention has been made to solve the above-described problems, and can generate a reference current with high accuracy without using an external resistor and can reduce the element size. The purpose is to provide.

Reference current generating circuit according to the present invention, a transistor Q _S to flow a current I corresponding to the control voltage applied to the base, made from the current mirror circuit of n stages (n ≧ 1), the current mirror of the first stage It includes transistors Q _M of input current connected to the transistor Q _S as a transistor in the circuit according to the current I flows, a current mirror portion for outputting a reference current corresponding to the current I, the k of the current mirror portion stage (1 ≦ k ≦ n) of the the compensating current mirror circuit that share the current mirror circuit and one of the transistors, the other transistor Q _C1 emitter mutually the compensating current mirror circuit - connecting the collector in the series Transistor Q _C2, and the transistor Q _C2 has a base corresponding to the base current of the transistor Q _S. Are combined in the input current to a chromatography scan current is caused to compensating for the base current supplied to the transistor Q _M.

In the reference current generating circuit according to another present invention, the transistor Q _C2 is set to the transistor Q _S and common current amplification factor h _FE.

In the reference current generating circuit according to another present invention, the transistor channel current of Q _C2 is, the current amplification factor h _FE and the compensation for the base current and the current corresponding to the variations in temperature of a predetermined variation range With respect to each variation of I, the compensation base current is set to vary within a range corresponding to the variation range of the current I.

Further reference current generating circuit according to another present invention, the emitter of the transistor Q _C2 - collector current, the current ratio of the current mirror circuit from the first stage of the current mirror portion to the (k-1) stage and It is adjusted by the current ratio of the compensating current mirror circuit.

According to a preferred aspect of the present invention, one terminal of the transistor Q _S , the transistors constituting the even-numbered current mirror circuit, and the emitter and collector of each of the transistors Q _C1 is connected to a first power supply, and the odd-numbered stages One terminal of the emitter and the collector of each of the transistors constituting the current mirror circuit and the transistor Q _C2 is connected to a second power source, and the base of the transistor Q _C1 is the current mirror of any even stage. is connected to the base of the transistor constituting the circuit, the base of the transistor Q _C2 is, the transistor Q with an emitter and the other terminal of the collector of _S, the transistor Q of the input side path of the current mirror circuit of the first stage the other terminal of the emitter and collector of _M A reference current generating circuit to be continued.

According to the present invention, since the external resistor is not used, a reduction in accuracy due to variations in the resistance value of the external resistor is avoided, and the number of terminals when configured as a semiconductor element is suppressed, and the element The size can be reduced. Furthermore, to compensate for the variations caused by the base current in the transistor Q _S that generates the underlying current I of the reference current, the reference current accuracy is improved is produced.

[Basic configuration]
Prior to description of an embodiment of the present invention (hereinafter referred to as an embodiment), a basic configuration serving as a basis thereof will be described with reference to the drawings.

  FIG. 1 is a schematic circuit diagram showing an example of the basic configuration. This circuit is formed as an integrated circuit on a semiconductor substrate. The circuit includes a ground GND that supplies a ground potential and Vcc that supplies a positive voltage as a power source. A voltage is divided by resistors R1 and R2 connected in series between Vcc and GND, and a voltage V1 at a connection point of these resistors becomes a control voltage for determining a reference current. The voltage V1 is applied to the base of the NPN transistor Q1. The emitter of transistor Q1 is connected to Vcc through resistor R3. On the other hand, the collector of Q1 is connected to the collector of transistor Q2.

PNP transistors Q2, Q3, and Q4 constitute a first stage current mirror circuit, Q2 constitutes an input side path, and Q4 constitutes an output side path. The emitters of Q2 and Q4 are connected to GND and their bases are connected to each other. This base is connected to the emitter of Q3, the base of Q3 is connected to the collector of Q1, and the collector of Q3 is connected to Vcc. Q3 is turned on, whereby Q2 and Q4 are also turned on. For example, here, the current ratio between Q2 and Q4 is set to 1: 1, and a current equivalent to the collector current _{ICQ2 of} Q2 flows through the collector of Q4. The collector of Q4 is connected to the collector of transistor Q5.

NPN transistors Q5, Q6, and Q7 constitute a second-stage current mirror circuit, Q5 constitutes an input side path, and Q7 constitutes an output side path. The emitters of Q5 and Q7 are connected to Vcc and their bases are connected to each other. This base is connected to the emitter of Q6, the base of Q6 is connected to the collector of Q4, and the collector of Q6 is connected to GND. Q6 is turned on, whereby Q5 and Q7 are also turned on. For example, here, the current ratio between Q5 and Q7 is set to 1: 8, and a current _obtained by _multiplying the collector current _{ICQ5 of} Q5 by 8 flows through the collector of Q7. The collector current of Q7 is input to the current variable circuit.

  The current variable circuit outputs a current I2 obtained by multiplying the input current by a. The output of the current variable circuit is connected to the collector of the transistor Q8.

The PNP transistors Q8, Q9, and Q10 constitute a third-stage current mirror circuit, with Q8 constituting the input side path and Q10 constituting the output side path. The emitters of Q8 and Q10 are connected to GND and their bases are connected to each other. This base is connected to the emitter of Q9, the base of Q9 is connected to the collector of Q8, and the collector of Q9 is connected to Vcc. Q9 is turned on, whereby Q8 and Q10 are also turned on. For example, here, the current ratio between Q8 and Q10 is set to 1:50, and the current I3, which is 50 times the collector current _{ICQ8 of} Q8, flows through the collector of Q10. The collector of Q10 serves as the output terminal OUT of the reference current generating circuit, and the current I3 is provided to other circuits as an output current for use.

This circuit constitutes a current amplifier circuit that amplifies the collector current I _CQ2 flowing in the input side transistor Q2 of the first stage current mirror circuit by the first to third stage current mirror circuit and the current variable circuit, and is obtained by amplification. The obtained current I3 is output as a reference current. For example, in the above-described configuration, I3 = 50 · I2 = 400 · a · I _CQ2 .

I _CQ2 can be treated as equal to the collector current I _CQ1 of Q1, a value corresponding to the current I supplied from the power supply Vcc via a resistor R3. The current I is determined by the voltage difference between the voltages Vcc and V2 across the resistor R3 and is given by the following equation.
I = (Vcc-V2) / R3 (1)
V2 is the potential of the emitter of Q1, R1, R2 base from the voltage V1 Q1 of which is determined by - the increased potential by emitter voltage V _BE minute. That is,
V2 = V1 + V _BE (2)
It is. By the way,
V1 = Vcc · R2 / (R1 + R2) (3)
It is.

Here, I _CQ1 is different from I by the base current I _{BQ1 of} Q1. Although this base current is basically small, it cannot be ignored when the required accuracy of the reference current is high, and the effect is particularly significant when the current amplification factor is large, as in the circuit described above. It becomes. When Q1 of the current amplification factor _{h FE,}
I _CQ1 = I−I _BQ1 = h _FE · I _BQ1 (4)
It is expressed. Also, by transforming this, I
I = (h _FE +1) I _BQ1 (5)
It is expressed. From equation (5), it is understood that when I is constant, the base current I _BQ1 decreases when h _FE is high, and conversely, when h _FE is low, the base current I _BQ1 increases.

For example, when h _FE = 50 and I _CQ1 = 100 μA in the standard state, the base current I _BQ1 is calculated from the equation (4):
I _BQ1 = ₂ μA
It becomes. Further, the current I is I = 102 μA from the equation (4) or (5). Further, when the magnification a is 0.5 in the current variable circuit, the output current I3 is
I3 = 20mA
It becomes.

Here, _hFE is not necessarily constant, and may vary with time, may vary depending on the manufacturing process, and may deviate from a standard value. For _example, it is assumed _{that h FE} becomes 1/2 of the standard value, i.e. _h FE = 25. At this time, since I is the same value as the standard state regardless of variations, that is, I = 102 μA, from the equation (5),
I _BQ1 = 102 / (25 + 1) = 3.92 μA
It becomes. That is, when h _FE is halved, the base current I _BQ1 is approximately halved. As a result, I _CQ1 is obtained from the equation (4):
I _CQ1 = 100-3.92 = 96.08μA
It becomes. Therefore, I3 is
I3 = 19.22 mA
This value has a variation of about -4% compared to the case of h _FE = 50 described above.

[Embodiment]
Based on the above basic configuration, embodiments of the present invention will be described below. FIG. 2 is a schematic circuit diagram of the reference current generating circuit according to the present embodiment. This circuit has a configuration common to the circuit having the basic configuration shown in FIG. 1, and the description thereof is omitted by using the same reference numerals for the portion.

  In this circuit, NPN transistors Q11 and Q12 are added to the circuit having the above-described basic configuration. Transistors Q11 and Q12 are connected between Vcc and GND with their channels in series. That is, the emitter of Q11 is connected to Vcc, the collector of Q12 is connected to GND, and the collector of Q11 and the emitter of Q12 are connected to each other.

  The base of Q11 is connected to the base of Q5 constituting the second stage current mirror circuit, and Q5 and Q11 constitute a current mirror circuit. That is, this current mirror circuit (compensation current mirror circuit) shares the input side transistor Q5 of the second stage current mirror circuit, while Q11 is configured as an output side path transistor.

Q12 based is connected to the collector of Q2, the base current _{I BQ12} the Q12 is synthesized in the _{I CQ1} from Q1. That is, the collector current _{I CQ2} of Q2 becomes _{I CQ2 = I CQ1 + I BQ12} . Here, Q12 is configured in common with Q1 and current amplification factor _hFE . For example, Q12 and Q1 are formed in the same shape and in the same process on a semiconductor substrate.

This circuit, unlike the circuits of the prior art, as well as generating a reference current without requiring an external resistor, suppress variations in I _CQ2 due to the difference of the current amplification factor h _FE generated in the basic configuration Thus, it is possible to supply a reference current with good accuracy. Fluctuation suppressing the _{I CQ2} is achieved by combining the _{I CQ1} the base current _{I BQ12} of Q12 as a compensation current (compensation for the base current). The operation of this circuit will be described below.

  For example, Q12 is configured as a transistor having the same size as Q1. Further, Q11 and Q5 are set to the same size, and the current ratio of the compensating current mirror circuit is set to 1: 1.

In this configuration, since the current ratio of the first-stage current mirror circuit composed of Q2 and Q4 is 1: 1, assuming that the current mirror circuit is ideal, the collector current I _{CQ11 of} Q11 is _This is the same as the collector current I _CQ2 . Here, the collector current I _CQ2 can be approximately regarded as I. Therefore, the collector current I _CQ11 can also be regarded as I. Its base current _{I BQ12} of Q12 case will be substantially equal to the base current _{I BQ1} of Q1. The _{I BQ12} by synthesizing the _{I CQ1,} loss due to the base current _{I BQ1} in Q1 is _compensated, it is possible to reduce the difference from the I in _{I CQ2.} Thus, variation of I _CQ2 due to the difference in h _FE is suppressed, variations in turn reference current is suppressed.

With respect to this configuration, an example of measured values when h _FE varies, for example, by 2 times and 1/2 times with respect to the standard state is shown.
(I) h When _FE is ½ times the standard value:
_{I BQ1 = 3.67μA, I CQ1 =} 116.0μA, I CQ2 = 119.7μA
(Ii) When _hFE is a standard value:
_{I BQ1 = 1.90μA, I CQ1 =} 120.0μA, I CQ2 = 121.9μA
(Iii) h When _FE is twice the standard value:
_{I BQ1 = 0.98μA, I CQ1 =} 122.0μA, I CQ2 = 123.0μA

From this result, the compensation current according to Q12, it can be seen that the fluctuation range of the I _CQ2 is suppressed than the variation width of the I _CQ1.

So far, it has been assumed that the current I is constant. However, in practice _{V BE} also vary depending on the _{h FE,} V2 is changed. As a result, the current I can vary. An embodiment in which the accuracy of the reference current is further improved in consideration of the fluctuation of I will be described below.

In general, V _BE decreases when h _FE is high and increases when h _FE is low. Therefore, when _hFE is low, V2 increases, current I decreases, and I _CQ1 also decreases. On the other hand, when _hFE is high, V2 decreases, current I increases, and _ICQ1 also increases. That is, a change in the _{I CQ1} due to _{the V BE} varies depending on the _{h FE,} the change in _{I CQ1} due to the base current of Q1 according to the above-described _{h FE} is changed, increased or decreased direction Are the same. Based on this relationship, the compensation current generated by Q12 is to appropriately suppress the fluctuation of the _{I CQ1} corresponding to _{h FE,} in this embodiment to adjust the ratio to _{I CQ2} of the collector current _{I CQ11} of Q11. Such adjustments, assuming the variation range of h _FE, can be performed as variations in I _CQ1 is preferably suppressed by at least the range. The collector current of Q11 can be adjusted by changing the current ratio of the compensating current mirror circuit by adjusting its size. By adjusting the collector current I _{CQ11 of} Q11, the compensation current I _BQ12 can also be changed in conjunction with it. At this time, the size of Q12 may be adjusted in accordance with the size of Q11.

For example, in the above case where h _FE can vary within a range of 1/2 to 2 times the standard value, the size of Q11 is set to twice Q5, and the current ratio of the compensating current mirror circuit is set to 1: 2. . As a result, the collector current I _{CQ11 of} Q11 is doubled, and the compensation current I _BQ12 is also doubled. At this time, the size of Q12 is also doubled in accordance with the size of Q11.

Examples of measured values for this configuration are shown below.
(I) h When _FE is ½ times the standard value:
_{I BQ1 = 3.67μA, I CQ1 =} 116.0μA, I BQ12 = 7.24μA, I CQ2 = 123.2μA
(Ii) When _hFE is a standard value:
_{I BQ1 = 1.90μA, I CQ1 =} 120.0μA, I BQ12 = 3.67μA, I CQ2 = 123.7μA
(Iii) h When _FE is twice the standard value:
_{I BQ1 = 0.98μA, I CQ1 =} 122.0μA, I BQ12 = 1.88μA, I CQ2 = 123.9μA

When this is compared with the result in the case of the current ratio 1: 1 of the compensation current mirror circuit described above, it can be seen that the fluctuation _range of I _CQ2 is further suppressed.

The adjustment magnification of the collector current _ICQ11 of Q11 can be set based on, for example, simulations or measurement results of prototype elements.

It is a schematic circuit diagram which shows an example of the fundamental structure relevant to embodiment of this invention. 1 is a schematic circuit diagram of a reference current generating circuit according to an embodiment of the present invention. It is a circuit diagram which shows the structure of the conventional reference current generation circuit.

Explanation of symbols

  Q1-Q12 transistors, R1-R3 resistors.

Claims (5)

A transistor Q _S for passing a current I according to a control voltage applied to the base;
n consists current mirror circuit stage (n ≧ 1), comprising the transistor Q _S connected to the transistor Q _M of the input current corresponding to the current I as a transistor of the current mirror circuit of the first stage, the current A current mirror that outputs a reference current according to I;
A compensating current mirror circuit sharing one transistor with the current mirror circuit of the k-th stage (1 ≦ k ≦ n) of the current mirror unit;
A transistor Q _C2 connected to the other transistor Q _C1 of the compensating current mirror circuit in series between the emitter and the collector;
Have
The transistor Q _C2 is to cause compensating a base current supplied to said been synthesized in the input current to a base current according to the base current of the transistor Q _S to the transistor Q _M,
A reference current generating circuit characterized by the above. The reference current generating circuit according to claim 1,
The transistor Q _C2 is a reference current generating circuit, characterized in that, to set the transistor Q _S and common current amplification factor h _FE. The reference current generating circuit according to claim 2,
The channel current of the transistor _QC2 is the compensation base current corresponding to the current amplification factor _hFE and temperature fluctuation in a predetermined fluctuation range, and the current I for compensation is the current of the compensation base current. Being set to change within a range corresponding to the fluctuation range of I,
A reference current generating circuit characterized by the above. The reference current generating circuit according to claim 3,
The emitter of the transistor Q _C2 - collector current is adjusted by the current ratio of the current ratio and the compensating current mirror circuit of the current mirror circuit from the first stage of the current mirror portion to the (k-1) stage A reference current generating circuit. In the reference current generation circuit according to any one of claims 1 to 3,
One terminal of the transistor Q _S , the transistors constituting the even-numbered current mirror circuit, and the emitter and collector of each of the transistors Q _C1 is connected to a first power supply,
One terminal of the transistor and the transistor Q _C2 respectively the emitter and collector constitute the current mirror circuit of the odd-numbered stage is connected to the second power supply,
The base of the transistor Q _C1 is connected to the base of the transistor constituting the current mirror circuit of any one of the even-numbered stage,
Base of the transistor Q _C2, together with the emitter and the other terminal of the collector of the transistor Q _S, the other terminal of the emitter and collector of the transistor Q _M of the input side path of the current mirror circuit of the first stage Being connected,
A reference current generating circuit characterized by the above.

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