JP2006217334A - Fm demodulation circuit - Google Patents

Fm demodulation circuit Download PDF

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JP2006217334A
JP2006217334A JP2005028850A JP2005028850A JP2006217334A JP 2006217334 A JP2006217334 A JP 2006217334A JP 2005028850 A JP2005028850 A JP 2005028850A JP 2005028850 A JP2005028850 A JP 2005028850A JP 2006217334 A JP2006217334 A JP 2006217334A
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JP4408085B2 (en
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Yusuke Otomo
祐輔 大友
Kazuyoshi Nishimura
和好 西村
Masashi Nogawa
正史 野河
Tomoaki Kawamura
智明 川村
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Nippon Telegraph and Telephone Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To obtain linearity of precise f-V property through a wide frequency area of an input FM signal. <P>SOLUTION: This FM demodulation circuit comprises: an edge detection means which detects an edge of the input FM signal of a differential format and outputs the detected result by using the differential format; a differential amplifier 3 where only one of a positive phase input terminal and an opposite phase input terminal is connected with a positive phase output terminal or an opposite phase output terminal of the edge detection means; and a reference voltage generation circuit 4 which applies reference voltage to an input terminal which is not connected with the output terminal of the edge detection means among the positive phase input terminal and an opposite phase input terminal of the differential amplifier 3. The edge detection means comprises: a differential delay circuit 1 outputting a signal obtained by delaying the input FM signal; and a differential AND circuit 2 which inputs the input FM signal as first input and a signal outputted from the differential delay circuit as second input. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、高精度に動作する広帯域なFM(Frequency Modulation)復調回路に関するものである。   The present invention relates to a broadband FM (Frequency Modulation) demodulation circuit that operates with high accuracy.

従来のFM復調回路の例を図7に示す(例えば、特許文献1、非特許文献1参照)。従来のFM復調回路は、正相入力信号INPと逆相入力信号INNとを入力とする差動遅延回路1と、差動AND回路2と、差動AND回路2の正相出力信号cpと逆相出力信号cnとを入力とする差動アンプ3とからなる。FM復調回路の実際の復調出力は、差動アンプ3の正相出力信号O3Pにローパスフィルタ(不図示)を接続して得られる。   An example of a conventional FM demodulation circuit is shown in FIG. 7 (see, for example, Patent Document 1 and Non-Patent Document 1). The conventional FM demodulation circuit has a differential delay circuit 1 that receives a positive phase input signal INP and a negative phase input signal INN, a differential AND circuit 2, and a positive phase output signal cp of the differential AND circuit 2. It comprises a differential amplifier 3 that receives the phase output signal cn. The actual demodulated output of the FM demodulating circuit is obtained by connecting a low-pass filter (not shown) to the positive phase output signal O3P of the differential amplifier 3.

従来のFM復調回路の接続について説明する。正相入力信号INPは、差動遅延回路1の正相入力端子及び差動AND回路2の第1の正相入力端子apに入力され、逆相入力信号INNは、差動遅延回路1の逆相入力端子及び差動AND回路2の第1の逆相入力端子anに入力される。差動遅延回路1の正相出力信号は、差動AND回路2の第2の正相入力端子bpに入力され、差動遅延回路1の逆相出力信号は、差動AND回路2の第2の逆相入力端子bnに入力される。差動AND回路2の正相出力端子cpは、差動アンプ3の正相入力端子と接続され、差動AND回路2の逆相出力端子cnは、差動アンプ3の逆相入力端子と接続される。差動アンプ3の出力は、正相出力信号O3Pと反転出力信号O3Nである。   The connection of the conventional FM demodulation circuit will be described. The positive phase input signal INP is input to the positive phase input terminal of the differential delay circuit 1 and the first positive phase input terminal ap of the differential AND circuit 2, and the negative phase input signal INN is the reverse of the differential delay circuit 1. The phase input terminal and the first negative phase input terminal an of the differential AND circuit 2 are input. The positive phase output signal of the differential delay circuit 1 is input to the second positive phase input terminal bp of the differential AND circuit 2, and the negative phase output signal of the differential delay circuit 1 is the second phase output signal of the differential AND circuit 2. Are input to the negative phase input terminal bn. The positive phase output terminal cp of the differential AND circuit 2 is connected to the positive phase input terminal of the differential amplifier 3, and the negative phase output terminal cn of the differential AND circuit 2 is connected to the negative phase input terminal of the differential amplifier 3. Is done. The outputs of the differential amplifier 3 are a normal phase output signal O3P and an inverted output signal O3N.

従来のFM復調回路の動作を、図8を用いて説明する。図7のFM復調回路には、FM信号である正相入力信号INPと逆相入力信号INNとが入力される。図8(A)、図8(B)では、FM信号の基本波である周波数fのサイン波がアンプにより周波数fのパルスに変換された後の正相入力信号INPと逆相入力信号INNとを示している。この正相入力信号INPと逆相入力信号INNとは、差動遅延回路1を通過することにより、共に遅延時間τだけ遅れる。差動AND回路2の第1の正相入力端子ap、第1の逆相入力端子anには、それぞれ正相入力信号INP、逆相入力信号INNが入力され、差動AND回路2の第2の正相入力端子bp、第2の逆相入力端子bnには、それぞれ差動遅延回路1の正相出力信号、逆相出力信号が入力される(図8(A)〜図8(D))。   The operation of the conventional FM demodulation circuit will be described with reference to FIG. A normal phase input signal INP and a negative phase input signal INN which are FM signals are input to the FM demodulation circuit of FIG. 8A and 8B, the positive phase input signal INP and the negative phase input signal INN after the sine wave of the frequency f, which is the fundamental wave of the FM signal, is converted into a pulse of the frequency f by the amplifier. Is shown. The normal phase input signal INP and the negative phase input signal INN are both delayed by a delay time τ by passing through the differential delay circuit 1. A positive phase input signal INP and a negative phase input signal INN are input to the first positive phase input terminal ap and the first negative phase input terminal an of the differential AND circuit 2, respectively. The positive phase output signal and the negative phase output signal of the differential delay circuit 1 are input to the positive phase input terminal bp and the second negative phase input terminal bn, respectively (FIGS. 8A to 8D). ).

差動AND回路2は、第1の正相入力端子ap及び第1の逆相入力端子anの入力と第2の正相入力端子bp及び第2の逆相入力端子bnの入力との論理積をとる。これにより、図8(E)、図8(F)に示すように、差動AND回路2の正相出力端子cpと逆相出力端子cnには、正相入力信号INPがローからハイに立ち上がるタイミングでパルスが発生する。このパルスは、差動遅延回路1の遅延時間τ程度のパルス幅を有する。差動AND回路2の正相出力端子cpと逆相出力端子cnから出力されたパルスは、差動アンプ3で差動増幅され、正相出力信号O3P、反転出力信号O3Nとして出力される(図8(G)、図8(H)))。正相出力信号O3Pは、図示しないローパスフィルタにより時間積分され、FM復調回路の出力信号となる。すなわち、正相出力信号O3Pのパルス幅の時間だけローパスフィルタの容量に電荷が蓄積され、電圧Voとして出力される。   The differential AND circuit 2 is a logical product of the inputs of the first positive phase input terminal ap and the first negative phase input terminal an and the inputs of the second positive phase input terminal bp and the second negative phase input terminal bn. Take. As a result, as shown in FIGS. 8E and 8F, the positive phase input signal INP rises from low to high at the positive phase output terminal cp and the negative phase output terminal cn of the differential AND circuit 2. A pulse is generated at the timing. This pulse has a pulse width of about the delay time τ of the differential delay circuit 1. The pulses output from the positive phase output terminal cp and the negative phase output terminal cn of the differential AND circuit 2 are differentially amplified by the differential amplifier 3 and output as a normal phase output signal O3P and an inverted output signal O3N (FIG. 8 (G), FIG. 8 (H))). The normal phase output signal O3P is time-integrated by a low-pass filter (not shown) and becomes an output signal of the FM demodulation circuit. That is, charge is accumulated in the capacitance of the low-pass filter for the time of the pulse width of the positive phase output signal O3P, and is output as the voltage Vo.

FM信号(正相入力信号INP及び逆相入力信号INN)の周波数fが高くなれば、正相出力信号O3Pの単位時間あたりのパルス数が多くなるため、出力電圧Voは高くなり、周波数fが低くなれば、正相出力信号O3Pの単位時間あたりのパルス数が少なくなるため、出力電圧Voは低くなる。よって、FM信号の周波数の高低が電位の高低に変換されて、FM信号がAM信号に復調される。少ない歪でFM復調を行うためには、FM信号の周波数fの広い範囲にわたって、周波数fに対して出力電圧Voが高い精度で比例すること(以下、f−V特性の線形性と呼ぶ)が必須である。図8(G)に示した正相出力信号O3Pの出力パルス面積が広い周波数にわたって不変であり、かつ出力パルス以外の信号箇所に現れるノイズが小さい場合に、f−V特性の良好な線形性が達成される。   If the frequency f of the FM signal (the positive phase input signal INP and the negative phase input signal INN) increases, the number of pulses per unit time of the positive phase output signal O3P increases, so the output voltage Vo increases and the frequency f If it becomes lower, the number of pulses per unit time of the positive phase output signal O3P becomes smaller, so the output voltage Vo becomes lower. Therefore, the frequency level of the FM signal is converted into the potential level, and the FM signal is demodulated into an AM signal. In order to perform FM demodulation with less distortion, the output voltage Vo is proportional to the frequency f with high accuracy over a wide range of the frequency f of the FM signal (hereinafter referred to as linearity of the fV characteristic). It is essential. When the output pulse area of the positive phase output signal O3P shown in FIG. 8G is invariant over a wide frequency and the noise appearing at signal portions other than the output pulse is small, the fV characteristic has good linearity. Achieved.

なお、出願人は、本明細書に記載した先行技術文献情報で特定される先行技術文献以外には、本発明に関連する先行技術文献を出願時までに発見するには至らなかった。
特開2002−368542号公報 広瀬,岸根,石原,赤沢,菊島,岸本,雲崎,「AM/FM一括変換による光映像伝送用高利得,広帯域FM復調IC」,電子情報通信学会技術報告CAS96−115,1997年3月,p.111−117
The applicant has not yet found prior art documents related to the present invention by the time of filing other than the prior art documents specified by the prior art document information described in this specification.
JP 2002-368542 A Hirose, Kishine, Ishihara, Akazawa, Kikushima, Kishimoto, Kumozaki, "High gain, wideband FM demodulation IC for optical video transmission by AM / FM batch conversion", IEICE Technical Report CAS 96-115, March 1997 , P. 111-117

図7に示した従来のFM復調回路の問題点は、差動AND回路2の正相出力端子cpと逆相出力端子cnの両方で発生するパルス幅の誤差とノイズとが差動アンプ3に入力されるために、f−V特性の高精度な線形性が得られないことである。これにより、従来のFM復調回路では、広い入力周波数領域に渡って、歪の少ないFM復調特性を得ることができない。ここで、差動AND回路2の回路構成を図9に示す。図9において、Q1〜Q9はNチャネルMOSトランジスタ、I1〜I3は定電流源、R1,R2は抵抗である。差動AND回路2では図9に例示するごとく、正相出力端子cpに出力される信号を生成する回路構成と逆相出力端子cnに出力される信号を生成する回路構成とに対称性がない。したがって、正相出力端子cpに出力される信号と逆相出力端子cnに出力される信号との間には、応答特性やノイズ波高値に相違が生じる。応答特性に相違が生じると、差動AND回路2の第1の入力と第2の入力との遅延差τに対して出力パルスの幅がτと異なることが生じる。   The problem with the conventional FM demodulator circuit shown in FIG. 7 is that the differential amplifier 3 is caused by an error in the pulse width and noise generated at both the positive phase output terminal cp and the negative phase output terminal cn of the differential AND circuit 2. Since it is input, high-precision linearity of the fV characteristic cannot be obtained. Thus, the conventional FM demodulation circuit cannot obtain an FM demodulation characteristic with little distortion over a wide input frequency region. Here, the circuit configuration of the differential AND circuit 2 is shown in FIG. In FIG. 9, Q1 to Q9 are N channel MOS transistors, I1 to I3 are constant current sources, and R1 and R2 are resistors. In the differential AND circuit 2, as illustrated in FIG. 9, there is no symmetry between a circuit configuration for generating a signal output to the positive phase output terminal cp and a circuit configuration for generating a signal output to the negative phase output terminal cn. . Therefore, there is a difference in response characteristics and noise peak value between the signal output to the positive phase output terminal cp and the signal output to the negative phase output terminal cn. If the response characteristics are different, the output pulse width may be different from τ with respect to the delay difference τ between the first input and the second input of the differential AND circuit 2.

差動アンプ3の正相出力信号O3Pは、正相出力端子cpに出力される信号と逆相出力端子cnに出力される信号のうちパルス幅が広い方の信号の影響を受けて、パルス幅がτより広くなるばかりでなく、正相出力端子cpと逆相出力端子cnの双方に現れるノイズが重畳される。このように、正相出力信号O3Pの出力パルス幅が広くなると、入力FM信号の周波数fが高い場合に、隣接するパルス同士の裾の部分が重なり、出力パルスの面積が低周波の場合よりも小さくなる。また、正相出力信号O3Pに重畳されたノイズは、このノイズに隣接する次の出力パルスとの位相関係により、出力パルスの波高値に変化を及ぼす。このような正相出力信号O3Pの出力パルスの幅及び波高値の変化は、入力FM信号の周波数fに依存する出力パルスの面積の変化となり、ローパスフィルタの出力電圧Voの周波数fに対する線形性を損なう。以上のように、従来のFM復調回路では、入力FM信号の広い周波数領域にわたって高精度なf−V線形性を達成することができないという問題点があった。   The positive-phase output signal O3P of the differential amplifier 3 is affected by the signal having the wider pulse width of the signal output to the positive-phase output terminal cp and the signal output to the negative-phase output terminal cn. Becomes wider than τ, and noise appearing at both the positive phase output terminal cp and the negative phase output terminal cn is superimposed. As described above, when the output pulse width of the positive phase output signal O3P is wide, when the frequency f of the input FM signal is high, the tail portions of adjacent pulses overlap, and the area of the output pulse is lower than that in the case of the low frequency. Get smaller. The noise superimposed on the positive phase output signal O3P changes the peak value of the output pulse due to the phase relationship with the next output pulse adjacent to the noise. Such a change in the width and peak value of the output pulse of the positive phase output signal O3P results in a change in the area of the output pulse depending on the frequency f of the input FM signal, and the linearity of the output voltage Vo of the low-pass filter with respect to the frequency f is changed. To lose. As described above, the conventional FM demodulation circuit has a problem that it is impossible to achieve highly accurate fV linearity over a wide frequency range of the input FM signal.

本発明は、上記課題を解決するためになされたもので、入力FM信号の広い周波数領域にわたってf−V特性の高精度な線形性を実現することができるFM復調回路を提供することを目的とする。   The present invention has been made to solve the above-described problem, and an object of the present invention is to provide an FM demodulation circuit capable of realizing highly accurate linearity of fV characteristics over a wide frequency range of an input FM signal. To do.

本発明のFM復調回路は、差動形式の入力FM信号のエッジを検出して、その検出結果を差動形式で出力するエッジ検出手段と、正相入力端子と逆相入力端子のうち一方だけが前記エッジ検出手段の正相出力端子あるいは逆相出力端子と接続された差動増幅手段と、この差動増幅手段の正相入力端子と逆相入力端子のうち、前記エッジ検出手段の出力端子と接続されていない方の入力端子にレファレンス電圧を与えるレファレンス電圧発生回路とを有するものである。
また、本発明のFM復調回路の1構成例において、前記エッジ検出手段は、前記差動形式の入力FM信号を遅延させた差動形式の信号を出力する差動遅延回路と、前記差動形式の入力FM信号を第1の入力とし、前記差動遅延回路から出力された差動形式の信号を第2の入力とし、前記第1の入力と前記第2の入力との論理積の結果を差動形式で出力する差動AND回路とからなるものである。
また、本発明のFM復調回路の1構成例において、前記エッジ検出手段は、前記差動形式の入力FM信号を遅延させた差動形式の信号を出力する差動遅延回路と、前記差動形式の入力FM信号を第1の入力とし、前記差動遅延回路から出力された差動形式の信号を第2の入力とし、前記第1の入力と前記第2の入力との排他的論理和の結果を差動形式で出力する差動EXOR回路とからなるものである。
また、本発明のFM復調回路の1構成例は、さらに、前記エッジ検出手段の正相出力端子と逆相出力端子のうち、前記差動増幅手段の入力端子と接続されていない方の出力端子に接続された負荷回路を有するものである。
The FM demodulating circuit of the present invention detects an edge of a differential input FM signal and outputs the detection result in a differential format, and only one of a positive phase input terminal and a negative phase input terminal. Differential amplification means connected to the positive phase output terminal or the negative phase output terminal of the edge detection means, and the output terminal of the edge detection means among the positive phase input terminal and the negative phase input terminal of the differential amplification means And a reference voltage generating circuit for applying a reference voltage to the input terminal not connected to the input terminal.
Further, in one configuration example of the FM demodulation circuit of the present invention, the edge detection means includes a differential delay circuit that outputs a differential signal obtained by delaying the differential input FM signal, and the differential signal. The input FM signal is the first input, the differential signal output from the differential delay circuit is the second input, and the result of the logical product of the first input and the second input is obtained. It comprises a differential AND circuit that outputs in a differential format.
Further, in one configuration example of the FM demodulation circuit of the present invention, the edge detection means includes a differential delay circuit that outputs a differential signal obtained by delaying the differential input FM signal, and the differential signal. Input FM signal as a first input, a differential signal output from the differential delay circuit as a second input, and an exclusive OR of the first input and the second input It comprises a differential EXOR circuit that outputs the result in a differential format.
In addition, one configuration example of the FM demodulating circuit according to the present invention further includes an output terminal that is not connected to an input terminal of the differential amplifying means, out of a positive phase output terminal and a negative phase output terminal of the edge detecting means. And a load circuit connected to the.

本発明によれば、エッジ検出手段の正相と逆相の出力のうち一方の出力だけを差動増幅手段に接続し、差動増幅手段の接続されていない端子にはレファレンス電圧を与えることにより、エッジ検出手段の正相と逆相の出力のうち、応答特性が良好でかつ低ノイズである一方の出力だけを用いることができるので、入力FM信号の周波数が高くなることに伴う差動増幅手段の出力パルスのパルス幅の増減を抑制することができ、また差動増幅手段の出力に現れるノイズを低減することができる。これにより、本発明では、入力FM信号の広い周波数帯域にわたって差動増幅手段の出力パルスの面積を不変とし、f−V特性の高精度な線形性を実現することができる。したがって、入力FM信号の広い周波数帯域にわたって低歪なFM復調回路を提供することができる。また、本発明では、差動増幅手段に与えるレファレンス電圧を調整することにより、差動増幅手段の出力パルス幅を調整することができるので、その結果としてFM復調ゲインを調整することができる。   According to the present invention, only one of the positive phase output and the negative phase output of the edge detection means is connected to the differential amplification means, and a reference voltage is applied to a terminal to which the differential amplification means is not connected. Since only one of the positive-phase and negative-phase outputs of the edge detection means that has good response characteristics and low noise can be used, differential amplification accompanying an increase in the frequency of the input FM signal The increase and decrease of the pulse width of the output pulse of the means can be suppressed, and the noise appearing at the output of the differential amplifying means can be reduced. Thereby, in this invention, the area of the output pulse of a differential amplification means is made invariable over the wide frequency band of an input FM signal, and the highly accurate linearity of fV characteristic is realizable. Therefore, it is possible to provide an FM demodulating circuit having low distortion over a wide frequency band of the input FM signal. In the present invention, the output pulse width of the differential amplifying means can be adjusted by adjusting the reference voltage applied to the differential amplifying means. As a result, the FM demodulation gain can be adjusted.

本発明のFM復調回路は、差動AND回路または差動EXOR回路の正相と逆相の出力のうち、応答特性が良好でかつ低ノイズな一方の出力だけを差動アンプに接続し、差動アンプの接続されていない端子にはレファレンス電圧を供給することを特徴とするものである。   The FM demodulator circuit of the present invention connects only one of the positive and negative phase outputs of the differential AND circuit or the differential EXOR circuit to the differential amplifier with a good response characteristic and low noise. A reference voltage is supplied to a terminal to which the dynamic amplifier is not connected.

[第1の実施の形態]
以下、本発明の実施の形態について図面を参照して説明する。図1は本発明の第1の実施の形態となるFM復調回路の構成を示すブロック図である。本実施の形態のFM復調回路は、正相入力信号INPと逆相入力信号INNとを入力とする差動遅延回路1と、差動AND回路2と、レファレンス電圧dpを発生するレファレンス電圧発生回路4と、レファレンス電圧dpと差動AND回路2の逆相出力信号cnとを入力とする差動アンプ3とからなる。FM復調回路の実際の復調出力は、差動アンプ3の正相出力信号O1Pにローパスフィルタ(不図示)を接続して得られる。
[First Embodiment]
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an FM demodulation circuit according to the first embodiment of the present invention. The FM demodulation circuit of the present embodiment includes a differential delay circuit 1 that receives a positive phase input signal INP and a negative phase input signal INN, a differential AND circuit 2, and a reference voltage generation circuit that generates a reference voltage dp. 4 and a differential amplifier 3 that receives the reference voltage dp and the negative phase output signal cn of the differential AND circuit 2 as inputs. The actual demodulated output of the FM demodulator circuit is obtained by connecting a low-pass filter (not shown) to the positive phase output signal O1P of the differential amplifier 3.

本実施の形態のFM復調回路の接続について説明する。正相入力信号INPは、差動遅延回路1の正相入力端子及び差動AND回路2の第1の正相入力端子apに入力され、逆相入力信号INNは、差動遅延回路1の逆相入力端子及び差動AND回路2の第1の逆相入力端子anに入力される。差動遅延回路1の正相出力信号は、差動AND回路2の第2の正相入力端子bpに入力され、差動遅延回路1の逆相出力信号は、差動AND回路2の第2の逆相入力端子bnに入力される。差動AND回路2の正相出力端子cpは、何処にも接続されず、差動AND回路2の逆相出力端子cnは、差動アンプ3の逆相入力端子と接続される。レファレンス電圧発生回路4の出力端子は、差動アンプ3の正相入力端子と接続される。差動アンプ3の出力は、正相出力信号O1Pと反転出力信号O1Nである。   Connection of the FM demodulation circuit of this embodiment will be described. The positive phase input signal INP is input to the positive phase input terminal of the differential delay circuit 1 and the first positive phase input terminal ap of the differential AND circuit 2, and the negative phase input signal INN is the reverse of the differential delay circuit 1. The phase input terminal and the first negative phase input terminal an of the differential AND circuit 2 are input. The positive phase output signal of the differential delay circuit 1 is input to the second positive phase input terminal bp of the differential AND circuit 2, and the negative phase output signal of the differential delay circuit 1 is the second phase output signal of the differential AND circuit 2. Are input to the negative phase input terminal bn. The positive phase output terminal cp of the differential AND circuit 2 is not connected anywhere, and the negative phase output terminal cn of the differential AND circuit 2 is connected to the negative phase input terminal of the differential amplifier 3. The output terminal of the reference voltage generation circuit 4 is connected to the positive phase input terminal of the differential amplifier 3. The outputs of the differential amplifier 3 are a normal phase output signal O1P and an inverted output signal O1N.

本実施の形態のFM復調回路の動作を、図2を用いて説明する。図1のFM復調回路には、FM信号である正相入力信号INPと逆相入力信号INNとが入力される。図2(A)、図2(B)では、FM信号の基本波である周波数fのサイン波がアンプにより周波数fのパルスに変換された後の正相入力信号INPと逆相入力信号INNとを示している。この正相入力信号INPと逆相入力信号INNとは、差動遅延回路1を通過することにより、共に遅延時間τだけ遅れる。差動AND回路2の第1の正相入力端子ap、第1の逆相入力端子anには、それぞれ正相入力信号INP、逆相入力信号INNが入力され、差動AND回路2の第2の正相入力端子bp、第2の逆相入力端子bnには、それぞれ差動遅延回路1の正相出力信号、逆相出力信号が入力される(図2(A)〜図2(D))。   The operation of the FM demodulation circuit according to this embodiment will be described with reference to FIG. A normal phase input signal INP and a negative phase input signal INN, which are FM signals, are input to the FM demodulation circuit of FIG. 2A and 2B, the positive-phase input signal INP and the negative-phase input signal INN after the sine wave of the frequency f, which is the fundamental wave of the FM signal, is converted into a pulse of the frequency f by the amplifier. Is shown. The normal phase input signal INP and the negative phase input signal INN are both delayed by a delay time τ by passing through the differential delay circuit 1. A positive phase input signal INP and a negative phase input signal INN are input to the first positive phase input terminal ap and the first negative phase input terminal an of the differential AND circuit 2, respectively. The positive phase output signal and the negative phase output signal of the differential delay circuit 1 are input to the positive phase input terminal bp and the second negative phase input terminal bn, respectively (FIGS. 2A to 2D). ).

差動AND回路2は、第1の入力(第1の正相入力端子ap及び第1の逆相入力端子anに入力される信号)と第2の入力(第2の正相入力端子bp及び第2の逆相入力端子bnに入力される信号)との論理積をとる。これにより、図2(E)に示すように、差動AND回路2の逆相出力端子cnには、正相入力信号INPがローからハイに立ち上がるタイミングでパルスが発生する。このパルスは、差動遅延回路1の遅延時間τ程度のパルス幅を有する。差動AND回路2の逆相出力端子cnから出力されたパルスは、差動アンプ3に入力される。   The differential AND circuit 2 includes a first input (signal input to the first positive phase input terminal ap and the first negative phase input terminal an) and a second input (second positive phase input terminal bp and Logical product with the second negative phase input terminal bn). As a result, as shown in FIG. 2E, a pulse is generated at the negative phase output terminal cn of the differential AND circuit 2 at the timing when the positive phase input signal INP rises from low to high. This pulse has a pulse width of about the delay time τ of the differential delay circuit 1. The pulse output from the negative phase output terminal cn of the differential AND circuit 2 is input to the differential amplifier 3.

差動アンプ3は、レファレンス電圧発生回路4から出力されるレファレンス電圧dpをしきい値として逆相出力端子cnの信号のハイ/ロー判定を行い、パルスを増幅して、図2(F)、図2(G)に示す正相出力信号O1P、反転出力信号O1Nとして出力する(すなわち、差動アンプ3は、レファレンス電圧dpと逆相出力端子cnの信号との差を増幅する)。正相出力信号O1Pは、図示しないローパスフィルタにより時間積分され、FM復調回路の出力信号となる。すなわち、正相出力信号O1Pのパルス幅の時間だけローパスフィルタの容量に電荷が蓄積され、電圧Voとして出力される。   The differential amplifier 3 performs high / low determination of the signal at the negative phase output terminal cn using the reference voltage dp output from the reference voltage generation circuit 4 as a threshold value, amplifies the pulse, and FIG. It outputs as the positive phase output signal O1P and the inverted output signal O1N shown in FIG. 2G (that is, the differential amplifier 3 amplifies the difference between the reference voltage dp and the signal at the negative phase output terminal cn). The normal phase output signal O1P is time-integrated by a low-pass filter (not shown) and becomes an output signal of the FM demodulation circuit. That is, electric charges are accumulated in the capacitance of the low-pass filter for the time of the pulse width of the positive phase output signal O1P and output as the voltage Vo.

FM信号(正相入力信号INP及び逆相入力信号INN)の周波数fが高くなれば、正相出力信号O1Pの単位時間あたりのパルス数が多くなるため、出力電圧Voは高くなり、周波数fが低くなれば、正相出力信号O1Pの単位時間あたりのパルス数が少なくなるため、出力電圧Voは低くなる。よって、FM信号の周波数の高低が電位の高低に変換されて、FM信号がAM信号に復調される。   If the frequency f of the FM signal (the positive phase input signal INP and the negative phase input signal INN) increases, the number of pulses per unit time of the positive phase output signal O1P increases, so the output voltage Vo increases and the frequency f If it becomes lower, the number of pulses per unit time of the positive phase output signal O1P becomes smaller, so the output voltage Vo becomes lower. Therefore, the frequency level of the FM signal is converted into the potential level, and the FM signal is demodulated into an AM signal.

ここで、差動AND回路2の正相出力と逆相出力のうち、正相出力端子cpに出力される信号の方が応答特性が劣り、またノイズの波高値も高い。そこで、本実施の形態では、正相出力端子cpを差動アンプ3の入力端子に接続せず、差動AND回路2の逆相出力端子cnだけを差動アンプ3の逆相入力端子に接続する。これにより、正相出力端子cpの信号の影響を受けることを回避することができる。よって、正相出力信号O1Pのパルス幅は、差動遅延回路1の遅延時間τに近い細い幅を維持し、かつ正相出力信号O1Pに現れるパルス以外のノイズも少なくなる。図2(F)に示した正相出力信号O1Pの出力パルス面積が広い周波数にわたって不変で、かつ出力パルス以外の信号箇所に現れるノイズが小さいため、入力FM信号の高い周波数までf−V特性の良好な線形性が得られる。したがって、本実施の形態によれば、FM復調回路に入力されるFM信号の周波数fの広い範囲にわたって、少ない歪でFM復調を行うことが可能となる。   Here, of the positive-phase output and the negative-phase output of the differential AND circuit 2, the signal output to the positive-phase output terminal cp is inferior in response characteristics, and the noise peak value is high. Therefore, in the present embodiment, the positive phase output terminal cp is not connected to the input terminal of the differential amplifier 3, and only the negative phase output terminal cn of the differential AND circuit 2 is connected to the negative phase input terminal of the differential amplifier 3. To do. Thereby, it can avoid receiving the influence of the signal of the positive phase output terminal cp. Therefore, the pulse width of the positive phase output signal O1P is kept narrow and close to the delay time τ of the differential delay circuit 1, and noise other than the pulse appearing in the positive phase output signal O1P is reduced. Since the output pulse area of the positive phase output signal O1P shown in FIG. 2 (F) is invariant over a wide frequency and the noise appearing at a signal location other than the output pulse is small, the fV characteristic of the input FM signal is high up to the high frequency. Good linearity is obtained. Therefore, according to the present embodiment, it is possible to perform FM demodulation with less distortion over a wide range of the frequency f of the FM signal input to the FM demodulation circuit.

図3に、本実施の形態のFM復調回路と図7に示した従来のFM復調回路のf−V特性を示す。図3の横軸は入力FM信号の周波数f、縦軸は周波数fに比例して出力されるべき電圧とFM復調回路から実際に出力された電圧との誤差(f−V線形性からのズレ)を表している。fV0は従来のFM復調回路のf−V特性、fV1は本実施の形態のFM復調回路のf−V特性である。ここで、ある周波数fが実際に回路で電圧Vrealに変換されるとき、その一次近似直線(周波数fに比例して出力されるべき理想の電圧Videal)を、傾きC[mV/MHz]とおいて次式のように求める。
Videal=C・f ・・・(1)
図3の縦軸の周波数−電圧変換誤差は、理想の電圧と実際の電圧との差(Vreal−Videal)である。
本実施の形態によれば、入力FM信号の周波数fが1GHzから4GHzまでの間で、出力電圧Voの誤差を従来の10分の1程度に低減することができる。さらに、本実施の形態によると、入力FM信号の周波数fが4GHzより高くなった場合でも、従来のような大きな誤差は発生しない。よって、本実施の形態は、入力FM信号の周波数fの広い範囲にわたって、格段の低歪でFM復調を可能とする絶大な効果を奏する。
FIG. 3 shows the fV characteristics of the FM demodulation circuit of the present embodiment and the conventional FM demodulation circuit shown in FIG. The horizontal axis in FIG. 3 is the frequency f of the input FM signal, and the vertical axis is the error (the deviation from the fV linearity) between the voltage to be output in proportion to the frequency f and the voltage actually output from the FM demodulation circuit. ). fV0 is the fV characteristic of the conventional FM demodulation circuit, and fV1 is the fV characteristic of the FM demodulation circuit of the present embodiment. Here, when a certain frequency f is actually converted into the voltage Vreal by the circuit, the linear approximation line (ideal voltage Video that should be output in proportion to the frequency f) is set as a slope C [mV / MHz]. It is calculated as follows:
Video = C · f (1)
The frequency-voltage conversion error on the vertical axis in FIG. 3 is the difference (Vreal-Video) between the ideal voltage and the actual voltage.
According to this embodiment, when the frequency f of the input FM signal is 1 GHz to 4 GHz, the error of the output voltage Vo can be reduced to about 1/10 of the conventional one. Furthermore, according to the present embodiment, even when the frequency f of the input FM signal is higher than 4 GHz, a large error as in the conventional case does not occur. Therefore, this embodiment has a tremendous effect that enables FM demodulation with remarkably low distortion over a wide range of the frequency f of the input FM signal.

[第2の実施の形態]
次に、本発明の第2の実施の形態について説明する。図4は本発明の第2の実施の形態となるFM復調回路の構成を示すブロック図であり、図1と同一の構成には同一の符号を付してある。本実施の形態のFM復調回路は、第1の実施の形態の差動AND回路2を、第1の入力(第1の正相入力端子ap及び第1の逆相入力端子anに入力される信号)と第2の入力(第2の正相入力端子bp及び第2の逆相入力端子bnに入力される信号)との排他的論理和をとる差動EXOR回路5に置き換えたものである。第1の実施の形態と同様に、差動EXOR回路5の正相出力端子epを何処にも接続せずにオープン状態とし、差動EXOR回路5の逆相出力端子enだけを差動アンプ3の逆相入力端子に接続する。
[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 4 is a block diagram showing a configuration of an FM demodulator circuit according to the second embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. The FM demodulator circuit of the present embodiment inputs the differential AND circuit 2 of the first embodiment to a first input (a first positive phase input terminal ap and a first negative phase input terminal an). Signal) and a second input (a signal input to the second positive-phase input terminal bp and the second negative-phase input terminal bn) is replaced with a differential EXOR circuit 5 that takes an exclusive OR. . As in the first embodiment, the positive phase output terminal ep of the differential EXOR circuit 5 is not connected anywhere and is opened, and only the negative phase output terminal en of the differential EXOR circuit 5 is connected to the differential amplifier 3. Connect to the negative phase input terminal.

本実施の形態のFM復調回路の動作を、図5を用いて説明する。図5(E)に示すように、差動EXOR回路5は、正相入力信号INPがローからハイに立ち上がるタイミングとハイからローに立ち下がるタイミングで逆相出力端子enにパルスを出力する。このパルスの時間幅は、第1の入力と第2の入力との間の時間差τにほぼ等しい。差動EXOR回路5の逆相出力端子enから出力されたパルスは、差動アンプ3に入力される。差動アンプ3は、レファレンス電圧発生回路4から出力されるレファレンス電圧dpと逆相出力端子enの信号との差を増幅して、図5(F)、図5(G)に示す正相出力信号O2P、反転出力信号O2Nとして出力する。正相出力信号O2Pは、図示しないローパスフィルタにより時間積分され、FM復調回路の出力信号となる。   The operation of the FM demodulation circuit according to this embodiment will be described with reference to FIG. As shown in FIG. 5E, the differential EXOR circuit 5 outputs a pulse to the negative phase output terminal en at the timing when the positive phase input signal INP rises from low to high and at the timing when the positive phase input signal INP falls from high to low. The time width of this pulse is approximately equal to the time difference τ between the first input and the second input. The pulse output from the negative phase output terminal en of the differential EXOR circuit 5 is input to the differential amplifier 3. The differential amplifier 3 amplifies the difference between the reference voltage dp output from the reference voltage generation circuit 4 and the signal at the negative-phase output terminal en, and outputs the positive-phase outputs shown in FIGS. 5 (F) and 5 (G). The signal O2P and the inverted output signal O2N are output. The normal phase output signal O2P is time-integrated by a low-pass filter (not shown) and becomes an output signal of the FM demodulation circuit.

図5(E)に示す差動EXOR回路5の逆相出力端子enの信号を図2(E)に示した逆相出力端子cnの信号と比較すれば明らかなように、同一の入力FM信号の周波数fに対して、単位時間当たりのパルスの数は第1の実施の形態の2倍になる。よって、本実施の形態のFM復調回路は、FM信号の周波数fを電圧Vに変換する際の傾きに相当する、変換ゲインを第1の実施の形態の2倍にできる。しかし、一方で、正相出力信号O2Pと反転出力信号O2Nの隣接するパルスの時間間隔が約半分になることから、入力FM信号の周波数fが高くなると、隣接するパルス間で裾の重なりが生じ、f−V特性の線形性が急激に劣化する問題が生じる。   As apparent from comparing the signal at the negative phase output terminal en of the differential EXOR circuit 5 shown in FIG. 5E with the signal at the negative phase output terminal cn shown in FIG. 2E, the same input FM signal is obtained. For the frequency f, the number of pulses per unit time is twice that of the first embodiment. Therefore, the FM demodulation circuit according to the present embodiment can double the conversion gain corresponding to the gradient when converting the frequency f of the FM signal into the voltage V as compared with the first embodiment. However, on the other hand, since the time interval between adjacent pulses of the positive phase output signal O2P and the inverted output signal O2N is approximately halved, if the frequency f of the input FM signal is increased, overlapping of the tails occurs between the adjacent pulses. , A problem arises that the linearity of the fV characteristic is rapidly deteriorated.

ここで、差動EXOR回路5の正相出力と逆相出力のうち、正相出力端子epに出力される信号の方がパルス幅が広く、またノイズの波高値も高い。そこで、本実施の形態では、正相出力端子epを差動アンプ3の入力端子に接続せず、差動EXOR回路5の逆相出力端子enだけを差動アンプ3の逆相入力端子に接続する。これにより、差動EXOR回路5の正相出力と逆相出力のうちパルス幅が狭く、ノイズの少ない逆相出力を選択して出力でき、正相出力端子epの信号の影響を受けることを回避することができる。さらに、本実施の形態では、レファレンス電圧dpを差動EXOR回路5の出力の中間電位より低く設定することで、正相出力信号O2Pと反転出力信号O2Nのパルス幅を遅延時間τより短く設定することが可能となる。これら2つの効果により、本実施の形態では、変換ゲインの大きな差動EXOR回路型のFM復調回路において、入力FM信号の周波数fの高い領域まで低歪なf−V特性を達成することができる。   Here, of the positive phase output and the negative phase output of the differential EXOR circuit 5, the signal output to the positive phase output terminal ep has a wider pulse width and a higher noise peak value. Therefore, in the present embodiment, the positive phase output terminal ep is not connected to the input terminal of the differential amplifier 3, and only the negative phase output terminal en of the differential EXOR circuit 5 is connected to the negative phase input terminal of the differential amplifier 3. To do. As a result, it is possible to select and output a negative phase output having a narrow pulse width and less noise out of the positive phase output and the negative phase output of the differential EXOR circuit 5, and avoid being affected by the signal of the positive phase output terminal ep. can do. Furthermore, in the present embodiment, the reference voltage dp is set lower than the intermediate potential of the output of the differential EXOR circuit 5, so that the pulse widths of the positive phase output signal O2P and the inverted output signal O2N are set shorter than the delay time τ. It becomes possible. With these two effects, in the present embodiment, in the differential EXOR circuit type FM demodulation circuit having a large conversion gain, low distortion fV characteristics can be achieved up to the high frequency region of the input FM signal. .

[第3の実施の形態]
次に、本発明の第3の実施の形態について説明する。図6は本発明の第3の実施の形態となるFM復調回路の構成を示すブロック図であり、図1と同一の構成には同一の符号を付してある。本実施の形態のFM復調回路では、第1の実施の形態の差動AND回路2においてオープン状態とした正相出力端子cpに負荷6を接続したことが、第1の実施の形態と異なる点である。負荷6は、差動AND回路2の逆相出力端子cnの出力抵抗と出力端子cnに付く容量との積と、差動AND回路2の正相出力端子cpの出力抵抗と出力端子cpに付く容量(負荷6)との積が等しくなるような値に設定することが望ましい。本実施の形態の基本動作は、図2を用いて説明した第1の実施の形態の動作と同じであるため、ここでは説明を省略する。
[Third Embodiment]
Next, a third embodiment of the present invention will be described. FIG. 6 is a block diagram showing the configuration of an FM demodulator circuit according to the third embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. The FM demodulator according to the present embodiment is different from the first embodiment in that the load 6 is connected to the positive phase output terminal cp that is opened in the differential AND circuit 2 according to the first embodiment. It is. The load 6 is attached to the product of the output resistance of the negative phase output terminal cn of the differential AND circuit 2 and the capacitance attached to the output terminal cn, and to the output resistance of the positive phase output terminal cp of the differential AND circuit 2 and the output terminal cp. It is desirable to set the value so that the product with the capacity (load 6) becomes equal. The basic operation of the present embodiment is the same as the operation of the first embodiment described with reference to FIG.

本実施の形態によれば、差動AND回路2の正相出力端子cpと逆相出力端子cnの駆動負荷を均等に設計することができ、差動AND回路2の電流バランスを保ち、逆相出力端子cnから出力される信号の応答を高速化し、出力のノイズを削減することができる。これにより、本実施の形態では、第1の実施の形態に比べて、入力FM信号の周波数fの更に高い領域まで低歪なf−V特性を達成することができる。   According to the present embodiment, the driving loads of the positive phase output terminal cp and the negative phase output terminal cn of the differential AND circuit 2 can be designed equally, the current balance of the differential AND circuit 2 is maintained, and the negative phase is maintained. It is possible to speed up the response of the signal output from the output terminal cn and reduce output noise. As a result, in this embodiment, it is possible to achieve fV characteristics with low distortion up to a region where the frequency f of the input FM signal is higher than in the first embodiment.

なお、本実施の形態では、差動AND回路2の正相出力端子cpに負荷6を接続したが、第2の実施の形態において差動EXOR回路5の正相出力端子epに負荷6を接続するようにしてもよい。これにより、第2の実施の形態においても、本実施の形態と同様の効果を得ることができる。   In the present embodiment, the load 6 is connected to the positive phase output terminal cp of the differential AND circuit 2. However, in the second embodiment, the load 6 is connected to the positive phase output terminal ep of the differential EXOR circuit 5. You may make it do. Thereby, also in 2nd Embodiment, the effect similar to this Embodiment can be acquired.

また、図9では差動AND回路2の構成例としてMOSトランジスタを使用する場合の例を示したが、これに限るものではなく、差動AND回路2にバイポーラトランジスタやMESFET等の異なるデバイスを使用している場合でも、本発明を適用することができる。差動AND回路や差動EXOR回路の前段あるいは後段のアンプの段数等を変更してFM復調回路を構成することは本発明の思想の範囲内である。   FIG. 9 shows an example in which a MOS transistor is used as a configuration example of the differential AND circuit 2. However, the present invention is not limited to this, and a different device such as a bipolar transistor or MESFET is used for the differential AND circuit 2. Even in this case, the present invention can be applied. It is within the scope of the idea of the present invention to configure the FM demodulator circuit by changing the number of stages of amplifiers at the front stage or the rear stage of the differential AND circuit or differential EXOR circuit.

本発明は、FM復調回路に適用することができる。   The present invention can be applied to an FM demodulation circuit.

本発明の第1の実施の形態となるFM復調回路の構成を示すブロック図である。It is a block diagram which shows the structure of the FM demodulation circuit used as the 1st Embodiment of this invention. 本発明の第1の実施の形態となるFM復調回路の各部の信号を示す入出力波形図である。It is an input-output waveform diagram which shows the signal of each part of the FM demodulation circuit which becomes the 1st Embodiment of this invention. 本発明の第1の実施の形態となるFM復調回路と従来のFM復調回路のf−V特性を示す図である。It is a figure which shows the fV characteristic of the FM demodulation circuit used as the 1st Embodiment of this invention, and the conventional FM demodulation circuit. 本発明の第2の実施の形態となるFM復調回路の構成を示すブロック図である。It is a block diagram which shows the structure of the FM demodulation circuit used as the 2nd Embodiment of this invention. 本発明の第2の実施の形態となるFM復調回路の各部の信号を示す入出力波形図である。It is an input-output waveform diagram which shows the signal of each part of the FM demodulation circuit which becomes the 2nd Embodiment of this invention. 本発明の第3の実施の形態となるFM復調回路の構成を示すブロック図である。It is a block diagram which shows the structure of the FM demodulation circuit used as the 3rd Embodiment of this invention. 従来のFM復調回路の構成を示すブロック図である。It is a block diagram which shows the structure of the conventional FM demodulation circuit. 従来のFM復調回路の各部の信号を示す入出力波形図である。It is an input-output waveform diagram which shows the signal of each part of the conventional FM demodulation circuit. FM復調回路に使用される差動AND回路の構成を示す回路図である。It is a circuit diagram which shows the structure of the differential AND circuit used for FM demodulation circuit.

符号の説明Explanation of symbols

1…差動遅延回路、2…差動AND回路、3…差動アンプ、4…レファレンス電圧発生回路、5…差動EXOR回路、6…負荷。
DESCRIPTION OF SYMBOLS 1 ... Differential delay circuit, 2 ... Differential AND circuit, 3 ... Differential amplifier, 4 ... Reference voltage generation circuit, 5 ... Differential EXOR circuit, 6 ... Load.

Claims (4)

差動形式の入力FM信号のエッジを検出して、その検出結果を差動形式で出力するエッジ検出手段と、
正相入力端子と逆相入力端子のうち一方だけが前記エッジ検出手段の正相出力端子あるいは逆相出力端子と接続された差動増幅手段と、
この差動増幅手段の正相入力端子と逆相入力端子のうち、前記エッジ検出手段の出力端子と接続されていない方の入力端子にレファレンス電圧を与えるレファレンス電圧発生回路とを有することを特徴とするFM復調回路。
Edge detection means for detecting an edge of a differential input FM signal and outputting the detection result in a differential format;
Differential amplification means in which only one of the positive phase input terminal and the negative phase input terminal is connected to the positive phase output terminal or the negative phase output terminal of the edge detection means;
A reference voltage generating circuit that applies a reference voltage to an input terminal that is not connected to the output terminal of the edge detection means, out of the positive phase input terminal and the negative phase input terminal of the differential amplification means, FM demodulator circuit.
請求項1記載のFM復調回路において、
前記エッジ検出手段は、
前記差動形式の入力FM信号を遅延させた差動形式の信号を出力する差動遅延回路と、
前記差動形式の入力FM信号を第1の入力とし、前記差動遅延回路から出力された差動形式の信号を第2の入力とし、前記第1の入力と前記第2の入力との論理積の結果を差動形式で出力する差動AND回路とからなることを特徴とするFM復調回路。
The FM demodulation circuit according to claim 1, wherein
The edge detection means includes
A differential delay circuit for outputting a differential signal obtained by delaying the differential input FM signal;
The differential input FM signal is used as a first input, the differential signal output from the differential delay circuit is used as a second input, and the logic of the first input and the second input is determined. An FM demodulation circuit comprising: a differential AND circuit that outputs a product result in a differential format.
請求項1記載のFM復調回路において、
前記エッジ検出手段は、
前記差動形式の入力FM信号を遅延させた差動形式の信号を出力する差動遅延回路と、
前記差動形式の入力FM信号を第1の入力とし、前記差動遅延回路から出力された差動形式の信号を第2の入力とし、前記第1の入力と前記第2の入力との排他的論理和の結果を差動形式で出力する差動EXOR回路とからなることを特徴とするFM復調回路。
The FM demodulation circuit according to claim 1, wherein
The edge detection means includes
A differential delay circuit for outputting a differential signal obtained by delaying the differential input FM signal;
The differential input FM signal is a first input, the differential signal output from the differential delay circuit is a second input, and the first input and the second input are exclusive. An FM demodulating circuit comprising: a differential EXOR circuit that outputs a result of a logical OR in a differential format.
請求項1記載のFM復調回路において、
さらに、前記エッジ検出手段の正相出力端子と逆相出力端子のうち、前記差動増幅手段の入力端子と接続されていない方の出力端子に接続された負荷回路を有することを特徴とするFM復調回路。
The FM demodulation circuit according to claim 1, wherein
Furthermore, it has a load circuit connected to the output terminal which is not connected to the input terminal of the differential amplification means among the positive phase output terminal and the negative phase output terminal of the edge detection means. Demodulator circuit.
JP2005028850A 2005-02-04 2005-02-04 FM demodulation circuit Expired - Fee Related JP4408085B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023026397A1 (en) * 2021-08-25 2023-03-02 日本電信電話株式会社 Signal amplification method and optical receiver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023026397A1 (en) * 2021-08-25 2023-03-02 日本電信電話株式会社 Signal amplification method and optical receiver

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