KR20040008819A - Receiver of communication system having offset voltage compensation circuit - Google Patents

Abstract

PURPOSE: A receiver of a communication system including an offset voltage compensating circuit is provided to extract a DC value loaded into an input signal without using a capacitor, and to compare DC values of a differential input signal and a differential output signal, thereby compensating the DC values on a signal path. CONSTITUTION: A common mode bias circuit(12) is connected between an inverting terminal and a non-inverting input terminal, and applies common mode voltages(VCM) to the inverting and the non-inverting input terminals. An offset voltage compensator(13) comprises as follows. CMVE(Common Mode Voltage Extraction) circuits(14,15) extract the common mode voltages(VCM), respectively, from front nodes of the inverting/the non-inverting input terminals. An average circuit(16) averages the common mode voltages(VCM+,VCM-). A voltage-to-current converter(17) converts the averaged common mode voltages into current values, and applies the current values to back nodes of the input terminals.

Description

Receiver of communication system having offset voltage compensation circuit

The present invention relates to a receiver applied to a communication system, and more particularly, to compensate for the DC offset voltage at the differential input and the differential output of the differential amplifier to perform normal differential amplification to prevent distortion of the signal. A receiver in a communication system comprising an offset voltage compensation circuit.

1 is a block diagram of a receiver applied to a general communication system.

Low Noise Amplifier (LNA) 1 for amplifying the received signal with minimum noise, Mixer 2 for changing the frequency of the RF band to a desired frequency, and spurious components generated by the mixing operation. Filter (3) for removing them, a variable gain amplifier (VGA) 4 for keeping the output signal constant, and a demodulator (5) for demodulating the modulated signal and restoring it to the original signal (5). ).

Here, the LNA 1 is an amplifier that amplifies the signal while minimizing the noise added to the input signal, the mixer 2 is a means for changing the frequency of the input signal to a specific frequency for signal processing, and the filter 3 ) Is a means having the characteristic of passing or removing only a specific frequency band desired.

In addition, the VGA 4 is an amplifier that maintains a constant output size by varying amplification gain. Instead of the VGA 4, a limiter, which is an amplifier having a predetermined output size, may be used instead of the VGA 4. have.

In such a system, since the stages are cascaded to each other, the offset voltage is amplified with the signal and signal processing is performed unless the DC offset voltage value generated in the previous stage is removed. Therefore, signal distortion occurs and the amplification degree of the differential amplification is lowered.

FIG. 2 is a detailed block diagram of the VGA of the receiver shown in FIG. 1.

The VGA 4 is composed of a plurality of cascaded amplifying circuit blocks 6, 7, 8. In order to effectively control common mode noise generated in the amplifying circuit blocks 6, 7, 8, the amplifying circuit blocks 6, 7, 8 are cascaded to have a differential input and a differential output form. .

3 is a waveform diagram illustrating a differential input signal and a differential output signal of each of the differential amplifiers 6, 7 and 8 shown in FIG. 2. Here, the input signals IN +, IN- and the output signals OUT +, OUT- will be described by taking an example of signals having phases opposite to each other.

The differential input signals IN + and IN- are signals that are 180 degrees out of phase with each other, where each signal has the same common mode voltage VCM, and only AC signals have opposite phase characteristics. When amplified, amplification characteristics can be effectively obtained during signal processing of the amplifying circuit blocks 6, 7 and 8.

4 is a waveform diagram illustrating a differential input signal and a differential output signal including the offset voltage VOS of each of the differential amplifiers 6, 7 and 8 shown in FIG. 2. Here, the input signals IN +, IN- and the output signals OUT +, OUT- will be described by taking an example of signals having phases opposite to each other.

When the differential input signals IN + and IN- do not have the same common mode voltage VCM, the difference between the common mode voltages VCM of the differential input signals IN + and IN- is also amplified and output through the differential amplifiers 6, 7, and 8. The common mode voltages VCM of the differential output signals OUT + and OUT- also differ.

As such, the amplification degree at which the common mode voltage VCM amplifies other signals is lower than the amplification degree at which the common mode voltage VCM amplifies the same signal. It will be distorted.

Therefore, when amplifying the differential input signals IN + and IN- including the offset voltage VOS, a high pass filter (hereinafter referred to as HPF) is used to compensate for the offset voltage VOS.

5 is a block diagram illustrating a differential amplifier that compensates for offset voltage VOS using HPF. The HPF can be connected to the front and rear ends of the differential amplifier respectively, but here is an example of connecting the front end only.

The HPF 9 is connected to the input of the differential amplifier 6 to compensate for the offset voltage VOS.

The HPF 9 uses the HPF which passes only the high frequency signal to remove only the DC voltage and transmit only the AC signal among the differential output signals connected to the next stage. Here, the HPF 9 mainly blocks a DC component by using a capacitor. When the frequencies of the input signals IN + and IN- are high, a relatively small capacitor can be used to sufficiently block the DC component.

However, since the blocks after the frequency-converting mixer 2 mainly process low frequency signals, it is necessary to use very large capacitors when using capacitors.

Therefore, the layout area is greatly increased, the time delay of the HPF 9 used is also very large, and the signal processing speed of the entire path is slowed, resulting in signal distortion.

An object of the present invention for solving the above problems is to extract a DC value carried in an input signal without using a capacitor, and compare the DC value carried in each of the differential input signal and the differential output signal to compensate for the value in the signal path. will be.

1 is a block diagram of a receiver applied to a general communication system.

2 is a detailed block diagram of the VGA of the receiver shown in FIG. 1;

3 is a waveform diagram showing a differential input signal and a differential output signal of each differential amplifier shown in FIG. 2;

4 is a waveform diagram illustrating a differential input signal and a differential output signal including the offset voltage VOS of each differential amplifier shown in FIG.

5 is a block diagram illustrating a differential amplifier that compensates for offset voltage VOS using HPF.

Fig. 6 is a block diagram showing the main part of a receiver of a communication system including an offset voltage compensation circuit according to the present invention.

FIG. 7 is a detailed circuit diagram showing a detailed circuit of the offset voltage compensation circuit shown in FIG.

<Description of Symbols for Major Parts of Drawings>

11: differential amplifier

12: common mode bias section

13: DC offset voltage compensation unit

14, 15: Common Mode Voltage Extraction

16: Average Circuit

17: Voltage to Current Converter

18, 19: Threshold Voltage Detector

20, 21, 22: buffer

R1, R2, R3, R4, R5, R6: Resistance

A receiver of a communication system including the offset voltage compensation circuit of the present invention for achieving the above object,

Low Noise Amplifier (LNA), which amplifies the received signal with minimum noise, Mixer that changes the frequency of the RF band to a desired frequency, and Filter that removes spurious components caused by the mixing operation. In the receiver of the communication system including a variable gain amplifier (VGA) for maintaining a constant size of the output signal, and a demodulator (Demodulation) for demodulating the modulated signal to restore the original signal,

The VGA includes a plurality of cascaded differential amplifiers and includes an offset voltage compensation circuit in front of each of the plurality of differential amplifiers.

The offset voltage compensation circuit,

Inverting and non-inverting common mode voltage extracting means for extracting common mode voltages of the inverting and non-inverting input terminals of the differential amplifier, respectively;

An average means for averaging the inverted and non-inverted common mode voltages extracted by each common mode voltage extracting means; And

And means for converting the average common mode voltage output by the averaging means into a current and applying the voltage to the current to the input terminal of the differential amplifier, respectively.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 6 is a block diagram illustrating an essential part of a receiver of a communication system including an offset voltage compensation circuit according to the present invention. Here, the case where the offset voltage compensation circuit is connected to the front end of the differential amplifier 11 is demonstrated as an example.

The common mode bias unit 12 is connected between the inverting and non-inverting input terminals of the differential amplifier 11 and applies the common mode voltage VCM to the inverting and non-inverting input terminals of the differential amplifier 11, respectively.

The offset voltage compensator 13 is connected between both ends of the common mode bias unit 12 to compensate for the offset voltages VOS of the input signals IN + and IN- of the differential amplifier 11.

In addition, the offset voltage compensator 13 extracts the common mode voltages VCM of the input signals IN + and IN- from the nodes in front of the inverted and non-inverted input terminals of the differential amplifier 11 to which the common mode bias unit 12 is connected. Average part of the inverted and non-inverted common mode voltage extraction unit (CMVE) 14 and 15 and the common mode voltages VCM + and VCM- extracted by the common mode voltage extraction units 14 and 15 respectively. (16) and a voltage applied to the rear node of the inverting and non-inverting input terminals of the differential amplifier 11 to which the common mode bias unit 12 is connected by converting the average common mode voltage VCMA of the average unit 16 into a current value. And a current converting section 17.

Here, the common mode voltage extractor 14 and 15 may include a threshold detector, a low pass filter (LPF), a peak valley detector, a rectifying circuit, or the like as needed. A look up table stored in a read only memory (ROM) may be used.

FIG. 7 is a detailed circuit diagram illustrating a detailed circuit of the offset voltage compensation circuit illustrated in FIG. 6. Here, the common mode voltage extraction units 14 and 15 will be described taking the case of using the threshold voltage detectors 18 and 19 as an example.

First, the common mode bias unit 12 is composed of two resistors R1 and R2 connected in series between the inverting and non-inverting input terminals of the differential amplifier 11, and the common mode voltage VCM at the common node of the two resistors R1 and R2. It is configured to be applied.

The offset voltage compensator 13 includes inverted and non-inverted threshold voltage detectors 18 and 19, an average unit 16, and a voltage-current converter 17.

The inverted and non-inverted threshold voltage detectors 18 and 19 are the common mode voltages VCM of the input signals IN + and IN- at the node in front of the inverted and non-inverted input terminals of the differential amplifier 11 to which the common mode bias unit 12 is connected. Respectively.

The average unit 16 includes buffers 20 and 21 for buffering the common mode voltages VCM + and VCM- respectively detected by the inverted and non-inverted threshold voltage detectors 18 and 19, and the respective buffers 20 and 21. Resistors R3 and R4 connected to an output terminal of the capacitor, and a buffer 22 buffering a voltage of a common node of the resistors R3 and R4.

The voltage-current converter 17 includes resistors R5 and R6 respectively connected between the output terminal of the average unit 16 and the input terminal of the differential amplifier 11.

The threshold voltage detectors 18 and 19 detect the common mode voltages VCM + and VCM- for the input signals IN + and IN-, respectively.

The average unit 16 averages the DC voltages of the common mode voltages VCM + and VCM- detected by the threshold voltage detectors 18 and 19.

That is, the detected common mode voltages VCM + and VCM- are respectively buffered by two buffers 20 and 21 and again buffered by one buffer 22 while the average common mode voltages of the two common mode voltages VCM + and VCM- are. Output to VCMA. The average common mode voltage VCMA corresponds to the center value of the DC offset voltage.

The average common mode voltage VCMA is converted into current by the voltage-current converter 17 and input to the input terminal of the differential amplifier 11. That is, the average common mode voltage VCMA is converted to current by two resistors R5 and R6.

Therefore, in the common mode bias section 12 to which the common mode voltage VCM of the actual circuit is applied, the two differential inputs IN + in the DC offset compensation section 13 for the DC offset voltages VOS + and VOS- respectively. In other words, the difference between the center value VCMA of the common mode voltages VCM + and VCM- of the IN- and the common mode voltage VCM of the actual differential input is converted into a current change and put into the differential input.

If the common mode voltages VCM + and VCM- of the two differential inputs IN + and IN- are the same, the output DC voltage VCMA of the average unit 13 is equal to the common mode voltage VCM. Accordingly, no current flows through the resistors R1 and R2 of the common mode bias unit 12 and the resistors R5 and R6 of the voltage-current converter 17.

However, if the common mode voltages VCM + and VCM- of the differential inputs IN + and IN- are different from each other, the output DC voltage VCMA of the average unit 13 becomes different from the common mode voltage VCM, and the resistors R1 and R by an amount correcting the difference. Current flows through resistor R5, resistor R2 and resistor R6, resulting in equalization of common mode voltages VCM + and VCM- of differential inputs IN + and IN-.

The common mode voltage extracting units 14 and 15, the average unit 16 and the voltage-current converting unit 17 constituting the offset voltage compensating unit 13 according to the present invention occupy a small area because they operate at a low frequency. do.

Here, the DC offset voltage compensator 13 is connected only to the input terminal of the differential amplifier 11, but may also be connected to the output terminal to compensate the offset voltage once again.

As described above, the offset voltage compensation circuit of the differential amplifier used in the receiver of the communication system according to the present invention has a layout area by using an offset voltage compensation circuit composed of a buffer and a resistor instead of a capacitor in the case of a receiver operating at a low frequency. This can greatly reduce the effect.

In addition, in the offset voltage compensation circuit according to the present invention, the present invention may be connected in parallel at any position of the cascaded differential input / output terminals.

Since the DC offset compensation circuit of the present invention operates at a very low frequency, the configuration of the offset voltage compensation circuit of the present invention has an effect of minimizing current consumption.

In addition, the resistance value used in the voltage-current conversion circuit of the DC offset compensation circuit of the present invention is made larger than the resistance value of the common mode bias circuit, thereby minimizing the reduction of the gain by the DC offset compensation circuit. have.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (8)

Low Noise Amplifier (LNA) to amplify the received signal with minimum noise, Mixer to change the frequency of the RF band to the desired frequency, Filter to remove spurious components caused by the mixing operation In the receiver of the communication system including a variable gain amplifier (VGA) for maintaining a constant size of the output signal, and a demodulator (Demodulation) for demodulating the modulated signal to restore the original signal, The VGA includes a plurality of cascaded differential amplifiers and includes an offset voltage compensation circuit in front of each of the plurality of differential amplifiers. The offset voltage compensation circuit, Inverting and non-inverting common mode voltage extracting means for extracting common mode voltages of the inverting and non-inverting input terminals of the differential amplifier, respectively; An average means for averaging the inverted and non-inverted common mode voltages extracted by each common mode voltage extracting means; And And a voltage-to-current converting means for converting the average common mode voltage outputted by the averaging means into a current and applying them to the input terminals of the differential amplifier, respectively. The method of claim 1, An offset voltage compensation circuit connected between the inverting and non-inverting input terminals of the differential amplifier, and further comprising common mode biasing means for applying a common mode voltage to the inverting and non-inverting input terminals of the differential amplifier, respectively. Receiver of a communication system comprising a. The method of claim 2, The common mode biasing means, Comprising two resistors connected in series between the inverting and the non-inverting input terminal of the differential amplifier, the common mode voltage is applied to the common node of the two resistors, characterized in that the communication system including an offset voltage compensation circuit receiving set. The method of claim 1, And an offset voltage compensation circuit further connected to the rear end of each differential amplifier. The method of claim 1, The common mode voltage extracting means, Lookup tables stored in threshold detectors, low pass filters (LPFs), peak valley detectors, smoothing circuits, and read-only memories (ROMs), depending on the receiver of the communications system (Look UpTable) receiver of a communication system comprising an offset voltage compensation circuit, characterized in that consisting of any one. The method of claim 1, The average means, Inverting and non-inverting buffers respectively buffering the inverted and non-inverted common mode voltages extracted by the common mode voltage extracting means; And And an average buffer for averaging and outputting outputs of the inverted and non-inverted buffers. The method of claim 6, The average means, A receiver of the communication system comprising an offset voltage compensation circuit further comprising two resistors connected respectively to the output terminals of the inverting and non-inverting buffers, the voltage of the common node being connected to the input terminal of the average buffer. . The method of claim 1, The voltage-current conversion means, And an offset voltage compensation circuit comprising two resistors each connected between an output terminal of said averaging means and an inverting and non-inverting input terminal of said differential amplifier.