JP2006210690A - Semiconductor device for surge protection - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a surge protecting semiconductor device which has a low terminal-to-terminal capacity and high surge restraint by eliminating deterioration of surge restraint due to rise of a breakdown voltage of the semiconductor device caused for realizing the low terminal-to-terminal capacity in the surge protecting semiconductor device. <P>SOLUTION: A plurality of p-type semiconductor layers 3, 4, 5 are formed in a line holding a low concentration n-type semiconductor layer 2 therebetween in a portion inside the low concentration n-type semiconductor layer 2 formed on the n-type semiconductor substrate 1 not to come into contact with the n-type semiconductor substrate 1. An anode electrode 7 is formed in the surface of the p-type semiconductor layer 3 of one line end, and a cathode electrode 8 is formed in the surface of the p-type semiconductor layer 5 of the other line end. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device for surge protection.

  As a semiconductor device for surge protection, it is widely known that when a surge reaching the breakdown voltage of the constant voltage diode is applied, the constant voltage diode causes the surge current to flow in the ground direction to suppress the surge.

  As a conventional semiconductor device for surge protection, it has a high surge suppression (clamp voltage is low) that does not destroy the device when a surge is applied, and a low terminal capacitance that does not affect the characteristics of the device. (For example, refer to Patent Document 1).

  FIG. 2 shows a conventional surge protection semiconductor device described in Patent Document 1. In FIG. In FIG. 2, 110 is a high concentration N type semiconductor substrate, 111 is a low concentration N type semiconductor layer, 112 is a P type semiconductor layer, 113 is a high concentration N type semiconductor layer, 114 is a cathode electrode, 115 is an anode electrode, and 116 is an insulating material. J11 is an interface between the low-concentration N-type semiconductor layer 111 and the P-type semiconductor layer 112, and J12 is an interface between the high-concentration N-type semiconductor layer 113 and the P-type semiconductor layer 112.

A low-concentration N-type semiconductor layer 111 is provided above the high-concentration N-type semiconductor substrate 110, and a region of the P-type semiconductor layer 112 is selectively formed from the surface of the low-concentration N-type semiconductor layer 111 into the layer. A region of the high-concentration N-type semiconductor layer 113 is selectively formed from the surface of the P-type semiconductor layer 112 into the layer, and the surface region of the low-concentration N-type semiconductor layer 111, the surface region of the P-type semiconductor layer 112, and the high-concentration N On the first main surface of the semiconductor substrate composed of the surface region of the type semiconductor layer 113, an insulating film 116 opened in the center of the surface region of the high concentration N type semiconductor layer 113 is formed, and the high concentration N exposed by insulation is exposed. The cathode electrode 114 is formed so as to cover a part of the surface of the insulating film 116 from the surface of the type semiconductor layer 113, and the anode electrode 115 is formed on the second main surface of the semiconductor substrate composed of the surface of the high concentration N type semiconductor substrate 110. Was formed.
JP 2003-110119 A

  However, in the above-described conventional configuration, the parasitic capacitance and surge suppression power are such that the semiconductor junction (J11) formed by the P-type semiconductor layer 112 and the low-concentration N-type semiconductor layer 111, and the high-concentration N-type semiconductor layer 113 It depends on the breakdown voltage of the semiconductor junction (J12) formed with the P-type semiconductor layer 112. In order to reduce the parasitic capacitance, it is effective to increase the specific resistance of the low-concentration N-type semiconductor layer 111, but if the specific resistance of the low-concentration N-type semiconductor layer 111 is increased, the breakdown of the semiconductor junctions J11 and J12 The voltage increases. However, if the breakdown voltage of the semiconductor junctions J11 and J12 is increased, the surge suppression voltage (clamp voltage) is increased, so that the surge suppression power is reduced. Due to the above-described mechanism, the parasitic capacitance and the surge suppression power are traded off, and a semiconductor device for surge protection that satisfies both requirements cannot be achieved.

  SUMMARY OF THE INVENTION The present invention solves the above-described conventional problems, and an object thereof is to provide a semiconductor device for surge protection having a high surge suppression power with a low inter-terminal capacitance and a reduced surge suppression voltage (clamp voltage).

  In order to solve the above-described conventional problems, a semiconductor device for surge protection according to the present invention forms a low-concentration first conductive semiconductor layer on a first conductive-type semiconductor substrate, and a part of the low-concentration first conductive-type semiconductor layer. In addition, a plurality of second conductivity type semiconductor layers are formed in a row with the low-concentration first conductivity type semiconductor layer interposed therebetween so as not to contact the first conductivity type semiconductor substrate. Thereafter, an insulating film is formed on the surfaces of the low-concentration first conductive type semiconductor layer and the plurality of second conductive type semiconductor layers, and the second conductive at the end of the plurality of second conductive type semiconductor layer sequences. The anode contact window is formed in the type semiconductor layer, the cathode contact window is formed in the second conductive type semiconductor layer at the other end of the column, and the surface anode electrode and the surface cathode electrode are formed so as to cover the contact window. And

  In the semiconductor device for low-capacity surge protection, a semiconductor junction is formed by a low-concentration first conductive semiconductor layer and a plurality of second conductive semiconductor layers, and the breakdown voltage at the side portion of the semiconductor junction is punch-through. As determined by the type, the width of the low-concentration first conductive semiconductor layer sandwiched between the plurality of second conductive semiconductor layers is determined. The breakdown voltage at the bottom of each semiconductor junction is determined by the avalanche type, and the concentration of the low-concentration first conductivity type semiconductor layer is set so as to be higher than the breakdown voltage of the side surface determined by the punch-through type. Determine the thickness of the layer.

となり、端子間容量を低減することができる。これによって降伏電圧を大きくせずに寄生容量を低減できる。 In such a configuration, the width of the low-concentration first conductive type semiconductor layer sandwiched between the adjacent second conductive type semiconductor layers is narrowed, the extension of the depletion layer is limited, and the breakdown voltage of the semiconductor device for surge protection is reduced to the punch-through type. Therefore, the specific resistance of the low-concentration first conductivity type semiconductor layer can be increased and the capacitance can be reduced without increasing the breakdown voltage. In addition, there are a plurality of interfaces between the low-concentration first conductive semiconductor layer and the second conductive semiconductor layer between the anode electrode and the cathode electrode, and a plurality of diodes are wired in series in an equivalent circuit. Therefore, when the parasitic capacitance is C, the inter-terminal capacitance C _t is expressed by the equation (1).

Thus, the inter-terminal capacitance can be reduced. This can reduce parasitic capacitance without increasing the breakdown voltage.

  As described above, in the semiconductor device for surge protection according to the present invention, the inter-terminal capacitance can be reduced without increasing the breakdown voltage of the device, so that the surge suppression power that lowers the surge suppression voltage (clamp voltage) with the low inter-terminal capacitance. High surge protection semiconductor device can be provided.

  Embodiments of the present invention will be described below.

  FIG. 1A is a front view of a semiconductor device for surge protection according to an embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line AB in FIG. 1A and 1B, a low-concentration N-type semiconductor layer 2 that is a low-concentration first conductive semiconductor layer is formed by epitaxial growth on an N-type semiconductor substrate 1 that is a first conductive-type semiconductor substrate. ing. The P-type semiconductor layers 3, 4, 5 are arranged at regular intervals from the surface of the low-concentration N-type semiconductor layer 2 to the inside so that the P-type semiconductor layers 3, 4, 5 do not contact the N-type semiconductor substrate 1 as the second conductivity type region for forming the PN junction. It is formed in a stripe shape when viewed from the front. Here, the interface between the low-concentration N-type semiconductor layer 2 and the first P-type semiconductor layer 3 is J1, and the interface between the low-concentration N-type semiconductor layer 2 and the second P-type semiconductor layer 4 is J2. The interface between the N-type semiconductor layer 2 and the third P-type semiconductor layer 5 is J3.

  An insulating film 6 made of a thermal oxide film is formed on the surface of the low-concentration N-type semiconductor layer 2 so that a part of the low-concentration N-type semiconductor layer 2 and the P-type semiconductor layers 3 and 5 are exposed. An anode electrode 7 made of aluminum is formed on the P-type semiconductor layer 3, and a cathode electrode 8 made of aluminum is formed on the P-type semiconductor layer 5.

  According to this configuration, the semiconductor device forms a PN junction by the low-concentration N-type semiconductor layer 2 and the plurality of P-type semiconductor layers 3, 4, and 5, and the breakdown voltage of the side surface of the PN junction is low. As determined by the punch-through type, the width of the low-concentration N-type semiconductor layer 2 sandwiched between the plurality of P-type semiconductor layers 3, 4, and 5 is determined. The breakdown voltage of the low-concentration N-type semiconductor layer 2 is determined so that the breakdown voltage at the bottom of each PN junction is determined by the avalanche type and higher than the breakdown voltage of the side surface determined by the punch-through type. Determine the thickness. In such a configuration, the width of the low-concentration N-type semiconductor layer 2 sandwiched between adjacent P-type semiconductor layers 3, 4, and 5 is narrowed, the extension of the depletion layer is limited, and the breakdown voltage of the semiconductor device is a punch-through type. By determining, the specific resistance of the low-concentration N-type semiconductor layer 2 can be increased and the parasitic capacitance can be reduced without increasing the breakdown voltage.

For example, at this time, the impurity concentration of the N-type semiconductor substrate 1 is 10 ²⁰ [cm ⁻³ ], the impurity concentration of the low-concentration N-type semiconductor layer 2 is 10 ¹⁴ [cm ⁻³ ], the thickness is 20 [μm], and the P-type semiconductor The impurity concentration of the layers 3, 4 and 5 is 10 ²⁰ [cm ⁻³ ], the thickness is 5 [μm], and the width of the low-concentration N-type semiconductor layer 2 sandwiched between adjacent P-type semiconductor layers is 1 [μm]. Then, the breakdown voltage at the bottom of the interface J1 between the low-concentration N-type semiconductor layer 2 and the first P-type semiconductor layer 3 is about 200 [V], but the breakdown voltage at the side surface can be about 7 [V]. . According to this, the parasitic capacitance C of the interface J1 between the low-concentration N-type semiconductor layer 2 and the first P-type semiconductor layer 3 is C = 2 × 10 ⁻⁴ [pF / μm ² ]. The same applies to the interface J2 between the low-concentration N-type semiconductor layer 2 and the second P-type semiconductor layer 4 and the interface J3 between the low-concentration N-type semiconductor layer 2 and the third P-type semiconductor layer 5.

となり、また直列に接続することで更なる寄生容量の低減が図れる。実施例の場合、ＰＮ接合が直列に４個接続されているため、端子間容量Ｃ_tは（３）式で表すように

となり、これによって降伏電圧を大きくせずに寄生容量を低減できるものである。上記の実施形態では形成する第２導電型半導体層の数を３個としたが、第２導電型半導体層の数は３個以上であってもよい。なお、本実施の形態による半導体装置は従来から用いられている製造方法により製造できるため、製造方法の説明は省略する。 When the breakdown voltage is 7 V and the surge withstand voltage is 10 kV in the conventional structure, the required PN junction area S is S = 2000 [μm ² ], and the parasitic capacitance is 6 [pF]. When the parasitic capacitance C ₃ of the P-type semiconductor layer 3 is calculated, as expressed by the following equation (2):

Further, the parasitic capacitance can be further reduced by connecting them in series. In the case of the embodiment, since four PN junctions are connected in series, the inter-terminal capacitance C _t is expressed by equation (3).

Thus, the parasitic capacitance can be reduced without increasing the breakdown voltage. In the above embodiment, the number of second conductive semiconductor layers to be formed is three, but the number of second conductive semiconductor layers may be three or more. Since the semiconductor device according to the present embodiment can be manufactured by a conventionally used manufacturing method, description of the manufacturing method is omitted.

  This is useful for improving high surge suppression power by reducing the surge suppression voltage (clamp voltage) with low terminal capacitance, and is particularly applicable to semiconductor devices for surge protection.

(A) Front view of a semiconductor device for surge protection according to an embodiment of the present invention (b) Cross-sectional view taken along line AB in FIG. 1 (a) Sectional view showing the overall structure of a conventional semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st conductivity type semiconductor substrate 2 Low concentration 1st conductivity type semiconductor layer 3, 4, 5 P type semiconductor layer 6, 116 Insulating film 7 Anode electrode 8 Cathode electrode 114 Cathode electrode 115 Anode electrode 110 High concentration N type semiconductor substrate 111 Low-concentration N-type semiconductor layer 112 P-type semiconductor layer 113 High-concentration N-type semiconductor layer J1 Interface J2 between low-concentration N-type semiconductor layer 2 and P-type semiconductor layer 3 Low-concentration N-type semiconductor layer 2 and P-type semiconductor layer 4 Interface J3 interface J11 between low-concentration N-type semiconductor layer 2 and P-type semiconductor layer 5 interface J12 interface P-type semiconductor layer 112 and low-concentration N-type semiconductor layer 111 J12 high-concentration N-type semiconductor layer 113 and P-type semiconductor layer 112 Interface with

Claims (1)

A low-concentration first conductive semiconductor layer is formed on the upper layer of the first conductive semiconductor substrate, and second conductive-type regions forming PN junctions from the surface of the low-concentration first conductive semiconductor layer to the inside thereof are arranged at regular intervals. The insulating film is formed on the surface of the low-concentration N-type semiconductor layer 2 so as to expose a part of the low-concentration first conductive semiconductor layer and the second conductive-type semiconductor region. A surge protection semiconductor device, wherein electrodes are formed in at least two places of the second conductivity type semiconductor region.

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