JPS61147570A - Schottky barrier semiconductor device - Google Patents

Abstract

PURPOSE:To improve the surge strength at the cost of a bit of breakdown voltage in the inverse direction by a method where in P<+> type silicon regions in a Schottky barrier semiconductor device are formed deeper. CONSTITUTION:P<+> type silicon regions 4 are diffused deeper than conventional ones to lower the punchthrough voltage directly below the regions 4 remarkably comparing with conventional punchthrough voltage. On the other hand, the conventional surge strength at the low barrier height part formed of a metallic layer 7 and an N-type silicon region 2 is around 80V. The regions 4 are deeply diffused so that the punchthrough voltage directly below the regions 4 may be set up at the voltage not exceeding 80V. Resultantly even if any surge volt age exceeding the surge breakdown voltage is impressed on the part between the layer 7 and an electrode 8, the punchthrough voltage may be generated below the regions 4 to pass any excessive surge voltage through the intermedi ary of the layers 2 and electrode 8. Through these procedures, any surge break down voltage in the Schottky barrier may be prevented from being generated.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a Schottky)<'I)7 semiconductor device having improved surge withstand voltage characteristics.

(b) Conventional technology Schottky barrier semiconductor devices have the characteristics of low forward voltage and low forward power loss, and can they be applied to output rectifier diodes of switching power supply circuits, etc.? r input,
The trap applied to the output rectifier diode of the single-speed switching power source circuit is required to have a high reverse breakdown voltage and a high breakdown withstand voltage (surge withstand voltage).

In the conventional Schottky barrier semiconductor device, the
As shown in Publication No. 5183 (HOIL29/48), improvements have been made to increase the reverse breakdown voltage. That is, it is a guard ring structure or a field plate structure. However, the guard ring structure only reduces the reverse current at the periphery of the metal-semiconductor contact, but cannot reduce the reverse current at the center of the metal-semiconductor contact. The field plate structure also improves the characteristics of the peripheral area of the metal-semiconductor contact. Therefore, in either structure, it was not possible to significantly increase the breakdown voltage of the Schottky barrier semiconductor device.

The Schottky barrier semiconductor device disclosed in Japanese Patent Publication No. 59-35183 makes it possible to reduce reverse current and increase reverse breakdown voltage.

To explain in detail with reference to FIGS. 3 and 4, a silicon substrate 03 having an N-type silicon region a2 epitaxially grown on an N-type silicon layer Qll is prepared, and a plurality of P-type silicon regions I are formed here. A metal layer aη made of chromium is provided using the opening 4 of the oxide film.

It is desirable to form the chromium metal layer αD by performing heat treatment for 6 minutes to 9000 minutes at a temperature of 350° C. to 500° C. after vapor deposition, whereby a stable barrier hydride of 0.65 ± 0.015 eV can be obtained. . Silicon substrate (
As is clear from Figure 4 showing the 1310 surface condition, P
The type silicon region (14) consists of four strip-shaped portions (14a) and upper and lower connecting portions (14b) and (14c).Therefore, in plan view, there are a plurality of rectangular shapes N in the P+ type silicon region I. A type silicon region α3 is arranged, and P type silicon regions I and N type silicon regions α4 are alternately exposed on the surface.

+ The distance between the P-type silicon regions a4 is the metal layer αη
The size is such that the P type silicon regions α are connected to each other by a space charge region generated when a negative voltage is applied to the lower metal electrode α and a positive voltage is applied to the lower metal electrode α. In this case, the voltage lower than the reverse breakdown voltage of the Schittky barrier formed by the N-type silicon region α2 and the metal layer αη is
In a Schottky barrier semiconductor device having the above structure, when a high reverse voltage is applied, a PN consisting of a P-type silicon region I and an N-type silicon region aa is connected to each other. The space charge region formed by the bonding expands, and the P-type silicon regions (141) are connected by the space charge region, and a space charge region is formed in the entire lower region of the metal layer (17) in contact with the silicon substrate αJ. is distributed.

As a result, the space charge region blocks the reverse current,
High reverse breakdown voltage can be achieved.

el Problems to be Solved by the Invention Although the conventional Schottky barrier semiconductor device can achieve an improvement in reverse breakdown voltage, it has the drawback that it cannot achieve an improvement in breakdown strength required for switching power supply circuits and the like.

That is, in a conventional Schottky barrier semiconductor device, if the N-cavity silicon region is approximately 11 μm thick, the P-cavity silicon region I is approximately 11 μm thick.
was formed to a depth of about 3 μm at the most, so it was operated in the range where the reverse breakdown voltage was highest, as shown in FIG. However, within this range, the surge withstand capability is used at its lowest range, as is clear from FIG. 2, and the conventional Schottky barrier semiconductor device has the disadvantage that the surge withstand capability is extremely weak in degrees centigrade.

In view of the above, the present invention was devised by diffusing the P-type silicon region of the Schottky barrier semiconductor device, thereby sacrificing the reverse breakdown voltage, while greatly increasing the surge resistance. An improved Schottky barrier semiconductor device is realized.

(E) Function The Schottky barrier semiconductor device according to the present invention has a P+ type silicon region (4) diffused deeper than the conventional one. The punch-through voltage under the formed PN junction is set low to improve the surge resistance required for switching power supplies and the like.

(F) Embodiment A Schottky barrier semiconductor device according to the present invention will be described in detail with reference to FIGS. 1 and 2.

In the Schottky barrier semiconductor device according to the present invention, a silicon substrate (3) having an N-type silicon region (2) which is epitaxially grown on an N+-type silicon layer (11 and serving as a tenth semiconductor region) is prepared, and a second semiconductor layer (3) is prepared. A plurality of P-type silicon regions (4) are formed, and an oxide film (5) is formed.
A metal layer (7) that forms a Schottky barrier made of molybdenum is provided using the opening (6). This metal layer (with a strength of 0.00000.
A barrier hydride of 65±0.015 eV is formed. P
The mold silicon region (4) has four strip-shaped parts (14a) and upper and lower joint parts (14b) as in the conventional one shown in FIG.
, (14C), in which a plurality of rectangular N-type silicon regions (2) are arranged in a P-type silicon region (4), and a P-type silicon region (4) is formed in a plane.
) and N-type silicon regions (2) are alternately arranged on the surface. The metal layer (force) contacts the P-type silicon region (4) and the surrounded N-type silicon region (2), forming a Schottky barrier between the N-type silicon regions (2).

The feature of the present invention lies in the P type silicon region (4).

+ The P-type silicon region (4) is diffused deeper than the conventional one. Specifically, when the N-type silicon region (2) is designed to have a thickness of approximately 11 μm, the conventional P-type silicon region (4), which is diffused to a thickness of at most 3 μm or less, becomes the Pi silicon region (4) of the present invention+. from 3.5μm to 4.5μm
is diffused to a depth of As is clear from FIG. 2, the depth of the P-type silicon region (4) is set within a range where the reverse breakdown voltage decreases but the surge resistance increases. Specifically, in the present invention, a material with a maximum reverse breakdown voltage of about 130V is used at about 110V.

According to the above structure, since the P type silicon region (4) is formed deeply, the punch-through voltage directly under the P type silicon region (4) can be greatly reduced compared to the conventional structure. - The conventional surge resistance at the low part of the barrier hide formed by the metal layer (7) and the N-type silicon region (2) is about 80V as shown in FIG. Therefore, in the present invention, the P type silicon region (4) is deeply diffused so that the punch-through voltage directly under the P type silicon region (4) can be set to 80 V or less. As a result, even if a surge voltage exceeding the surge breakdown voltage of the Schottky barrier is applied between the metal layer (force) and the metal electrode (8) on the back surface, punch-through occurs under the +P type silicon region (4) and the surge voltage N-type silicon layer (2) and metal electrode (
8) Escape via. Therefore, surge breakdown in the Schottky barrier can be prevented, and all the surge voltage can be absorbed by the depletion layer under the P-type silicon region (4). Therefore, as is clear from FIG. 2, the surge resistance can be greatly improved from the conventional 80V to IKV.

(G) Effects of the Invention According to the present invention, by forming the P-type silicon region (4) deeper than before, the surge resistance can be improved by more than 10 times than before, although the reverse breakdown voltage is slightly sacrificed. has. As a result, it is possible to obtain a shut-chip parrier diode that is most suitable for switching power supply circuits, etc., and contributes to the reduction in size and weight of power supply circuits.

Further, the present invention provides P of the conventional Schottky barrier semiconductor device.
This can be achieved simply by deeply diffusing the mold silicon region (4).
It has the advantage that it can be introduced without any increase in process steps.

[Brief explanation of the drawing]

FIG. 1 is a sectional view illustrating the Schottky barrier semiconductor device of the present invention, FIG. 2 is a characteristic diagram illustrating the reverse breakdown voltage characteristics and surge withstand capacity of the Schottky barrier semiconductor device of the present invention and the conventional Schottky barrier semiconductor device, and FIGS. FIG. 4 is a cross-sectional view and a top view illustrating a conventional Schottky barrier semiconductor device. (1) is Nu silicon layer, (2) is N-type silicon layer + region, (2) is semiconductor substrate, (4) is P-type silicon region, (5) is oxide film, (6) is opening, (7) is The metal layer (8) is a metal electrode. Applicant Sanyo Electric Co., Ltd. and one other agent Patent attorney Seiji Sano Figure 1

Claims (1)

[Claims] (1) In a Schottky barrier semiconductor device comprising a first semiconductor region of one conductivity type, a second semiconductor region of the opposite conductivity type provided on the surface of the first semiconductor region, and a Schottky barrier metal layer, A Schottky barrier semiconductor device, characterized in that the second semiconductor region is formed deeply and a punch-through voltage directly under the second semiconductor region is set to be lower than a surge breakdown voltage of the Schottky barrier.