JP2006203228A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To repair a defect of a gate insulating film without oxidizing a metal gate electrode in a MISFET where the metal gate electrode is formed on the much thinned gate insulating film with a thickness of a silicon dioxide reduced thickness of less than 5 nm. <P>SOLUTION: After the W film 11A of a gate electrode material is formed on the gate insulating film 9A having the thickness of the silicon dioxide reduced thickness of less than 5 nm formed on a main surface of a single crystal silicon substrate 1, the silicon substrate 1 is heat-treated in an atmosphere where a mixed gas of moisture and hydrogen is set in a ratio to oxidize the silicon, but the W film 11A is not substantially oxidized by the partial pressure of moisture/hydrogen, thereby, the defect of the gate insulating film 9A under the W film 11A is repaired. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a technology effective when applied to the manufacture of a semiconductor integrated circuit device having a MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a metal gate electrode.

  Patent Document 1 (Japanese Patent Application Laid-Open No. 59-132136 (Kobayashi et al.)) Discloses that a gate electrode having a metal structure made of a W film (or Mo film) is formed on a Si (silicon) substrate and then mixed with water and hydrogen. A technique for selectively oxidizing only Si without oxidizing the W (Mo) film by oxidizing in an atmosphere is disclosed. This utilizes the property that the water / hydrogen partial pressure ratio at which the oxidation-reduction reaction is in equilibrium is different between W (Mo) and Si. The W (Mo) is reduced but Si is oxidized. By setting within such a range, selective oxidation of Si is realized.

  Patent Document 2 (Japanese Patent Laid-Open No. 7-94716 (Muraoka et al.)) Forms a gate electrode having a polymetal structure including a metal nitride layer such as TiN and a metal layer such as W on a Si substrate via a gate oxide film. After that, a technique is disclosed in which oxidation is performed in an atmosphere in which a reducing gas (hydrogen) and an oxidizing gas (water) are diluted with nitrogen. According to this publication, only Si can be selectively oxidized without oxidizing the metal layer, and the denitrification reaction from the metal nitride layer is prevented by diluting the water + hydrogen mixed gas with nitrogen. It is said that oxidation of the metal nitride layer can be prevented at the same time.

  Patent Document 3 (Japanese Patent Application Laid-Open No. 60-160667 (Azuma)) forms a thin film made of a refractory metal such as W or Mo on a silicon substrate and then heat-treats it in a non-oxidizing atmosphere. It discloses a technique for forming a very thin silicon oxide film at the interface between the two by diffusing oxygen stored in the substrate surface.

  Patent Document 4 (Japanese Patent Application Laid-Open No. 11-330468 (Japanese Patent Application No. 10-138939)) discloses a semiconductor wafer using a mixed gas containing water vapor synthesized by a catalyst from hydrogen gas, oxygen gas and hydrogen gas in a polymetal gate. The refractory metal film constituting a part of the gate electrode is not substantially oxidized by heat treatment to improve the profile of the gate insulating film under the edge of the polymetal gate electrode that has been cut by etching. Discloses a method performed under conditions for oxidizing the gate insulating film.

  Patent Document 5 (Japanese Patent Laid-Open No. 10-233505 [0043]) discloses a step of forming a gate oxide film 3 on the surface of a semiconductor substrate, and tungsten, molybdenum, chromium on the surface of the gate oxide film 3. , Tantalum, niobium, vanadium and other metal nitrides or a composite of these metals and metal nitrides, and then a tungsten equilibrium vapor pressure curve (oxidation of tungsten by moisture and tungsten by hydrogen). Heat treatment in an atmosphere containing moisture within the range enclosed by the equilibrium vapor pressure curve of silicon oxidation-reduction, which is also determined thermodynamically, and the relationship between the amount of water added and the temperature at which the oxide reduction reaction equilibrates) Thus, there is a disclosure of performing a heat treatment by selective oxidation of silicon.

In Patent Document 6 (Japanese Patent Laid-Open No. 9-298170, [0028]), a trapping layer capable of trapping water and oxygen is provided in order to improve the adhesion between the low-resistance metal film and the underlying silicon. As a metal constituting the upper layer, the amount of water added in the oxidation-reduction reaction equilibrium atmospheric pressure curve is at least one kind of constituent element of the trapping film provided between the metal film and the silicon film. By using an element that is less than the amount of water added in the equilibrium vapor pressure curve in, the upper metal is not oxidized, only this metal is oxidized, and this metal reacts with the silicon oxide film to capture its oxygen. There is a disclosure of a method in which the underlying silicon is not oxidized.
JP 59-132136 A JP-A-7-94716 JP 60-160667 A Japanese Patent Application Laid-Open No. 11-330468 (Japanese Patent Application No. 10-138939) JP-A-10-233505, paragraph [0043] JP-A-9-298170, paragraph [0028]

  (1) A CMOS-LSI having a circuit composed of a fine MISFET having a gate length of 0.18 μm or less has a low-resistance conductive property including metal in order to reduce gate delay and ensure high-speed operation even during low-voltage operation. It is required to form a gate electrode using a material.

  A promising low-resistance gate electrode material of this type is a composite conductive film (hereinafter referred to as polymetal) in which a refractory metal film is stacked on a polycrystalline silicon film. Polymetal can be used not only as a gate electrode material but also as a wiring material because its sheet resistance is as low as about 2Ω / □. As the refractory metal, W (tungsten), Mo (molybdenum), Ti (titanium), or the like, which shows good low resistance even at a low temperature process of 800 ° C. or less and has high electromigration resistance, is used. When these refractory metal films are laminated directly on the polycrystalline silicon film, the adhesive strength between the two is reduced, or a high-resistance silicide layer is formed at the interface between the two by a high-temperature heat treatment process. Therefore, in an actual polymetal gate, a conductive barrier film made of a metal nitride film such as TiN (titanium nitride) or WN (tungsten nitride) is interposed between the polycrystalline silicon film and the refractory metal film. It consists of a layer structure.

  (2) A CMOS-LSI having a circuit composed of fine MISFETs having a gate length of 0.18 μm or less is one of polymetal gates in order to set the threshold voltage (Vth) low in accordance with the low voltage operation. A so-called dual gate structure in which the n-channel MISFET is n-type and the p-channel MISFET is p-type is being adopted for the polycrystalline silicon film constituting the portion. In this case, the gate electrode of the n-channel type MISFET has a structure in which a refractory metal film is laminated on an n-type polycrystalline silicon film doped with an n-type impurity such as P (phosphorus). The gate electrode has a structure in which a refractory metal film is laminated on a p-type polycrystalline silicon film doped with B (boron) which is a p-type impurity.

  However, as a problem of the above (1), when the gate length of the MISFET becomes 0.18 μm or less, a two-layer structure in which a refractory metal film is laminated on the upper part of the polycrystalline silicon film, and further, there is a conductive property between them. A gate electrode having a three-layer structure with a porous barrier film interposed between them has an extremely large aspect ratio, which makes it difficult to process the gate electrode.

  Further, as the problem of the above (2), B (boron) in the p-type polycrystalline silicon film constituting a part of the gate electrode of the p-channel type MISFET diffuses to the substrate side through the gate oxide film, and p For example, the threshold voltage (Vth) may be changed by changing the flat band voltage (Vfb) of the channel MISFET.

  Therefore, in order to avoid these problems, a so-called metal gate electrode is developed in which a refractory metal film such as W or Mo is directly formed on the gate oxide film without an intermediate layer such as a polycrystalline silicon film. Is underway.

  On the other hand, in order to realize high speed and high performance of the MISFET, it is necessary to reduce the gate oxide film in proportion to the miniaturization of the MISFET. For example, the MISFET having a gate length of about 0.25 μm to 0.2 μm. In this case, a gate oxide film thinner than 5 nm is required.

  However, if the thickness of the gate oxide film is made thinner than 5 nm, a decrease in the withstand voltage due to the generation of direct tunnel current or hot carriers due to stress becomes obvious. Further, when a refractory metal film such as W or Mo is directly formed on such a thin gate oxide film, defects are also generated in the gate oxide film in the vicinity of the interface between them to lower the withstand voltage.

  The defects in the gate oxide film are mainly caused by oxygen vacancies in the Si—O bond. Therefore, this defect can be repaired by heat-treating the substrate in an oxidizing atmosphere and supplying oxygen to the oxygen deficient portion. However, if the substrate is heat-treated in an oxidizing atmosphere, the refractory metal film, which is the gate electrode material deposited on the gate oxide film, is also oxidized at the same time, which increases the resistance of the gate insulating film. .

  As a measure to avoid a decrease in dielectric strength due to the thinning of the gate oxide film, the effective film thickness can be obtained by using an insulating metal oxide such as tantalum oxide having a dielectric constant larger than that of silicon oxide as the gate insulating film material. There is an option to increase the value.

  Since these insulating metal oxides are crystalline materials, in order to obtain the original insulating characteristics, a process of performing heat treatment in an oxygen atmosphere after film formation and supplying oxygen into the film is indispensable. However, when the substrate is heat-treated in an oxidizing atmosphere, the refractory metal film, which is the gate electrode material deposited on the gate insulating film, is also oxidized, so that the resistance of the gate insulating film increases.

  An object of the present invention is to provide a technique for improving the reliability and manufacturing yield of a MISFET in which a metal gate electrode is formed on an ultrathin gate insulating film.

  Another object of the present invention is to provide a technique for improving the reliability and manufacturing yield of a MISFET in which a metal gate electrode is formed on a gate insulating film containing a metal oxide having a dielectric constant higher than that of silicon oxide.

  Another object of the present invention is to provide a method for forming a gate insulating film having a silicon dioxide equivalent film thickness of less than 5 nm.

  Another object of the present invention is to provide a defect repair method for a gate insulating film having a silicon dioxide equivalent film thickness of less than 5 nm.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The method for manufacturing a semiconductor integrated circuit device according to the present invention includes (a) a first refractory metal having a redox equilibrium curve in a gas atmosphere containing moisture and hydrogen on a lower moisture side than that of silicon. Forming a first film on the silicon surface on the first main surface of the wafer; and (b) the moisture / hydrogen partial pressure ratio does not substantially oxidize the silicon surface, and the first high A heat treatment is performed on the first main surface on which the first film is formed in a gas atmosphere containing moisture and hydrogen set to a ratio that oxidizes the melting point metal, and the first high A step of forming a gate insulating film on the silicon surface by converting the melting point metal into its oxide; and (c) oxidation in a gas atmosphere containing water and hydrogen before or after the step (b). Reduction equilibrium curve is more than that of silicon And a step of forming a second gate electrode of a refractory metal in a high moisture side.

The outline of the invention of the present application other than the above-described invention can be simply classified and described as follows. That is,
1. A method of manufacturing a semiconductor integrated circuit device comprising the following steps;
(A) A gate insulating film comprising a single insulating film having a silicon dioxide equivalent film thickness of less than 5 nm and comprising silicon oxide as a main component or a composite insulating film including the other insulating film and a wafer. (B) forming a refractory metal as a main component on the gate insulating film without passing through an intermediate layer containing polycrystalline silicon as a main component. Forming a metal gate electrode by patterning the metal film after forming the metal film to be processed, (c) the moisture / hydrogen partial pressure ratio does not substantially oxidize the refractory metal and oxidizes silicon By performing a heat treatment on the first main surface on which the metal gate electrode is formed in a gas atmosphere containing moisture and hydrogen set to a ratio, the gate insulation immediately below the metal gate electrode is processed. A step of repairing defects in the film.

  2. In the method for manufacturing a semiconductor integrated circuit device of the present invention, in the item 1, the refractory metal is molybdenum or tungsten.

  3. In the method for producing a semiconductor integrated circuit device according to the present invention, in the item 1 or 2, the gate insulating film has a silicon dioxide equivalent film thickness of less than 4 nm.

  4). In the method for producing a semiconductor integrated circuit device of the present invention, in the item 1 or 2, the silicon dioxide equivalent film thickness of the gate insulating film is less than 3 nm.

5. A method of manufacturing a semiconductor integrated circuit device comprising the following steps;
(A) a gate insulating film having a film thickness in terms of silicon dioxide equivalent to less than 5 nm and comprising a single insulating film containing silicon nitride as a main component or a composite insulating film including other insulating films and a wafer; (B) forming a refractory metal as a main component on the gate insulating film without passing through an intermediate layer containing polycrystalline silicon as a main component. Forming a metal gate electrode by patterning the metal film after forming the metal film to be processed, (c) the moisture / hydrogen partial pressure ratio does not substantially oxidize the refractory metal and oxidizes silicon By performing a heat treatment on the first main surface on which the metal gate electrode is formed in a gas atmosphere containing moisture and hydrogen set to a ratio, the gate insulation immediately below the metal gate electrode is processed. A step of repairing defects in the film.

  6). In the method for manufacturing a semiconductor integrated circuit device according to the present invention, in the item 5, the refractory metal is molybdenum or tungsten.

  7). In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the item 5 or 6, the gas containing moisture and hydrogen further contains nitrogen or ammonia gas.

8). A method of manufacturing a semiconductor integrated circuit device comprising the following steps;
(A) A single insulating film whose main component is a metal oxide having a silicon dioxide equivalent film thickness of less than 5 nm and having a dielectric constant larger than that of silicon dioxide, or a composite insulating film including this and another insulating film Forming a gate insulating film made of a film on a silicon surface on the first main surface of the wafer; (b) without interposing an intermediate layer having polycrystalline silicon as a main component on the gate insulating film; Forming a metal gate electrode by patterning the metal film after forming a metal film containing a refractory metal as a main component; and (c) a moisture / hydrogen partial pressure ratio substantially oxidizing the refractory metal. Without performing heat treatment on the first main surface on which the metal gate electrode is formed in a gas atmosphere containing moisture and hydrogen set to a ratio that oxidizes silicon. A step of repairing defects of the gate insulating film immediately below Rugate electrode.

  9. In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the item 8, the metal constituting the metal oxide film is titanium, zirconium, or hafnium.

  10. In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the item 8, the metal constituting the metal oxide film is tantalum.

  11. In the method for producing a semiconductor integrated circuit device according to the present invention, in the item 8, the metal constituting the metal oxide film is aluminum.

12 In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the item 8, the metal oxide film is a high dielectric material having an ABO ₃ type perovskite structure in a broad sense and is in a paraelectric phase at an operating temperature. It is.

  13. In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the item 12, the high dielectric is BST.

14 A method of manufacturing a semiconductor integrated circuit device comprising the following steps;
(A) A first film mainly containing a first refractory metal having a redox equilibrium curve in a gas atmosphere containing moisture and hydrogen on the lower moisture side than that of silicon is used as the first film of the wafer. (B) a moisture / hydrogen partial pressure ratio is set such that the silicon surface is not substantially oxidized and the first refractory metal is oxidized. In a gas atmosphere containing hydrogen and hydrogen, a heat treatment is performed on the first main surface on which the first film is formed, and the first refractory metal is converted into an oxide thereof, thereby A step of forming a gate insulating film on the silicon surface; (c) a step of forming a gate electrode before or after the step (b).

  15. In the method for manufacturing a semiconductor integrated circuit device according to the present invention, in the item 14, the first refractory metal is titanium, zirconium, or hafnium.

  16. In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the item 14 or 15, the gas atmosphere containing the moisture and hydrogen in the step (b) is formed by synthesizing moisture using a catalyst. .

17. A method of manufacturing a semiconductor integrated circuit device comprising the following steps;
(A) A gate insulating film mainly composed of an oxide of a first refractory metal whose oxidation-reduction equilibrium curve in a gas atmosphere containing moisture and hydrogen is on the moisture side lower than that of silicon is formed on the wafer. Forming on the silicon surface on the first main surface; (b) a ratio such that the moisture / hydrogen partial pressure ratio does not substantially oxidize the silicon surface and generates an oxide of the first refractory metal. In a gas atmosphere containing moisture and hydrogen set to 1, heat treatment is performed on the first main surface on which the first film is formed, and the first refractory metal is converted to its oxide. (C) a step of forming a gate electrode on the gate insulating film before or after the step (b).

  18. In the method of manufacturing a semiconductor integrated circuit device according to the item 17, in the item 17, the gate insulating film in the step (a) is formed on the silicon surface via a silicon oxide film.

  19. In the method for manufacturing a semiconductor integrated circuit device according to the present invention, in the item 17 or the item 18, the first refractory metal is titanium, zirconium, or hafnium.

  20. In the manufacturing method of a semiconductor integrated circuit device according to the present invention, the gas atmosphere containing the moisture and hydrogen in the step (b) is synthesized by synthesizing moisture using a catalyst. It is formed.

21. A method of manufacturing a semiconductor integrated circuit device comprising the following steps;
(A) By patterning a metal film containing a first refractory metal as a main component whose oxidation-reduction equilibrium curve in a gas atmosphere containing moisture and hydrogen is on a higher moisture side than that of silicon, Forming a gate electrode on the silicon surface on the first main surface; (b) performing a heat treatment on the first main surface in a state where the gate electrode is formed; Forming a gate insulating film having a silicon dioxide equivalent film thickness of less than 5 nm on a silicon surface and having silicon oxide as a main component;

  22. In the method for manufacturing a semiconductor integrated circuit device according to the present invention, in the item 21, the first refractory metal is molybdenum or tungsten.

23. A method of manufacturing a semiconductor integrated circuit device comprising the following steps;
(A) a first film to be a gate insulating film mainly composed of a first refractory metal whose oxidation-reduction equilibrium curve in an atmosphere containing moisture and hydrogen is on the moisture side lower than that of silicon; Forming on the silicon surface on the first main surface of the wafer; (b) in a state in which the first film is formed, the second redox equilibrium curve is on a higher moisture side than that of silicon. Forming a second film on the first main surface to be a gate electrode containing a refractory metal as a main component; and (c) patterning the first film and the second film. (D) performing a heat treatment on the first main surface in a state where the gate electrode is formed, and oxidizing the first film immediately below the gate electrode. The step of converting into a gate insulating film.

24. 24. In the method of manufacturing a semiconductor integrated circuit device according to the invention, in the item 23, the second refractory metal is molybdenum or tungsten. In the method for manufacturing a semiconductor integrated circuit device according to the present invention, in the item 23, the first refractory metal is titanium, zirconium, or hafnium.

26. A method of manufacturing a semiconductor integrated circuit device comprising the following steps;
(A) a semiconductor integrated circuit substrate having a silicon surface on a first main surface; (b) two containing two or more oxides of zirconium oxide, hafnium oxide or titanium oxide provided on the silicon surface; A gate insulating film containing a main or multi-element oxide as a main component; and (c) a gate electrode provided on the gate insulating film.

27. A method of manufacturing a semiconductor integrated circuit device comprising the following steps;
(A) A gate insulating film comprising a single insulating film having a silicon dioxide equivalent film thickness of less than 5 nm and comprising silicon oxide as a main component or a composite insulating film including the other insulating film and a wafer. (B) forming a conductive barrier film on the gate insulating film; and (c) forming polycrystalline silicon on the barrier film as a main component. A step of forming a metal film containing the first refractory metal as a main component without using an intermediate layer; and (d) a step of forming a gate electrode by patterning the barrier film and the metal film. (E) The gate electrode is formed in a gas atmosphere containing moisture and hydrogen whose moisture / hydrogen partial pressure ratio is set to such a ratio that does not substantially oxidize the refractory metal and oxidizes silicon. Before By performing the heat treatment on the first main surface, the step of repairing defects in the gate insulating film immediately below the gate electrode.

  28. In the method for manufacturing a semiconductor integrated circuit device according to the present invention, in the item 27, the first refractory metal is tungsten.

  29. In the method for manufacturing a semiconductor integrated circuit device according to the present invention, in the item 27, the conductive barrier film contains titanium nitride as a main component.

  30. In the method for manufacturing a semiconductor integrated circuit device according to the present invention, in the item 27, item 28 or item 29, the gas containing moisture and hydrogen further contains nitrogen or ammonia gas.

31. A method of manufacturing a semiconductor integrated circuit device comprising the following steps;
(A) forming a gate insulating film having a silicon dioxide equivalent film thickness of less than 5 nm on the main surface of the silicon substrate; (b) a metal having a refractory metal as a main component on the gate insulating film. After forming the film, the metal film has a moisture / hydrogen partial pressure ratio in a gas atmosphere containing moisture and hydrogen set to such a ratio that does not substantially oxidize the refractory metal and oxidizes silicon. A step of repairing defects in the gate insulating film directly under the metal film by heat-treating a main surface of the formed silicon substrate; and (c) a step of patterning the metal film to form a metal gate electrode.

  32. In the method for producing a semiconductor integrated circuit device according to the present invention, in the item 31, the gate insulating film contains silicon oxide as a main component.

  33. In the method for producing a semiconductor integrated circuit device according to the present invention, in the item 32, the gate insulating film thermally oxidizes the main surface of the silicon substrate in a gas atmosphere containing moisture and oxygen synthesized using a catalyst. By forming.

  34. In the method for producing a semiconductor integrated circuit device according to the present invention, in the item 31, the gate insulating film contains silicon oxynitride as a main component.

  35. In the method for producing a semiconductor integrated circuit device according to the present invention, in the item 34, the gate insulating film is formed by forming a silicon oxide film on the surface of the substrate and then heat-treating the substrate in a nitrogen-containing gas atmosphere. To do.

  36. In the method for producing a semiconductor integrated circuit device according to the present invention, in the item 31, the gate insulating film contains silicon nitride as a main component.

  37. In the method for manufacturing a semiconductor integrated circuit device according to the item 36, the gate insulating film is formed by depositing a silicon nitride film on the substrate by a CVD method.

  38. In the method for manufacturing a semiconductor integrated circuit device according to the present invention, in any one of the items 31 to 37, the refractory metal is molybdenum or tungsten.

39. A method of manufacturing a semiconductor integrated circuit device comprising the following steps;
(A) forming a gate insulating film having a silicon dioxide equivalent film thickness of less than 5 nm on the main surface of the silicon substrate; (b) conductivity comprising a refractory metal nitride on the gate insulating film. After forming a metal film containing a refractory metal as a main component through the barrier film, the moisture / hydrogen partial pressure ratio is set to a ratio that does not substantially oxidize the refractory metal and oxidizes silicon. Defects in the gate insulating film immediately below the conductive barrier film by heat-treating the main surface of the silicon substrate on which the metal film and the conductive barrier film are formed in a gas atmosphere containing moisture and hydrogen. (C) A step of patterning the metal film and the conductive barrier film to form a metal gate electrode.

  40. In the method for producing a semiconductor integrated circuit device according to the present invention, in the item 39, the refractory metal constituting the conductive barrier film is molybdenum or tungsten.

  41. In the method for producing a semiconductor integrated circuit device according to the present invention, in the item 39, the refractory metal constituting the conductive barrier film is titanium.

  42. In the method for producing a semiconductor integrated circuit device according to the present invention, the moisture concentration of the gas atmosphere containing the moisture and hydrogen is 1% or less in the item 41.

  43. In the method for producing a semiconductor integrated circuit device according to the present invention, in the item 41, nitrogen or ammonia is further added to the gas atmosphere containing the moisture and hydrogen.

44. A method of manufacturing a semiconductor integrated circuit device comprising the following steps;
(A) forming a gate insulating film made of a metal oxide having a silicon dioxide equivalent film thickness of less than 5 nm on the main surface of the silicon substrate and having a dielectric constant larger than that of silicon dioxide; (b) After forming a metal film containing refractory metal as a main component on the gate insulating film, the moisture / hydrogen partial pressure ratio is set to a ratio that does not substantially oxidize the refractory metal and oxidizes silicon. Repairing defects in the gate insulating film directly under the metal film by heat-treating a main surface of the silicon substrate on which the metal oxide is formed in a gas atmosphere containing water and hydrogen. c) A step of patterning the metal film to form a metal gate electrode before or after the step of repairing defects in the gate insulating film.

  45. In the method for producing a semiconductor integrated circuit device according to the present invention, in the item 44, the refractory metal is molybdenum or tungsten.

  46. In the method for producing a semiconductor integrated circuit device according to the present invention, in the item 44 or 45, the metal oxide is titanium oxide, zirconium oxide, hafnium oxide, tantalum oxide, aluminum oxide, or BST.

47. A method of manufacturing a semiconductor integrated circuit device comprising the following steps;
(A) forming a first refractory metal film on the main surface of the silicon substrate; (b) after forming a metal film containing a second refractory metal as a main component on the first refractory metal film. The heat treatment is performed in a gas atmosphere containing moisture and hydrogen set to such a ratio that the moisture / hydrogen partial pressure ratio does not substantially oxidize the second refractory metal and oxidizes the first refractory metal. Forming a gate insulating film having a thickness less than 5 nm on the surface of the silicon substrate by converting the first refractory metal into its oxide; and (c) the heat treatment step. A step of patterning the metal film before or after forming a metal gate electrode.

  48. In the method for producing a semiconductor integrated circuit device according to the present invention, in the item 47, the refractory metal is molybdenum or tungsten.

  49. In the method for producing a semiconductor integrated circuit device according to the present invention, in the item 47 or 48, the first refractory metal is titanium, zirconium, hafnium or tantalum.

50. A method of manufacturing a semiconductor integrated circuit device comprising the following steps;
(A) A gas containing water and hydrogen whose moisture / hydrogen partial pressure ratio is set to a ratio that does not substantially oxidize the refractory metal film after the refractory metal film is formed on the main surface of the silicon substrate. Performing a heat treatment in an atmosphere to form a gate insulating film made of silicon oxide having a film thickness in terms of silicon dioxide of less than 5 nm at the interface between the substrate and the refractory metal film; and (b) the heat treatment process. Forming a metal gate electrode by patterning the refractory metal film before or after the step.

  51. In the method for producing a semiconductor integrated circuit device according to the present invention, in the item 50, the refractory metal is molybdenum or tungsten.

  52. 52. In the method for manufacturing a semiconductor integrated circuit device according to the present invention, in any one of 31 to 51, the gate insulating film has a silicon dioxide equivalent film thickness of less than 4 nm.

  53. In the method for manufacturing a semiconductor integrated circuit device according to the present invention, in any one of the items 31 to 52, the gate insulating film has a silicon dioxide equivalent film thickness of less than 3 nm.

  54. In the method for producing a semiconductor integrated circuit device according to the present invention, the gate insulating film has a silicon dioxide equivalent film thickness of 1.5 nm to 2 nm.

  55. In the method for manufacturing a semiconductor integrated circuit device according to the present invention, in any one of the items 31 to 54, the gate length of the metal gate electrode is 0.25 μm or less.

  56. In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the gate length of the metal gate electrode is 0.18 μm or less in any one of the items 31 to 55.

  57. In the method for producing a semiconductor integrated circuit device according to the present invention, the gate length of the metal gate electrode is 0.1 μm or less in any one of the items 31 to 56.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to one invention of the present application, the reliability and manufacturing yield of a MISFET in which a metal gate electrode is formed on an ultrathin gate insulating film can be improved.

  According to one invention of the present application, it is possible to improve the reliability and manufacturing yield of a MISFET in which a metal gate electrode is formed on a gate insulating film containing a metal oxide having a dielectric constant higher than that of silicon oxide.

  According to one invention of the present application, since a high-quality gate insulating film having a silicon dioxide equivalent film thickness of less than 5 nm can be formed with a high yield, high integration of CMOS-LSI can be promoted.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiments, when necessary for convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), except when explicitly stated and in principle limited to a specific number in principle. It is not limited to the specific number, and may be a specific number or more. Furthermore, in the following embodiments, it is needless to say that the constituent elements (including element steps and the like) are not necessarily essential unless explicitly stated and clearly considered essential in principle. Yes.

  Similarly, in the following embodiments, when referring to the shapes and positional relationships of components and the like, the shapes and the like of the components are substantially the same unless explicitly stated or otherwise apparent in principle. Including those that are approximate or similar to. The same applies to the above numerical values and ranges.

  In addition, the term “semiconductor integrated circuit device” (or an electronic device, an electronic circuit device, etc.) in this application is not limited to a device manufactured on a silicon wafer, but unless otherwise specified, an SOI (Silicon On Insulator). Also included are those made on other substrates such as substrates and TFT liquid crystals.

(Embodiment 1)
The present embodiment is applied to the manufacture of a CMOS-logic LSI in which an n-channel MISFET and a p-channel MISFET constitute an integrated circuit.

  First, as shown in FIG. 1, a single crystal silicon substrate 1 (hereinafter referred to as substrate or wafer) 1 having a specific resistance of about 10 Ωcm is heat-treated at about 850 ° C., and a thin silicon oxide film 2 having a thickness of about 10 nm is formed on the main surface. Then, a silicon nitride film 3 having a thickness of about 120 nm is deposited on the silicon oxide film 2 by a CVD (Chemical Vapor Deposition) method, and then the element is formed by dry etching using a photoresist film (not shown) as a mask. The silicon nitride film 3 in the isolation region is removed.

  The silicon oxide film 2 relieves stress applied to the substrate 1 when heat-treating the silicon oxide film embedded in the element isolation trench in a later step, or relieves damage on the surface of the substrate 1 due to ion implantation. Form with purpose. The silicon nitride film 3 is used as a protective film for preventing oxidation of the surface of the substrate 1 below (active region) and a stopper when polishing the surface of the silicon oxide film embedded in the element isolation trench.

  Next, as shown in FIG. 2, an element isolation groove 4 having a depth of about 350 nm is formed on the substrate 1 in the element isolation region by dry etching using the silicon nitride film 3 as a mask, and then the element isolation groove 4 is formed by the above etching. In order to remove the damage layer generated on the inner wall of the substrate, the substrate 1 is heat-treated at about 1000 ° C. to form a thin silicon oxide film 5 having a thickness of about 10 nm on the inner wall of the element isolation trench 4.

  Next, as shown in FIG. 3, after the silicon oxide film 6 is embedded in the element isolation trench 4, the surface thereof is flattened. In order to embed and planarize the silicon oxide film 6, first, a silicon oxide film 6 having a thickness of about 600 nm is deposited on the substrate 1 by a CVD method, and then the substrate 1 is made to improve the film quality of the silicon oxide film 6. Heat treatment is performed at about 1000 ° C. Next, the silicon oxide film 6 is polished by a chemical mechanical polishing (CMP) method using the silicon nitride film 3 as a stopper, leaving the silicon oxide film 6 only in the element isolation trench 4.

  Next, after removing the silicon nitride film 3 remaining on the active region of the substrate 1 by wet etching using hot phosphoric acid, B (boron) is ion-implanted into a part of the substrate 1 as shown in FIG. Then, the p-type well 7 is formed, and P (phosphorus) is ion-implanted into the other part to form the n-type well 8.

  Next, an impurity (B or P) for adjusting the threshold voltage (Vth) of the MISFET is ion-implanted in the vicinity of the surface of each of the p-type well 7 and the n-type well 8, and as shown in FIG. Then, the silicon oxide film 2 on the surface of each of the p-type well 7 and the n-type well 8 is removed with an HF (hydrofluoric acid) -based cleaning solution to thereby remove the active region substrate 1 (p-type well 7 and n-type well 8). To expose the surface.

  Next, a gate insulating film is formed on the surface of each of the p-type well 7 and the n-type well 8 by the following method.

  In general, in order to realize high-speed and high-performance MIS devices, it is necessary to reduce the gate insulating film as the MISFET is miniaturized. For example, a logic device having a gate length of about 0.25 μm to 0.2 μm In the case of the MISFET for use, a gate insulating film having a thickness of less than 5 nm is required. Depending on the type of MIS device, a gate insulating film with a gate length of less than 4 nm when the gate length is about 0.18 μm to 0.14 μm, and a gate insulating film with a thickness of less than 3 nm when the gate length is about 0.13 μm to 0.1 μm. Required.

  As is well known, as a method of oxidizing the surface of a single crystal silicon substrate at a high temperature to form a gate insulating film (gate oxide film), hydrogen is burned in an oxygen atmosphere to generate moisture, and this moisture is combined with oxygen. There is a wet oxidation (pyrogenic oxidation) method in which an oxide film is formed by supplying to the substrate surface. However, in the oxide film forming method using this combustion method, it is difficult to form a high-quality ultrathin gate insulating film having a film thickness of less than 5 nm with good reproducibility.

  That is, the above oxide film forming method using the combustion method can be controlled only within a high concentration range in which the water concentration of the water + oxygen mixed gas as the oxidizing species is about 18 to 40%. Therefore, when heat treatment is performed in a water + oxygen mixed gas atmosphere having such a moisture concentration, a large amount of OH groups and hydrogen due to moisture are taken into the oxide film, and Si—H bonds and Structural defects such as Si—OH bonds are likely to occur. This structural defect is cut by application of voltage stress such as hot carrier injection to form a charge trap, which causes deterioration of electrical characteristics such as variation in threshold voltage and reduction in dielectric strength.

  In addition, in order to form a thin thermal oxide film with a uniform film thickness and good reproducibility, the film growth rate is reduced compared to when a relatively thick oxide film is formed, and the film is formed under more stable oxidation conditions. There is a need. However, in the case of the above combustion method, since the moisture concentration is high, the growth rate of the film is high, and the film is formed in an extremely short time. Therefore, it is possible to stably form an ultrathin oxide film having a film thickness of less than 5 nm. I can't.

  Furthermore, in order to form a clean gate insulating film, it is necessary to remove in advance a low-quality oxide film formed on the surface of the silicon substrate by wet cleaning. After this wet cleaning, the substrate (wafer) A thin native oxide is inevitably formed on the surface of the substrate until it is oxidized. Further, in the oxidation step, an undesired initial oxide film is formed on the surface of the substrate by contact with oxygen in the oxidizing species before the original oxidation is performed. In particular, in the case of the above-described combustion method, in order to avoid the danger of hydrogen explosion, the hydrogen is burned after sufficiently flowing oxygen in advance, so that the time during which the surface of the substrate is exposed to oxygen becomes longer and the initial oxidation is performed. A film is formed thick.

  As described above, the actual gate oxide film includes the natural oxide film and the initial oxide film in addition to the oxide film formed by the original thermal oxidation. The film is of lower quality than the intended original oxide film. Therefore, in order to obtain a high-quality gate insulating film, the proportion of these low-quality oxide films in the oxide film must be as low as possible. However, when a thin oxide film is formed by the combustion method, The proportion of low-quality insulating films will rather increase.

  For example, when an oxide film having a film thickness of 9 nm is formed by a combustion method, if the film thickness of the natural oxide film and the initial oxide film in the oxide film are 0.7 nm and 0.8 nm, respectively, the original oxide film Therefore, the ratio of the original oxide film in the oxide film is about 83.3%. However, when an oxide film having a film thickness of 4 nm is formed by using this combustion method, the film thicknesses of the natural oxide film and the initial oxide film are not different from 0.7 nm and 0.8 nm, respectively. The thickness is 4- (0.7 + 0.8) = 2.5 nm, and the ratio decreases to 62.5%. That is, when an ultra-thin silicon oxide film is formed by the conventional combustion method (pyrogenic oxidation method), not only the uniformity and reproducibility of the film thickness cannot be secured, but also the film quality is lowered.

  Therefore, in this embodiment, a high-quality ultra-thin gate insulating film is formed by the method described below. However, the formation of the gate insulating film is not limited to this method, and the gate insulating film can also be formed using a water + hydrogen mixed gas described later.

  FIG. 6 is a schematic view showing a single-wafer type film forming apparatus 100 used for forming a gate insulating film. As shown in the figure, the film forming apparatus 100 includes a cleaning apparatus 101 that removes the oxide film on the surface of the substrate (wafer) 1 by a wet cleaning method prior to the formation of the gate insulating film. By adopting such a cleaning-oxidation integrated processing system, the wafer 1 subjected to the cleaning process in the cleaning apparatus 101 can be transferred to the film forming apparatus 100 in a short time without being brought into contact with the atmosphere. The formation of an undesired natural oxide film on the surface of the wafer 1 between the removal of the silicon oxide film 2 and the formation of the gate insulating film can be suppressed as much as possible.

The wafer 1 loaded on the loader 102 of the cleaning apparatus 101 is first transported to the cleaning chamber 103 and subjected to a cleaning process with a cleaning liquid such as NH ₄ OH + H ₂ O ₂ + H ₂ O, and then into the hydrofluoric acid cleaning chamber 104. The silicon oxide film 2 on the surface is removed by being transported and subjected to a cleaning treatment with dilute hydrofluoric acid (HF + H ₂ O). Thereafter, the wafer 1 is transported to the drying chamber 105 and subjected to a drying process to remove moisture on the surface. Moisture remaining on the surface of the wafer 1 causes structural defects such as Si—H and Si—OH in the gate insulating film and at the gate insulating film / silicon substrate interface, thereby forming charge traps, and is sufficiently removed. It is necessary to keep it.

  The wafer 1 after the drying process is immediately transferred to the buffer 106 of the film forming apparatus 100. The film forming apparatus 100 is configured by a multi-chamber system including an oxide film forming chamber 107, an oxynitride film forming chamber 108, a heat treatment chamber 109, a loader / unloader 110, a metal film forming chamber 111, and the like. The transfer system 112 includes a robot hand 113 for loading (unloading) the wafer 1 into / from each processing chamber. The inside of the transfer system 112 is maintained in an inert gas atmosphere such as nitrogen in order to suppress as much as possible the formation of a natural oxide film on the surface of the wafer 1 due to air contamination. Further, the inside of the transfer system 112 is kept in an ultra-low moisture atmosphere of ppb level in order to suppress the adhesion of moisture to the surface of the wafer 1 as much as possible. The wafers 1 loaded into the film forming apparatus 100 are first transferred to the oxide film forming chamber 107 via the robot hand 113 in units of one or two.

  FIG. 7A is a schematic plan view showing an example of a specific configuration of the oxide film forming chamber 107, and FIG. 7B is a cross-sectional view taken along the line BB ′ of FIG. 7A. .

  The oxide film forming chamber 107 includes a chamber 120 formed of a multi-walled quartz tube, and lamps 130 for heating the wafer 1 are installed at the upper and lower portions thereof. Inside the chamber 120, a disc-shaped heat equalizing ring 122 for evenly distributing the heat supplied from the lamp 130 over the entire surface of the wafer 1 is installed, and a susceptor 123 for holding the wafer 1 horizontally is placed on the top. Is placed. The soaking ring 122 is made of a heat-resistant material such as quartz or SiC (silicon carbide), and is supported by a support arm 124 extending from the wall surface of the chamber 120. A thermocouple 125 that measures the temperature of the wafer 1 held by the susceptor 123 is installed near the soaking ring 122.

  One end of a gas introduction pipe 126 for introducing water, oxygen and purge gas into the chamber 120 is connected to a part of the wall surface of the chamber 120. The other end of the gas introduction pipe 126 is connected to a catalyst-type moisture generation device described later. A partition wall 128 having a large number of through holes 127 is provided in the vicinity of the gas introduction pipe 126, and the gas introduced into the chamber 120 passes through the through holes 127 of the partition wall 128 and enters the chamber 120. Spread evenly. One end of an exhaust pipe 129 for discharging the gas introduced into the chamber 120 is connected to the other part of the wall surface of the chamber 120.

  FIG. 8 is a schematic view showing a catalytic moisture + oxygen mixed gas generator 140 connected to the chamber 120 of the oxide film forming chamber 107. The gas generator 140 includes a reactor 141 made of a heat-resistant and corrosion-resistant alloy (for example, Ni alloy known as a trade name “Hastelloy”), and contains Pt (platinum), Ni ( A coil 142 made of a catalytic metal such as nickel) or Pd (palladium) and a heater 143 for heating the coil (or curved counter plate) 142 are installed.

  A process gas composed of hydrogen and oxygen and a purge gas composed of an inert gas such as nitrogen or Ar (argon) are introduced into the reactor 141 from a gas storage tank 144a, 144b, 144c through a pipe 145. In the middle of the pipe 145, mass flow controllers 146 a, 146 b, 146 c for adjusting the amount of gas and open / close valves 147 a, 147 b, 147 c for opening and closing the gas flow path are installed, and the gas introduced into the reactor 141 The amount and component ratio of these are precisely controlled by these.

The process gas (hydrogen and oxygen) introduced into the reactor 141 is excited by contact with a coil (or curved counter plate) 142 heated to about 350 to 450 ° C., and hydrogen radicals are generated from hydrogen molecules. (H ₂ → 2H *), oxygen radicals are generated from oxygen molecules (O ₂ → 2O *). Since these two types of radicals are chemically very active, they react quickly to produce moisture (2H * + O * → H ₂ O). This moisture is mixed with oxygen in the connection portion 148 and diluted to a low concentration, and is introduced into the chamber 120 of the oxide film forming chamber 107 through the gas introduction pipe 126.

  The catalyst-type water + oxygen mixed gas generation apparatus 140 as described above can control the amount of hydrogen and oxygen involved in the generation of water with high accuracy, and is therefore introduced into the chamber 120 of the oxide film formation chamber 107 together with oxygen. The water concentration can be controlled over a wide range and with high accuracy from a very low concentration of ppt or less to a high concentration of about several tens of percent. In addition, when process gas is introduced into the reactor 141, moisture is instantly generated, so that a desired moisture concentration can be obtained in real time. Therefore, hydrogen and oxygen can be introduced into the reactor 141 at the same time, and it is not necessary to introduce oxygen prior to the introduction of hydrogen as in a conventional moisture generation system employing a combustion method. The catalyst metal in the reactor 141 may be made of a material other than the metal described above as long as it can radicalize hydrogen or oxygen. Further, the catalyst metal may be processed into a coil shape and used, for example, may be processed into a hollow tube or a fine fiber filter and the process gas may be passed through the inside.

  In order to form a gate insulating film using the film forming apparatus 100, first, the chamber 120 of the oxide film forming chamber 107 is opened, and the wafer 1 is placed on the susceptor 123 while introducing a purge gas (nitrogen or Ar) into the chamber 120. To load. Thereafter, the chamber 120 is closed, and subsequently purge gas is introduced to sufficiently exchange the gas in the chamber 120. The susceptor 123 is previously heated by the lamp 130 so that the wafer 1 is heated quickly. The heating temperature of the wafer 1 is in the range of 800 to 900 ° C., preferably about 850 ° C. When the temperature of the wafer 1 is 800 ° C. or lower, the quality of the gate insulating film is deteriorated, and when the temperature is 900 ° C. or higher, the surface of the wafer 1 is easily roughened.

  Next, oxygen and hydrogen are introduced into the reactor 141 of the moisture + oxygen mixed gas generating apparatus 140, and the generated moisture is introduced into the chamber 120 together with oxygen to oxidize the surface of the wafer 1 for several minutes, thereby allowing the wafer 1 to be oxidized. A gate insulating film 9A made of silicon oxide is formed on the surface (FIG. 9).

  When oxygen and hydrogen are introduced into the reactor 141 of the film forming apparatus 100, hydrogen is not introduced before oxygen. If hydrogen is introduced before oxygen, it is dangerous because unreacted hydrogen flows into the hot chamber 120. On the other hand, when oxygen is introduced prior to hydrogen, this oxygen flows into the chamber 120 and forms a low-quality oxide film (initial oxide film) on the surface of the waiting wafer 1. Therefore, hydrogen is introduced at the same time as oxygen, or is introduced at a slightly later timing (within 5 seconds) than oxygen in consideration of work safety. In this way, the thickness of the initial oxide film that is undesirably formed on the surface of the wafer 1 can be minimized.

  FIG. 10 is a graph showing the dependency of the moisture concentration on the oxide film growth rate, where the horizontal axis indicates the oxidation time and the vertical axis indicates the oxide film thickness. As shown in the figure, the growth rate of the oxide film is the slowest when the water concentration is 0 (dry oxidation), and increases as the water concentration increases. Therefore, in order to form the ultrathin gate insulating film 9A having a film thickness of less than 5 nm with good reproducibility and a uniform film thickness, the moisture concentration is lowered to slow the oxide film growth rate, and the film is formed under stable oxidation conditions. It is effective to perform a membrane.

  A preferable concentration of moisture introduced into the chamber 120 of the oxide film forming chamber 107 is a concentration at which an initial withstand voltage superior to that obtained by dry oxidation (moisture concentration = 0) is obtained, and a conventional combustion method is adopted. The upper limit is about 40%. In particular, in order to form the ultrathin gate insulating film 9A having a film thickness of less than 5 nm with a uniform film thickness and high reproducibility, and with high quality, the moisture concentration is set in the range of 0.5% to 5%. Is preferred.

Here, the “moisture concentration” of the moisture + oxygen mixed gas is a value indicating the percentage of moisture contained in the moisture + oxygen mixed gas introduced into the chamber 120 as a percentage. Therefore, for example, as shown in FIG. 11, when the flow rate of oxygen introduced into the chamber 120 is F 2 _O and the flow rate of moisture is _FW , the moisture concentration C of the moisture + oxygen mixed gas is C = {F _W / (F _W + F _O )} × 100 (%). Note that the water + oxygen mixed gas introduced into the chamber 120 may be at a reduced pressure or a high pressure in addition to a normal pressure. Further, it may contain a purge gas such as nitrogen or Ar.

On the other hand, the “moisture concentration” of the water + hydrogen mixed gas described later is defined as a value indicating the partial pressure ratio of water to hydrogen contained in the water + hydrogen mixed gas as a percentage. That is, when the partial pressure of hydrogen contained in moisture and hydrogen mixed gas was _{P H,} the partial pressure of water and _{P W,} the water concentration of the water and hydrogen gas _{mixture, (P W / P H)} × 100 ( %). Therefore, for example, when the partial pressure of hydrogen is 99 and the partial pressure of water is 1, the water concentration of the water + hydrogen mixed gas is [(1/99) × 100] ≈1.01%.

  In this embodiment, the p-type well 7 and the n-type well are oxidized by oxidizing the main surface of the wafer 1 by setting the heating temperature of the wafer 1 to 850 ° C. and the moisture concentration of the moisture + oxygen mixed gas to 0.8%. A gate insulating film 9 A is formed on each surface of 8. The film thickness of the gate insulating film 9A is less than 5 nm when the gate length of the gate electrode formed thereon in the next step is 0.25 μm to 0.2 μm, and less than 4 nm when 0.18 μm to 0.14 μm. In the case of 0.13 μm to 0.1 μm, the thickness is less than 3 nm. The film thickness of the gate insulating film 9A here is a silicon dioxide equivalent film thickness and may not match the actual film thickness.

Thereafter, the gate insulating film 9A made of silicon oxide may be converted into a silicon oxynitride film by the following method. That is, the wafer 1 on which the gate insulating film 9A is formed is transferred to the oxynitride film forming chamber 108 of the film forming apparatus 100 shown in FIG. 6, and is made of NO (nitrogen oxide) or N ₂ O (nitrous oxide). By performing heat treatment in a nitrogen-containing gas atmosphere, nitrogen is segregated in the silicon oxide film.

  The above oxynitridation process is not an essential process, but when the thickness of the gate insulating film 9A is less than 5 nm, stress generated at the interface between the two due to the difference in thermal expansion coefficient with the silicon substrate becomes obvious, and It will trigger the outbreak. Since the silicon oxynitride film relieves this stress, the reliability and withstand voltage of the ultrathin gate insulating film 9A are further improved by performing the above oxynitriding treatment. The gate insulating film 9A made of a silicon oxynitride film can also be formed by heat-treating the wafer 1 in a water + oxygen mixed gas to which nitrogen or ammonia is added.

  Next, the wafer 1 on which the gate insulating film 9A is formed is transferred to the metal film forming chamber 111 of the film forming apparatus 100, and as shown in FIG. 12, W (tungsten) to be a gate electrode is formed on the gate insulating film 9A. ) Deposit film 11A. The W film 11A is deposited by sputtering or CVD, and the film thickness is about 50 nm. Also, a Mo film can be used as a gate electrode material to replace the W film 11A. Mo has the advantage of lower electrical resistance than W.

In the film of the gate insulating film 9A made of silicon oxide (or silicon oxynitride), defects mainly due to Si—O bond defects occur during the film formation. When the W film 11A is directly deposited on the gate insulating film 9A without an intermediate layer such as a polycrystalline silicon film, the stress generated in the film of the W film 11A during the film formation is directly under the gate. Since it is added to the insulating film 9A, a defect occurs in the gate insulating film 9A near the interface between the two. Further, when the W film 11A is deposited on the gate insulating film 9A by sputtering, the surface of the gate insulating film 9A is sputtered to cause damage, or W ions penetrate into the substrate 1 and enter the gate insulating film 9A. Or reduce the film thickness. On the other hand, when the W film 11A is deposited by the CVD method, the surface of the gate insulating film 9A is etched by fluorine in the reaction gas (WF ₆ ), and the actual film thickness becomes thinner than the desired film thickness. Therefore, even when the W film 11A is formed by any method, it is inevitable that a defect occurs in the gate insulating film 9A immediately below the W film 11A. In particular, the ultra-thin gate insulating film 9A having a film thickness of less than 5 nm deteriorates withstand voltage and TDDB (Time-dependent dielectric breakdown) resistance even if the above-described defects are present in the film. , Film quality and reliability are reduced.

  Therefore, next, the wafer 1 is heat-treated in an oxidizing atmosphere to repair the defects generated in the gate insulating film 9A. That is, oxygen is supplied to the gate insulating film 9A immediately below it through the W film 11A, and oxygen is introduced into Si-O bond deficient portions present in the silicon oxide film constituting the gate insulating film 9A to repair the deficient portions. .

  However, when the defect repair of the gate insulating film 9A is performed in a normal oxidizing atmosphere, for example, a dry oxygen atmosphere, the W film 11A covering the gate insulating film 9A is also oxidized at the same time, so that the resistance of the gate electrode increases. End up. Therefore, the defect repair of the gate insulating film 9A must be performed by a method capable of selectively oxidizing only Si without substantially oxidizing W which is the gate electrode material.

FIG. 13 is a graph showing the temperature dependence of the equilibrium vapor pressure ratio (P _H2O / P _H2 ) of the oxidation-reduction reaction using a water + hydrogen mixed gas, and the curves (a) to (e) in the figure are respectively The equilibrium vapor pressure ratios of W, Mo (molybdenum), Ta (tantalum), Si, and Ti (titanium) are shown.

  As shown in the figure, by setting the water / hydrogen partial pressure ratio within a range between the curves (a) and (d), only Si is selectively oxidized without oxidizing W. be able to. That is, by performing a heat treatment on the wafer 1 in a moisture + hydrogen mixed gas atmosphere in a region where the moisture / hydrogen partial pressure ratio is sandwiched between the curves (a) and (d), the gate is formed without oxidizing the W film 11A. The defect can be repaired by oxidizing the insulating film 9A.

  Similarly, by setting the moisture / hydrogen partial pressure ratio within the range between the curves (b) and (d) in the figure, only Si is selectively oxidized without oxidizing Mo. be able to. That is, when the gate electrode material is Mo, the wafer 1 is heat-treated in a moisture + hydrogen mixed gas atmosphere in which the moisture / hydrogen partial pressure ratio is set within this range, so that the gate is not oxidized and the Mo film is not oxidized. Defect repair of the insulating film 9A can be performed.

  The defect repair of the gate insulating film 9A is performed by transferring the wafer 1 on which the W film 11A is formed from the metal film forming chamber 111 of the film forming apparatus 100 to the heat treatment chamber 109. Since the chamber of the heat treatment chamber 109 has the same structure as the chamber 101 of the oxide film formation chamber 107 used for forming the gate insulating film 9A, its illustration is omitted.

  FIG. 14 is a schematic view showing a catalyst-type water + hydrogen mixed gas generation device 240 and a hydrogen gas abatement device 250 connected to the heat treatment device 109.

  The moisture + hydrogen mixed gas generating device 240 has a structure similar to the moisture + oxygen mixed gas generating device 140 used for forming the gate insulating film 9A. That is, the moisture + hydrogen mixed gas generating apparatus 240 includes a reactor 241a made of a heat-resistant and corrosion-resistant alloy, and a coil 242 made of a catalytic metal and a heater 243 for heating the coil 242 are installed therein. Yes.

  A process gas composed of hydrogen and oxygen and a purge gas composed of an inert gas such as nitrogen or Ar are introduced into the reactor 241a from a gas storage tank 244a, 244b, 244c through a pipe 245, respectively. Between the gas storage tanks 244a, 244b, 244c and the pipe 245, mass flow controllers 246a, 246b, 246c for adjusting the gas amount, and opening / closing valves 247a, 247b, 247c for opening and closing the gas flow path are installed, The amount and component ratio of the gas introduced into the reactor 241a are precisely controlled thereby.

The process gas (hydrogen and oxygen) introduced into the reactor 241a is excited in contact with the coil 242 heated to about 350 to 450 ° C., and hydrogen radicals are generated from hydrogen molecules (H ₂ → 2H *). ), Oxygen radicals are generated from oxygen molecules (O ₂ → 2O *). Since these two types of radicals are chemically very active, they react quickly to produce moisture (2H * + O * → H ₂ O). Therefore, a water + hydrogen mixed gas is generated by introducing a hydrogen / oxygen mixed gas containing hydrogen in excess of the molar ratio (hydrogen: oxygen = 2: 1) in which moisture is generated into the reactor 241a. Can do. The generated water + hydrogen mixed gas is introduced into the heat treatment chamber 209 through the gas introduction pipe 208.

  Since the catalyst-type gas generator 240 as described above can control the amount of hydrogen and oxygen involved in the generation of moisture and the ratio thereof with high accuracy in the same manner as the moisture + oxygen mixed gas generator 140 described above, heat treatment is performed. The water concentration in the water + hydrogen mixed gas introduced into the chamber 209 can be controlled over a wide range and with high accuracy from a very low concentration of the ppb order to a high concentration of several tens of percent. In addition, when process gas is introduced into the reactor 241a, moisture is instantaneously generated, so that a moisture + hydrogen mixed gas having a desired moisture concentration can be obtained in real time. Thereby, since mixing of foreign substances can be minimized, a clean moisture + hydrogen mixed gas can be introduced into the heat treatment chamber 209.

  In order to repair the defect of the gate insulating film 9A, first, the wafer 1 is loaded while introducing the purge gas (nitrogen or Ar) into the chamber of the heat treatment chamber 209, then the chamber is closed, and the purge gas is subsequently introduced into the chamber. After sufficient gas exchange is performed, a water + hydrogen mixed gas is introduced into the chamber. The heating temperature of the wafer 1 at this time is preferably in the range of 700 ° C. to 800 ° C., more preferably about 750 ° C. Further, the water concentration of the water + hydrogen mixed gas is preferably in the range of 0.5% to 30%, more preferably in the range of 1% to 20%.

  By performing the heat treatment under the above conditions, the oxidized species (OH group) derived from the moisture in the moisture + hydrogen mixed gas enters the gate insulating film 9A through the W film 11A, and becomes an oxygen-deficient defect portion of the Si—O bond. Supply oxygen to repair defects. Further, even if the heat treatment is performed under these conditions, the W film 11A is not oxidized, so that the resistance of the gate electrode does not increase.

  Since stress is accumulated in the W film 11A when it is formed, when the gate electrode is formed by patterning the W film 11A, the residual stress in the film is concentrated on the side wall end of the gate electrode, and this region. This reduces the hot carrier resistance of the gate insulating film 9A. When the heat treatment for repairing defects in the gate insulating film 9A is performed, the stress accumulated in the W film 11A is relieved, so that the resistance of the gate insulating film 9A to hot carriers at the end of the side wall after the gate electrode is formed. The malfunction which falls can be suppressed simultaneously.

  After the above-described defect repair work for the gate insulating film 9A is completed, the water + hydrogen mixed gas in the heat treatment chamber 209 is discharged through the exhaust pipe 211 shown in FIG. 14 and cooled to 500 ° C. or lower by the cooler 256. After that, it is introduced into the reactor 241b of the hydrogen gas abatement apparatus 250. At this time, oxygen gas is supplied into the exhaust pipe 211 from the gas storage tank 244a through the pipe 251 and is introduced into the reactor 241b together with the water + hydrogen mixed gas. Between the gas storage tank 244a and the pipe 251, a mass flow controller 246d for adjusting the amount of oxygen gas and an open / close valve 247d for opening and closing the flow path of the oxygen gas are installed, and the oxygen gas introduced into the reactor 242b The amount is precisely controlled by these. A check valve 252 that prevents the oxygen gas from flowing back into the heat treatment chamber 209 is provided in the middle of the exhaust pipe 211.

  The reactor 241b of the hydrogen gas abatement apparatus 250 is made of a heat-resistant and corrosion-resistant alloy, like the reactor 241a of the gas generating apparatus 240, and has a coil 242 made of catalytic metal and a heater 243 for heating the coil 242 inside. And are installed. The water + hydrogen mixed gas and oxygen gas introduced into the reactor 241b are excited by being brought into contact with the coil 242 heated to about 350 to 450 ° C. and generated from hydrogen radicals and oxygen molecules generated from hydrogen molecules. Oxygen radicals react quickly to produce moisture.

  Therefore, when the moisture + hydrogen mixed gas discharged from the heat treatment chamber 209 is introduced into the reactor 241b, oxygen at least 1/2 (molar ratio) of the amount of hydrogen in the mixed gas is simultaneously introduced, The gas is completely oxidized and converted to water. This oxygen gas may be introduced into the reactor 241b prior to the introduction of the water + hydrogen mixed gas, or may continue to flow into the reactor 241b through the pipe 251 and the exhaust pipe 211 at all times. Moisture generated in the reactor 241b is discharged to the outside through the exhaust pipe 253 together with excess oxygen gas. In the middle of the exhaust pipe 253, there are a hydrogen gas sensor 254 for confirming whether or not the hydrogen gas has been completely converted into water, and a cooler 255 for liquefying the discharged high-temperature water (water vapor). Is provided.

  Next, as shown in FIG. 15, a silicon nitride film 13 having a film thickness of about 50 nm to 100 nm is deposited on the top of the W film 11A by the CVD method, and the silicon nitride film 13 is formed by dry etching using the photoresist film 14 as a mask. The gate electrode 11 is formed by patterning the W film 11A. The gate length of the gate electrode 11 is in the range of 0.25 μm to 0.1 μm. Since the sheet resistance of the gate electrode 11 composed of W is 2Ω / □ or less, the operation speed of the MISFET can be improved. In addition, after depositing the silicon nitride film 13 on the upper part of the W film 11A, prior to the step of patterning the W film 11A to form the gate electrode 11, the heat treatment using the moisture + hydrogen mixed gas is performed once again. The stress in the W film 11A caused by the deposition of the silicon nitride film 13 may be reduced.

  Next, after the photoresist film 14 used for processing the gate electrode 11 is removed by ashing (ashing), dry etching residues and ashing residues remaining on the surface of the substrate 1 are removed with an etching solution such as hydrofluoric acid. . As shown in FIG. 16, when this wet etching is performed, the gate insulating film 9A in the region excluding the lower portion of the gate electrode 11 is shaved, and at the same time, the gate insulating film 9A under the side wall of the gate electrode 11 is isotropic. Since the etching causes an undercut, the breakdown voltage of the gate insulating film 9A is lowered. Therefore, next, heat treatment (reoxidation treatment) is performed to regenerate the gate insulating film 9A shaved by the wet etching. In addition, as a technique related to this reoxidation treatment, there are Japanese Patent Application No. 10-138939, Japanese Patent Application Laid-Open No. 10-335562, and US Patent Application No. 09/088668 corresponding thereto.

  Since the re-oxidation process has to oxidize Si (substrate 1) without oxidizing the W film (11A) constituting the gate electrode 11, as in the above-described defect repair process of the gate insulating film 9A, Substrate) 1 is carried into the heat treatment apparatus 209, and heat treatment is performed in a moisture + hydrogen mixed gas atmosphere generated by a catalyst-type water + hydrogen mixed gas generation apparatus 240. The moisture concentration of the moisture + hydrogen mixed gas may be the same as that of the moisture + hydrogen mixed gas used for defect repair of the gate insulating film 9A. The heat treatment temperature is the same as or slightly lower than the temperature at the time of defect repair of the gate insulating film 9A.

  By performing this heat treatment, the surface of the substrate (Si) 1 is oxidized, and the thickness of the gate oxide film 9 which has been thinned by the wet etching process is restored to the state before etching. Further, the profile of the side wall end portion of the gate electrode 11 is improved (FIG. 17).

  If the re-oxidation process is performed for a long time, the oxide film thickness near the end of the gate electrode 11 becomes thicker than necessary, an offset occurs at the end of the gate electrode 11, and the threshold voltage of the MISFET ( Vth) deviates from the design value. There is also a problem that the effective channel length is shorter than the processing value of the gate electrode 11. In particular, in a fine MISFET having a gate length of less than 0.25 μm, a thinning allowable amount from a design value of a gate processing dimension is severely limited from the viewpoint of device design. This is because even if the thinning amount is slightly increased, the threshold voltage is rapidly decreased by the short channel effect. Therefore, the upper limit of the thickness of the oxide film grown by the re-oxidation treatment is desirably about 50% of the thickness of the gate insulating film 9A.

  The above-described defect repair of the gate insulating film 9A can also be performed after forming the gate electrode 11 by patterning the W film 11A. That is, the defect repair of the gate insulating film 9A and the re-oxidation treatment of the gate insulating film 9A can be performed collectively. In this case, since the upper portion of the gate electrode 11 is covered with the silicon nitride film 13, oxygen is supplied to the gate insulating film 9 </ b> A immediately below the gate electrode 11 through the sidewall of the gate electrode 11.

Next, as shown in FIG. 18, an n ^- type semiconductor region 16 is formed in the p-type well 7 on both sides of the gate electrode 11 by ion-implanting an n-type impurity such as P (phosphorus) into the p-type well 7. Further, a p-type impurity, for example, B (boron) is ion-implanted into the n-type well 8 to form p ⁻ -type semiconductor regions 17 in the n-type well 8 on both sides of the gate electrode 11.

  Next, as shown in FIG. 19, sidewall spacers 18 are formed on the sidewalls of the gate electrode 11. The side wall spacers 18 are formed by, for example, anisotropically etching a silicon nitride film having a thickness of about 50 nm deposited on the substrate 1 by the CVD method and leaving the silicon nitride film on the side walls of the gate electrode 11.

Next, an n type impurity such as As (arsenic) is ion-implanted into the p type well 7 to form an n ⁺ type semiconductor region 20 (source and drain), and a p type impurity such as B (boron) is formed in the n type well 8. ) Is ion-implanted to form a p ⁺ type semiconductor region 21 (source, drain). Through the steps so far, the n-channel MISFET Qn is formed in the p-type well 7 and the p-channel MISFET Qp is formed in the n-type well 8.

Next, as shown in FIG. 20, a silicon oxide film 22 is deposited on the substrate 1 by a CVD method, and the surface thereof is flattened by using a chemical mechanical polishing method, and then a photoresist film (not shown) is masked. Then, the silicon oxide film 22 is dry etched to form a contact hole 23 above the n ⁺ type semiconductor region 20 (source, drain), and a contact hole 24 above the p ⁺ type semiconductor region 21 (source, drain). Form.

  Next, as shown in FIG. 21, after depositing a W film on top of the silicon oxide film 22 by CVD or sputtering, the W film is patterned using a photoresist film (not shown) as a mask. Wirings 25 to 30 are formed on the silicon oxide film 22.

(Embodiment 2)
When a metal film such as a W film or Mo film is directly deposited on the gate insulating film made of silicon oxide and heat treatment is performed, a high-resistance silicide compound is generated at the interface between the two, and the breakdown voltage of the gate insulating film is deteriorated. Sometimes. As a countermeasure, a method of forming a conductive barrier film that prevents an interfacial reaction between a W film (or Mo film) that is a gate electrode material and a gate insulating film made of silicon oxide thereunder is well known. . Suitable materials for this conductive barrier film are high melting points such as titanium nitride (TiN), tungsten nitride (WN), and molybdenum nitride (MoN), which are conductive materials having low reactivity and high heat resistance. Metal nitride. Further, nitrides such as tantalum (Ta), zirconium (Zr), and hafnium (Hf) can also be used.

  When the conductive barrier film is formed between the W film (or Mo film) and the gate insulating film made of silicon oxide under the W film, the defect repair of the gate insulating film 9A is performed by the following method.

  First, as shown in FIG. 22, a gate insulating film made of silicon oxide (or silicon oxynitride) having a film thickness of less than 5 nm is formed on the surface of each of the p-type well 7 and the n-type well 8 by the same method as in the first embodiment. After forming 9A, a conductive barrier film 12 is formed on the gate insulating film 9A, and a W film 11A (or Mo film) having a film thickness of about 50 nm is formed on the conductive barrier film 12 by sputtering or CVD. Form. The conductive barrier film 12 is composed of a WN film, a MoN film, or a TiN film deposited by a CVD method or a sputtering method, and has a thickness of about 5 nm.

  Next, in this state, heat treatment is performed to repair defects in the gate insulating film 9A. This heat treatment is performed by a method that can selectively oxidize only Si without oxidizing W (or Mo) which is a gate electrode material and metal (W, Ti or Mo) constituting the conductive barrier film.

  For example, when the gate electrode material is W and the barrier material is WN, the water + hydrogen partial pressure ratio is set within the region between the curve (a) and the curve (d) in FIG. By performing the heat treatment in the mixed gas atmosphere, defects in the gate insulating film 9A can be repaired without oxidizing the gate electrode material and the barrier material. Further, when the gate electrode material is Mo and the barrier material is MoN, the moisture + hydrogen mixed gas atmosphere in which the moisture / hydrogen partial pressure ratio is set within the range between the curves (b) and (d) By performing the heat treatment therein, defects in the gate insulating film 9A can be repaired without oxidizing the gate electrode material and the barrier material. That is, in these cases, the defect of the gate insulating film 9A can be repaired by the same method as in the first embodiment.

  On the other hand, when the gate electrode material is W (or Mo) and the barrier material is TiN, Ti has a higher oxidation rate than Si in the moisture + hydrogen mixed gas atmosphere as shown in FIG. Thus, it is not possible to selectively oxidize only Si without oxidizing it. That is, in this case, when the defect repair of the gate insulating film 9A is performed by the same method as in the first embodiment, the barrier material is also oxidized, and the resistance of the gate electrode is increased.

  However, in this case as well, the oxidation rate of Ti and Si can be slowed by using the catalyst type water + hydrogen mixed gas generator and setting the moisture in the water + hydrogen mixed gas to a very low concentration. Therefore, the increase in resistance of the gate electrode can be suppressed within a range that does not cause a problem in practice by minimizing the oxidation of the barrier material. Specifically, the heat treatment may be performed in a moisture + hydrogen mixed gas atmosphere having a moisture concentration of 1% or less, preferably about several ppm to 100 ppm.

  As another method for preventing the oxidation of the gate electrode material and repairing the defect of the gate insulating film 9A while minimizing the oxidation of the barrier material, the moisture / hydrogen partial pressure ratio is changed to the curve (a) in FIG. In the case where Mo is Mo, there is a method in which heat treatment is performed in a gas atmosphere in which nitrogen or ammonia is added to a water + hydrogen mixed gas set within a range between the region (b) and the curve (d).

  When heat treatment is performed in a moisture + hydrogen mixed gas atmosphere to which nitrogen or ammonia is added, OH groups and nitrogen diffuse into the conductive barrier film 12 through the W film 11A (or Mo) film, and oxidation of Ti by the OH groups The reaction and the nitriding reaction of Ti with nitrogen compete. Therefore, the defect of the gate insulating film 9A can be repaired while suppressing the oxidation of the conductive barrier film 12. Also in this case, it is desirable to reduce the moisture concentration and to make the oxidation rate of the conductive barrier film 12 as slow as possible. Further, when this gas is used, a part of the gate insulating film 9A composed of a silicon oxide film is converted into a silicon oxynitride film, so that the reliability and withstand voltage of the ultrathin gate insulating film 9A are further improved. To do.

  Next, as shown in FIG. 23, a silicon nitride film 13 having a film thickness of about 50 nm to 100 nm is deposited on the W film 11A by the CVD method, and then the silicon nitride film 13 is formed by dry etching using the photoresist film 14 as a mask. And the W film 11A are patterned to form the gate electrode 11. Thereafter, in order to regenerate the gate insulating film 9A shaved by the etching, the same heat treatment (reoxidation treatment) as that in the first embodiment is performed. Also in this embodiment, after the gate electrode 11 is formed, defect repair and re-oxidation treatment of the gate insulating film 9A can be performed collectively.

(Embodiment 3)
When the gate insulating film made of silicon oxide is thinned to a silicon dioxide equivalent film thickness of less than 5 nm, particularly less than 3 nm, a reduction in the withstand voltage due to the generation of direct tunneling current or hot carriers due to stress becomes obvious. In this embodiment, as a countermeasure, the gate insulating film is formed of a silicon nitride film or a composite insulating film of a silicon oxide film and a silicon nitride film.

  Since the silicon nitride film has a higher dielectric constant than the silicon oxide film, the silicon dioxide equivalent film thickness is thinner than the actual film thickness. Therefore, by configuring the gate insulating film with a single silicon nitride film or a composite film of it and silicon oxide, the effective film thickness can be increased compared to the gate insulating film configured with the silicon oxide film. The above problems can be improved. In addition, the above-described problem that occurs when a W film is directly deposited on the gate insulating film made of a silicon oxide film can be improved.

  Here, the silicon dioxide equivalent film thickness (hereinafter also simply referred to as the equivalent film thickness) dr of the single insulating film or the composite insulating film is the relative dielectric constant εi of the target insulating film, the film thickness di, When the relative dielectric constant of silicon is εs, the film thickness is defined by the equation shown in FIG.

The dielectric constants of silicon oxide (SiO ₂ ) and silicon nitride (Si ₃ N ₄ ) are _{4 to} 4.2 and 8, respectively. Accordingly, when the dielectric constant of silicon nitride is calculated as twice the dielectric constant of silicon oxide, for example, the silicon nitride equivalent film thickness of a silicon nitride film having a film thickness of 6 nm is 3 nm. That is, the gate insulating film made of a silicon nitride film with a thickness of 6 nm and the gate insulating film made of a silicon oxide film with a thickness of 3 nm have the same capacitance. The capacitance of the gate insulating film made of a composite film of a silicon oxide film with a thickness of 2 nm and a silicon nitride film with a thickness of 2 nm (equivalent film thickness = 1 nm) is a gate insulation made of a single silicon oxide film with a thickness of 3 nm. It is the same as the capacity of the membrane.

  Defect repair in the case where the gate insulating film is composed of a silicon nitride film (single or composite insulating film mainly composed of a silicon nitride film) is performed by the following method. First, as shown in FIG. 25, the p-type well 7 and the n-type well 8 are formed on the substrate 1 by the same method as in the first embodiment, and then the surfaces thereof are washed to remove unnecessary insulating films. Thereafter, a silicon nitride film is deposited on them by a CVD method to form a gate insulating film 9B. This silicon nitride film is preferably formed by a low pressure CVD method that causes less damage to the substrate 1 than by a plasma CVD method. Further, a silicon nitride film may be formed by plasma nitriding the surface of the substrate 1.

  The silicon dioxide equivalent film thickness of the gate insulating film 9B (silicon nitride film) is less than 5 nm when the gate length of the gate electrode formed thereon in the next step is about 0.25 μm to 0.2 μm. When it is about 0.18 μm to 0.14 μm, it is less than 4 nm, and when the gate length is about 0.13 μm to 0.1 μm, it is less than 3 nm. In this case, the actual film thickness of the gate insulating film 9B (silicon nitride film) is less than 10 nm, less than 8 nm, and less than 6 nm, respectively.

  Next, as shown in FIG. 26, a W film 11A (or Mo film) having a thickness of about 50 nm is formed on the gate insulating film 9B by sputtering or CVD.

  In the film of the gate insulating film 9B made of silicon nitride, defects caused mainly by Si-N bond defects occur during the film formation. Further, when the W film 11A is directly deposited on the gate insulating film 9B, stress generated in the film of the W film 11A at the time of film formation is applied to the gate insulating film 9B (silicon nitride film) immediately below the W film 11A. Defects also occur in the nearby gate insulating film 9B. The ultrathin gate insulating film 9B having a silicon dioxide equivalent film thickness of less than 5 nm deteriorates the withstand voltage and the TDDB resistance even if the above-described defects are slightly present in the film, causing a decrease in the reliability of the film.

  Therefore, the wafer 1 is heat-treated in an oxidizing atmosphere, and oxygen is supplied to the lower gate insulating film 9B through the W film 11A, thereby repairing the defects in the gate insulating film 9B. In this case, the defect repair is performed by introducing oxygen into a Si-N bond deficient portion existing in the silicon nitride film constituting the gate insulating film 9B to form a Si-O bond. Further, since the heat treatment for repairing defects must selectively oxidize only Si without oxidizing W which is a gate electrode material, the moisture / hydrogen partial pressure ratio is set to the same as in the first embodiment. The process is performed in a moisture + hydrogen mixed gas atmosphere set in a region between the curves (a) and (d) in FIG. Furthermore, when the gate electrode material is a Mo film, heat treatment is performed in a moisture + hydrogen mixed gas atmosphere in which the moisture / hydrogen partial pressure ratio is set within a range between the curves (b) and (d). Do. Further, the moisture + hydrogen mixed gas is generated using the catalyst-type moisture + hydrogen mixed gas generating device capable of controlling the moisture concentration with high accuracy.

  In order to form the gate insulating film 9B made of a composite film of a silicon nitride film and a silicon oxide film, for example, the surface of the substrate 1 (p-type well 7 and n-type well 8) is thermally oxidized to form a silicon oxide film. Thereafter, a silicon nitride film is deposited thereon by CVD. Also in this case, heat treatment is performed using the moisture + hydrogen mixed gas, and oxygen is introduced into the Si—N bond deficient portion present in the silicon nitride film and the Si—O bond deficient portion present in the silicon oxide film, respectively. To repair the defect.

  Defect repair of the gate insulating film 9B formed of a composite film of a silicon nitride film and a silicon oxide film may be performed in a gas atmosphere in which nitrogen or ammonia is added to a water + hydrogen mixed gas. In this case, since the silicon oxide film which is a part of the gate insulating film 9B is converted into an oxynitride film, the reliability and the withstand voltage of the gate insulating film 9B are further improved.

  Next, as shown in FIG. 27, a silicon nitride film 13 having a film thickness of about 50 nm to 100 nm is deposited on the W film 11A by the CVD method, and then the silicon nitride film 13 is dry-etched using the photoresist film 14 as a mask. And the W film 11A are patterned to form the gate electrode 11.

(Embodiment 4)
In the third embodiment, the gate insulating film is formed using a silicon nitride film having a dielectric constant approximately twice that of the silicon oxide film or an insulating film containing the silicon nitride film as a main component, but is higher than the silicon nitride film. When an insulating material having a dielectric constant is used, an insulating film having a silicon dioxide equivalent film thickness of less than 5 nm can be formed with a film thickness larger than that of the silicon nitride film, so that formation of a fine MISFET is further facilitated.

As a gate insulating film material having a dielectric constant higher than that of a silicon nitride film, refractory metal oxides such as tantalum oxide (Ta ₂ O ₅ ) and titanium oxide (TiO ₂ ) can be given. Tantalum oxide has a high dielectric constant of 20 to 25 and can be easily formed by CVD, so it has been used for DRAM (Dynamic Random Access Memory) capacitor materials. Is highly consistent. Further, titanium oxide having a dielectric constant of 80 to 120, which is even higher, is highly compatible with existing semiconductor manufacturing processes because Ti is used as a silicide material in the semiconductor manufacturing process. In addition, zirconium (Zr) and hafnium (Hf) oxides (ZrO ₂ , HfO ₂ ), which are the same group 4A metals as titanium, also have a high dielectric constant substantially the same as titanium oxide, and are chemically Since it is stable, it can be used as an ultra-thin gate insulating film material.

  For example, in order to form a MISFET having a gate insulating film made of titanium oxide, first, as shown in FIG. 28, a p-type well 7 and an n-type well 8 are formed on a substrate 1 by the same method as in the first embodiment. After the formation, the surfaces are cleaned to remove unnecessary insulating films, and a titanium oxide film is deposited thereon by sputtering to form a gate insulating film 9C. At this time, by setting the thickness of the titanium oxide film to about 40 to 60 nm, the gate insulating film 9C having a silicon dioxide equivalent film thickness of 2 nm can be obtained.

  Next, as shown in FIG. 29, a W film 11A (or Mo film) having a thickness of about 50 nm is formed on the gate insulating film 9C by sputtering or CVD.

  The crystalline metal oxide such as titanium oxide constituting the gate insulating film 9C includes many defects (mainly oxygen vacancies existing in the crystal or at the grain boundaries) that are current leakage paths in the film immediately after the film formation. It is out. Further, when the W film 11A is directly deposited on the gate insulating film 9C, stress generated in the film of the W film 11A at the time of film formation is applied to the gate insulating film 9C immediately below the gate insulating film 9C. A defect also occurs in 9C. Therefore, in order to obtain a titanium oxide film having an insulating characteristic that can be used as a gate insulating film, it is necessary to repair these defects.

  In order to repair defects in the gate insulating film 9C made of a refractory metal oxide such as titanium oxide, the substrate 1 is heat-treated in an oxidizing atmosphere, and oxygen is introduced into oxygen deficient portions of the gate insulating film 9C through the W film 11A. Introduce to modify and crystallize the film.

  When the refractory metal oxide is titanium oxide, the heat treatment must be performed in an atmosphere in which Ti is oxidized without substantially oxidizing W, which is a gate electrode material deposited on the refractory metal oxide. Therefore, this heat treatment needs to be performed in a moisture + hydrogen mixed gas atmosphere in which the moisture / hydrogen partial pressure ratio is set within the range between the curves (a) and (e) shown in FIG. . However, as shown in the figure, Ti has an equilibrium vapor pressure curve in a moisture + hydrogen mixed gas atmosphere that is slightly lower in moisture partial pressure than Si, so that heat treatment is performed in a moisture + hydrogen mixed gas atmosphere having a high moisture concentration. When performing the above, the substrate 1 is also oxidized. As a result, a silicon oxide film is formed at the interface between the gate insulating film 9C and the substrate 1 immediately below it, and the effective silicon dioxide equivalent film thickness of the gate insulating film 9C is increased.

  Therefore, when it is desired to suppress the growth of the silicon oxide film as much as possible, heat treatment is performed by setting the moisture in the moisture + hydrogen mixed gas to an extremely low concentration using the catalyst-type moisture + hydrogen mixed gas generating apparatus. Thereby, since the oxidation rate of Si is slowed, it is possible to repair defects of the gate insulating film 9C while minimizing the oxidation of the substrate 1. Specifically, the moisture concentration in the moisture + hydrogen mixed gas atmosphere is set to about several ppm to 100 ppm, and heat treatment is performed in a temperature range of 400 ° C. to 700 ° C.

Zr and Hf described above, like Ti, have a redox equilibrium curve in a moisture + hydrogen mixed gas atmosphere on the lower moisture side than that of Si. Accordingly, when the gate insulating film 9C in which a thin film of these refractory metal oxides (ZrO ₂ , HfO ₂ ) is deposited on the substrate 1 is formed, the defect repair is performed by the gate insulating film 9C made of titanium oxide. The method is the same as that for defect repair. That is, heat treatment is performed in a water + hydrogen mixed gas atmosphere in which the moisture / hydrogen partial pressure ratio is set to a ratio that does not oxidize the gate electrode material (W) and selectively oxidizes only these metals (Zr, Hf). I do.

  On the other hand, in order to form a MISFET having a gate insulating film made of tantalum oxide, a tantalum oxide film is first deposited by CVD on the substrate 1 (p-type well 7 and n-type well 8). 9C is formed. At this time, by setting the film thickness of the tantalum oxide film to about 10 nm to 12 nm, the gate insulating film 9C having a silicon dioxide equivalent film thickness of 2 nm can be obtained.

  In order to repair defects in the gate insulating film 9C made of tantalum oxide, heat treatment is performed in an atmosphere in which Ta is oxidized without substantially oxidizing W, which is a gate electrode material deposited thereon. That is, after depositing the W film 11A on the gate insulating film 9C, the moisture / hydrogen partial pressure ratio is set within the range of the region sandwiched between the curves (a) and (c) in FIG. The substrate 1 is heat-treated in a hydrogen mixed gas atmosphere. However, as shown in the figure, since Ta has a lower oxidation rate than Si in a moisture + hydrogen mixed gas atmosphere, only Ta cannot be oxidized without substantially oxidizing Si. That is, when repairing a defect in the gate insulating film 9C made of tantalum oxide, the substrate 1 is also oxidized at the same time. As a result, a silicon oxide film is formed at the interface between the gate insulating film 9C and the substrate 1 immediately below it, and the effective silicon dioxide equivalent film thickness of the gate insulating film 9C is increased.

  However, also in this case, the heat treatment is performed by using the catalyst type water + hydrogen mixed gas generator and setting the moisture in the water + hydrogen mixed gas to a very low concentration. As a result, the oxidation rate of Ta and Si is slowed, so that the oxidation of the substrate 1 can be minimized and the defect of the gate insulating film 9C can be repaired. Specifically, the moisture concentration of the water + hydrogen mixed gas is set to about 1% to 50%, and heat treatment is performed in a temperature range of 400 ° C. to 700 ° C.

  Defect repair of the gate insulating film 9C made of a refractory metal oxide such as titanium oxide, zirconium oxide, hafnium oxide, or tantalum oxide film is performed before the gate electrode material (W film 11A) is deposited thereon. Also good. In this case, since sufficient oxygen can be supplied to the metal oxide constituting the gate insulating film 9C, defects in the film can be repaired more reliably. However, in order to repair defects generated in the gate insulating film 9C due to the deposition of the W film 11A, it is necessary to perform the above heat treatment again after the deposition of the W film 11A.

  The defect repair of the gate insulating film 9C made of the above-described refractory metal oxide may be performed after the gate electrode is formed by patterning the W film or the Mo film deposited thereon. Further, it may be performed before and after the formation of the gate electrode.

The gate insulating film made of a metal oxide can also be formed using alumina (Al ₂ O ₃ ) having a dielectric constant of 8 to 10. Further, it can be formed using a metal oxide (for example, BST (barium strontium titanate), etc.) having a paraelectric phase at an operating temperature, which is a high dielectric material including an ABO ₃ type perovskite structure. . Furthermore, it may be formed using a binary or multi-element oxide containing two or more kinds of metal oxides as a main component, or a composite film of these metal oxides and a silicon oxide film or a silicon nitride film. it can.

(Embodiment 5)
The gate insulating film 9C made of an oxide of a refractory metal having an equilibrium curve of oxidation-reduction reaction in a moisture + hydrogen mixed gas atmosphere such as titanium oxide, zirconium oxide, hafnium oxide, etc. on the lower moisture side than that of Si is It can also be formed by such a method.

  First, as shown in FIG. 30, the p-type well 7 and the n-type well 8 are formed on the substrate 1 by the same method as in the first embodiment, and then the surfaces thereof are washed to remove unnecessary insulating films. Thereafter, a Ti film 31 is deposited on them by sputtering.

  Next, as shown in FIG. 31, the water / hydrogen partial pressure ratio is such that Si is not substantially oxidized and only Ti is selectively oxidized (curve (d) and curve (e) in FIG. 13). The substrate 1 is heat-treated in a moisture + hydrogen mixed gas atmosphere set within a region between the two. As a result, the Ti film 31 is oxidized and converted into a titanium oxide film, resulting in a gate insulating film 9C made of titanium oxide.

  When the gate insulating film 9C made of a zirconium oxide film (or hafnium oxide film) is formed by the same method, after depositing a Zr film (or Hf film) on the substrate 1, the moisture / hydrogen partial pressure ratio is the substrate 1 ( The substrate 1 is heat-treated in a moisture + hydrogen mixed gas atmosphere set to a ratio that does not substantially oxidize Si) but selectively oxidizes only Zr (or Hf). As a result, the Zr film (or Hf film) is oxidized and converted into a zirconium oxide film (or hafnium oxide film). As a result, a gate insulating film 9C made of a zirconium oxide film (or hafnium oxide film) is obtained.

  The heat treatment for converting the refractory metal film deposited on the substrate 1 into its oxide may be performed after depositing a gate electrode material such as a W film on the refractory metal film. In this case, as shown in FIG. 32, first, a Ti film 31 is deposited on the upper portion of the substrate 1 (p-type well 7 and n-type well 8) by the sputtering method, and then the sputtering method or the CVD is formed on the Ti film 31. The W film 11A (or Mo film) having a thickness of about 50 nm is formed by the method.

  Next, the ratio of the moisture / hydrogen partial pressure ratio that does not substantially oxidize Si but selectively oxidizes only Ti (in the region sandwiched between the curves (d) and (e) in FIG. 13). The substrate 1 is heat-treated in a moisture + hydrogen mixed gas atmosphere set within the range. As a result, the oxidized species (OH group) derived from the moisture in the moisture + hydrogen mixed gas enters the Ti film 31 through the W film 11A (or Mo film) and converts the Ti film 31 into a titanium oxide film. As shown in FIG. 33, a gate insulating film 9C made of a titanium oxide film is formed immediately below the W film 11A (or Mo film) which is a gate electrode material. In addition, even if heat treatment is performed in a moisture + hydrogen mixed gas atmosphere in which the moisture / hydrogen partial pressure ratio is set to the above ratio, the W film 11A (or Mo film) is not oxidized, so that the resistance of the gate electrode is reduced. It will never grow.

  The gate insulating film 9C made of a zirconium oxide film or a hafnium oxide film can also be formed by oxidizing the zirconium film or the hafnium film by the above method.

(Embodiment 6)
The gate insulating film 9A having a silicon dioxide equivalent film thickness of less than 5 nm and containing silicon oxide as a main component can also be formed by the following method.

  First, as shown in FIG. 34, a p-type well 7 and an n-type well 8 are formed on the substrate 1 by the same method as in the first embodiment, and then the surfaces thereof are washed to remove unnecessary insulating films. Thereafter, a W film 11A (or Mo film) having a film thickness of about 50 nm is formed on them by sputtering or CVD.

  Next, the substrate 1 on which the W film 11A is formed is heat-treated. In this heat treatment, the moisture / hydrogen partial pressure ratio is set within the range between the curves (a) and (d) of FIG. The process is performed in a moisture + hydrogen mixed gas atmosphere in which the moisture concentration is set so as to selectively oxidize only Si. The moisture + hydrogen mixed gas may be generated by using the catalyst type moisture + hydrogen mixed gas generating device capable of controlling the moisture concentration with high accuracy.

  By performing the above heat treatment, oxidized species (OH groups) derived from moisture in the moisture + hydrogen mixed gas enter the substrate 1 through the W film 11A, and the surface thereof is oxidized. As a result, as shown in FIG. 35, a gate insulating film 9A made of an extremely thin silicon oxide film is formed at the interface between the W film 11A and the substrate 1. According to this method, it is possible to form a gate insulating film composed of an extremely thin silicon oxide film having a thickness of 1 nm or less.

  If the heat treatment temperature for oxidizing the surface of the substrate 1 exceeds 550 ° C. to 600 ° C., the W film 11A reacts with the substrate 1 to form a silicide compound at the interface between them, and this silicide reaction occurs. It is necessary to perform heat treatment in a low temperature region. Similarly, in the case where the metal film for the gate electrode is Mo, a silicide reaction occurs when the heat treatment temperature exceeds 500 ° C. Therefore, it is necessary to perform the heat treatment in a temperature range below that.

  The heat treatment for forming the gate insulating film 9D made of silicon oxide at the interface between the W film 11A and the substrate 1 may be performed after the gate electrode is formed. In this case, as shown in FIG. 36, a W film 11A having a thickness of about 50 nm is first formed on the substrate 1 (p-type well 7 and n-type well 8) by sputtering or CVD, and then a photoresist is formed. The gate electrode 11 is formed by dry etching the W film 11A using a film (not shown) as a mask. The gate electrode 11 may be formed by dry etching the Mo film.

  Next, the substrate 1 on which the gate electrode 11 is formed is heat treated. In this heat treatment, the moisture / hydrogen partial pressure ratio is set within the range between the curves (a) and (d) of FIG. The process is performed in a moisture + hydrogen mixed gas atmosphere in which the moisture concentration is set so as to selectively oxidize only Si.

  By performing the above heat treatment, the surface of the substrate 1 is oxidized, and a gate insulating film 9A 'made of silicon oxide is formed as shown in FIG. At this time, oxidizing species (OH groups) are also supplied to the substrate 1 immediately below the gate electrode 11 through the W film (11A) constituting the gate electrode 11, so that the substrate 1 in this region is also oxidized. However, since the substrate 1 immediately below the gate electrode 11 has a smaller amount of oxidation than the substrate 1 in other regions, the gate insulating film formed of an extremely thin silicon oxide film at the interface between the W film 11A and the substrate 1 9A is formed. According to this method, it is possible to form a gate insulating film composed of an extremely thin silicon oxide film having a thickness of 1 nm or less.

  In this case as well, it is necessary to perform heat treatment in a temperature region where no silicide compound is generated at the interface between the W film (11A) constituting the gate electrode 11 and the substrate 1.

(Embodiment 7)
The present embodiment is applied to the manufacture of a MISFET in which a gate electrode is formed using a damascene method.

  First, as shown in FIG. 38, after the p-type well 7 and the n-type well 8 are formed on the substrate 1 by the same method as in the first embodiment, the p-type well 7 and the n-type well 8 remain on the respective surfaces. A polycrystalline silicon film 41A having a film thickness of about 50 nm is deposited on the silicon oxide film 2 by CVD.

Next, as shown in FIG. 39, after patterning the polycrystalline silicon film 41A by dry etching using a photoresist film (not shown) as a mask to form the gate electrode 41, the same method as in the first embodiment is performed. Side wall spacers 18 are formed on the sidewalls of the gate electrode 11, and n ⁺ type semiconductor regions 20 (source and drain) are formed in the p type well 7 and p ⁺ type semiconductor regions 21 (source and drain) are formed in the n type well 8. Form each one. Note that the material constituting the gate electrode 41 does not have to be polycrystalline silicon, and may be composed of, for example, silicon nitride.

  Next, as shown in FIG. 40, after the silicon oxide film 42 is deposited on the substrate 1 by the CVD method, the silicon oxide film 42 is flattened by the chemical mechanical polishing method, so that the height of the surface is set to the gate electrode. Adjust to 11 height.

  Next, as shown in FIG. 41, by removing the gate electrode 11 by dry etching using the silicon oxide film 42 as a mask, the surface of the substrate 1 (p-type well 7, n-type well 8) below the gate electrode 11 is removed. To expose.

  Next, as shown in FIG. 42, an extremely thin silicon oxide film 43 having a thickness of 1 nm or less is formed on the surface of the substrate 1 (p-type well 7, n-type well 8) exposed by removing the gate electrode 11. This silicon oxide film 43 is formed by heat-treating the substrate 1 in a moisture + hydrogen mixed gas atmosphere in which the moisture / hydrogen partial pressure ratio is set to oxidize Si. The moisture concentration at this time is, for example, about 1% to 30%, and the heat treatment temperature is, for example, about 700 ° C. to 800 ° C.

  Next, as shown in FIG. 43, an extremely thin titanium oxide film 44 having a silicon dioxide equivalent film thickness of 1 nm or less is deposited on the silicon oxide films 42 and 43 by sputtering. The insulating film deposited at this time may be any metal oxide for a gate insulating film having a high dielectric constant, such as zirconium oxide, hafnium oxide, or tantalum oxide film.

  Next, as shown in FIG. 44, the titanium oxide film 44 on the silicon oxide film 42 is removed by a chemical mechanical polishing method. As a result, gate insulation comprising a composite film of the silicon oxide film 43 and the titanium oxide film 44 on the surface of the substrate 1 (p-type well 7, n-type well 8) in the region where the gate electrode is to be formed in the next step. A film 9E is formed. At this time, a part of the gate insulating film 9E (titanium oxide film 44) is also formed on the side wall of the side wall spacer 48.

  Next, heat treatment for repairing defects in the silicon oxide film 43 and the titanium oxide film 44 constituting the gate insulating film 9E is performed. This heat treatment is performed by heat-treating the substrate 1 in a moisture + hydrogen mixed gas atmosphere in which the moisture / hydrogen partial pressure ratio is set to oxidize Si and Ti. The moisture concentration at this time is, for example, about 1% to 30%, and the heat treatment temperature is, for example, about 600 ° C. to 800 ° C.

  Next, as shown in FIG. 45, after a W film is formed on the silicon oxide film 42 and the gate insulating film 9E by a sputtering method or a CVD method, the W film on the silicon oxide film 42 is formed by a chemical mechanical polishing method. By removing, the gate electrode 11 is formed. The gate electrode 11 may be made of Mo, Cu, Al, or the like. Through the steps so far, the n-channel MISFET Qn is formed in the p-type well 7 and the p-channel MISFET Qp is formed in the n-type well 8.

  When the gate electrode 11 is formed by the above-described damascene method, a part of the gate insulating film 9E is also formed on the gate electrode 11, so that the breakdown voltage of the gate insulating film 9E at the lower side wall of the gate electrode 11 is improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is used for manufacturing a semiconductor integrated circuit device having a MISFET having a metal gate electrode.

It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 1 of this invention. It is the schematic which shows the single-wafer | sheet-fed film-forming apparatus used for formation of a gate insulating film. (A) is a schematic plan view which shows an example of a specific structure of an oxide film formation chamber, (b) is sectional drawing along the B-B 'line of (a). It is the schematic which shows a catalyst type water | moisture + oxygen mixed gas production | generation apparatus. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 1 of this invention. It is a graph which shows the dependence of the water concentration with respect to the oxide film growth rate. (A) is explanatory drawing for defining the moisture concentration of a water | moisture + oxygen mixed gas, (b) is explanatory drawing for defining the moisture concentration of a water | moisture + hydrogen mixed gas. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 1 of this invention. It is a graph which shows the temperature dependence of the equilibrium vapor pressure ratio (P _H2O / P _H2 ) of the oxidation-reduction reaction using the water + hydrogen mixed gas. It is the schematic which shows a catalyst type water | moisture + hydrogen mixed gas production | generation apparatus and a hydrogen gas abatement apparatus. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 1 of this invention. It is a principal part expanded sectional view of the semiconductor substrate which shows the manufacturing method of the CMOS-logic LSI which is Embodiment 1 of this invention. It is a principal part expanded sectional view of the semiconductor substrate which shows the manufacturing method of the CMOS-logic LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 2 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 2 of this invention. It is a formula which defines the silicon dioxide equivalent film thickness of an insulating film. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 3 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 3 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 3 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 4 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 4 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 5 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 5 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 5 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 5 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 6 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 6 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 6 of this invention. It is a principal part expanded sectional view of the semiconductor substrate which shows the manufacturing method of the CMOS-logic LSI which is Embodiment 6 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 7 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 7 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 7 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 7 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 7 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 7 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 7 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of CMOS-logic LSI which is Embodiment 7 of this invention.

Explanation of symbols

1 Silicon substrate (wafer) for semiconductor integrated circuit devices
2 silicon oxide film 3 silicon nitride film 4 element isolation trench 5 silicon oxide film 6 silicon oxide film 7 p-type well 8 n-type well 9A to 9E gate insulating film 11A W film 11 gate electrode 12 conductive barrier film 13 silicon nitride film 14 Photoresist film 15 Silicon nitride film 16 n ⁻ type semiconductor region 17 p ⁻ type semiconductor region 18 Side wall spacer 20 n ⁺ type semiconductor region (source, drain)
21 p ⁺ type semiconductor region (source, drain)
22 Silicon oxide film 23 Contact hole 24 Contact holes 25-30 Wiring 31 Ti film 41A Polycrystalline silicon film 41 Gate electrode 42 Silicon oxide film 43 Silicon oxide film 44 Titanium oxide film 100 Film forming apparatus 101 Cleaning apparatus 102 Loader 103 Cleaning chamber 104 Hydrofluoric acid cleaning chamber 105 Drying chamber 106 Buffer 107 Oxide film formation chamber 108 Oxynitride film formation chamber 109 Heat treatment chamber 110 Loader / unloader 111 Metal film formation chamber 112 Transfer system 113 Robot hand 120 Chamber 122 Soaking ring 123 Susceptor 124 Support arm 125 Thermocouple 126 Gas introduction pipe 127 Through hole 128 Bulkhead 129 Exhaust pipe 130 Lamp 140 Moisture + oxygen mixed gas generator 141 Reactor 142 Coil 143 Heaters 144a to 144c Gas storage tank 145 Pipe 146 a to 146c Mass flow controllers 147a to 147c Open / close valve 148 Connection unit 240 Moisture + hydrogen mixed gas generator 241a Reactor 241b Reactor 242 Coil 243 Heater 244a to 144c Gas storage tank 245 Piping 246a to 246e Mass flow controllers 247a to 247e Open / close valve 250 Hydrogen gas abatement device 251 Pipe 252 Check valve 253 Exhaust pipe 254 Hydrogen gas sensor 255, 256 Cooler Qn n-channel MOSFET
Qp p-channel MOSFET

Claims (16)

A method of manufacturing a semiconductor integrated circuit device comprising the following steps;
(A) A first film mainly containing a first refractory metal having a redox equilibrium curve in a gas atmosphere containing moisture and hydrogen on the lower moisture side than that of silicon is used as the first film of the wafer. Forming on the silicon surface on the main surface of
(B) in a gas atmosphere containing moisture and hydrogen set to such a ratio that the moisture / hydrogen partial pressure ratio does not substantially oxidize the silicon surface and oxidizes the first refractory metal; Forming a gate insulating film on the silicon surface by performing a heat treatment on the first main surface on which the first film is formed and converting the first refractory metal into an oxide thereof;
(C) Before or after the step (b), a second refractory metal gate electrode having a redox equilibrium curve in a gas atmosphere containing moisture and hydrogen on the higher moisture side than that of silicon is formed. Process.   2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first refractory metal is titanium, zirconium, or hafnium.   3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the gas atmosphere containing moisture and hydrogen in the step (b) is formed by synthesizing moisture using a catalyst. A method for manufacturing an integrated circuit device. A method of manufacturing a semiconductor integrated circuit device comprising the following steps;
(A) A gate insulating film mainly composed of an oxide of a first refractory metal whose oxidation-reduction equilibrium curve in a gas atmosphere containing moisture and hydrogen is on the moisture side lower than that of silicon is formed on the wafer. Forming on the silicon surface on the first major surface;
(B) In a gas atmosphere containing moisture and hydrogen set to such a ratio that the moisture / hydrogen partial pressure ratio does not substantially oxidize the silicon surface and generates the oxide of the first refractory metal. Then, heat treatment is performed on the first main surface on which the gate insulating film is formed, and oxygen is supplied to the first refractory metal oxide to repair defects in the gate insulating film. Process,
(C) A step of forming a gate electrode on the gate insulating film before or after the step (b).   5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein the gate insulating film in the step (a) is formed on the silicon surface via a silicon oxide film. Production method.   6. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein the first refractory metal is titanium, zirconium, or hafnium.   7. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the gas atmosphere containing water and hydrogen in the step (b) is formed by synthesizing water using a catalyst. A method for manufacturing an integrated circuit device. A method of manufacturing a semiconductor integrated circuit device comprising the following steps;
(A) By patterning a metal film containing a first refractory metal as a main component whose oxidation-reduction equilibrium curve in a gas atmosphere containing moisture and hydrogen is on a higher moisture side than that of silicon, Forming a gate electrode on the silicon surface on the first major surface;
(B) With respect to the first main surface in a state where the gate electrode is formed, a moisture / hydrogen partial pressure ratio is set to a ratio that does not substantially oxidize the gate electrode but oxidizes the silicon surface. By performing heat treatment in a gas atmosphere containing moisture and hydrogen, the silicon surface immediately below the gate electrode has a silicon dioxide equivalent film thickness of less than 5 nm, and silicon oxide is a major component. Forming a gate insulating film.   9. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein the first refractory metal is molybdenum or tungsten. A method of manufacturing a semiconductor integrated circuit device comprising the following steps;
(A) a first film to be a gate insulating film mainly composed of a first refractory metal whose oxidation-reduction equilibrium curve in an atmosphere containing moisture and hydrogen is on the moisture side lower than that of silicon; Forming on the silicon surface on the first major surface of the wafer;
(B) In a state where the first film is formed, a second electrode to be a gate electrode whose main component is a second refractory metal whose redox equilibrium curve is on a higher moisture side than that of silicon. Forming the film on the first film,
(C) forming the gate electrode by patterning the first film and the second film;
(D) In the state where the gate electrode is formed, the water / hydrogen partial pressure ratio with respect to the first main surface does not substantially oxidize the second film and oxidizes the first film. Forming a gate insulating film by performing a heat treatment in a gas atmosphere containing moisture and hydrogen set to a ratio and oxidizing the first film immediately below the second film;   11. The method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein the second refractory metal is molybdenum or tungsten.   12. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein the first refractory metal is titanium, zirconium, or hafnium. A method of manufacturing a semiconductor integrated circuit device comprising the following steps;
(A) A first film mainly containing a first refractory metal having a redox equilibrium curve in a gas atmosphere containing moisture and hydrogen on the lower moisture side than that of silicon is used as the first film of the wafer. Forming on the silicon surface on the main surface of
(B) in a gas atmosphere containing moisture and hydrogen set to such a ratio that the moisture / hydrogen partial pressure ratio does not substantially oxidize the silicon surface and oxidizes the first refractory metal; Forming a gate insulating film on the silicon surface by performing a heat treatment on the first main surface on which the first film is formed and converting the first refractory metal into an oxide thereof;
(C) A step of forming a gate electrode on the gate insulating film before or after the step (b).   14. The method of manufacturing a semiconductor integrated circuit device according to claim 13, wherein the first film in the step (a) is formed on the silicon surface via a silicon oxide film. Manufacturing method.   14. The method of manufacturing a semiconductor integrated circuit device according to claim 13, wherein the first refractory metal is titanium, zirconium, or hafnium.   14. The method of manufacturing a semiconductor integrated circuit device according to claim 13, wherein the gas atmosphere containing the water and hydrogen in the step (b) is formed by synthesizing water using a catalyst. A method for manufacturing an integrated circuit device.

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