JP2006201807A - Power supply circuit, liquid crystal display device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply circuit with which electric power consumption is reduced, a liquid crystal display device, and electronic equipment. <P>SOLUTION: The power supply circuit includes: a charge pump circuit which performs a charge pump operation, using the clock generated by a pulsed clock including periodically generated pulses and to which any of first to N-th potentials is supplied directly or via an adjusting mechanism; a means which stops the charge of a pumping capacitor included in a charge pump circuit and the charge of a backup capacitor by the pumping capacitor in the generation period of the pulsed clock; and a means which stops the operation of the charge pump by stopping the prescribed clock supplied to the charge pump circuit when a display off control signal of a liquid crystal panel is inputted. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a power supply circuit, a liquid crystal display device including the power supply circuit, and an electronic apparatus including the liquid crystal display device.

  As a first background art, a power supply circuit used for a one-line line sequential driving liquid crystal display device will be described with reference to FIG. This figure is basically the same as FIG. 3 of JP-A-2-150819. Here, V0 to V5 have a relationship of VD = V0−V1 = V1−V2 = V3−V4 = V4−V5. For example, when the duty is 1/240, VD is about 1.6V.

  The voltage input from the outside to the liquid crystal display device is VCC for the logic part of the driver IC and GND for generating the liquid crystal panel drive voltage using GND as a reference potential. VEE is considerably higher than VCC. For example, in the case of 1/240 duty, it is about 20V to 25V. Among V0 to V5, VEE is used as it is for V0, and GND is used as it is for V5. As the remaining V1 to V4, a voltage obtained by dividing the voltage between VEE and GND by resistors R1 to R5 and subjected to low impedance conversion by operational amplifiers OP1 to OP4 is used. OP1 to OP4 operate with a VEE voltage, and VCC is not directly involved in forming the panel drive voltage itself.

  Hereinafter, the scanning line side is represented by Y and the data line side is represented by X, and power consumption will be described. For example, a scanning line electrode of the panel is represented as a Y electrode, a driver IC that drives the Y electrode is represented as a Y driver, a data line electrode of the panel is represented as an X electrode, and a driver IC that drives the X electrode is represented as an X driver. The voltage applied to the non-selected Y electrode is V1 or V4. When the unselected Y electrode is V1, the voltage applied to the X electrode is V0 or V2, and when the unselected Y electrode is V4, the voltage applied to the X electrode is V3 or V5.

  In the case of 1/240 duty, the Y electrode in the selected state is only one line, while the remaining 239 lines are all in the non-selected state. Therefore, the charge / discharge current flowing between the X electrode and the selected Y electrode is considerably smaller than the charge / discharge current flowing between the X electrode and the non-selected Y electrode. That is, the current consumption of the liquid crystal panel itself is mostly charge / discharge current flowing between the X electrode and the non-selected Y electrode. Therefore, only the charge / discharge current flowing between the X electrode and the non-selected Y electrode is noted here.

  For example, consider a case where the voltage of the X electrode changes from V0 to V2 when the voltage of the non-selected Y electrode is V1. At this time, assuming that the capacitance of the liquid crystal layer between the XY electrodes is Cpn, the charge of Cpn × (V0−V1) flows out of V0 and flows into V1 when the voltage of the X electrode changes from V0 to V1. (See D in FIG. 48). Next, when the voltage of the X electrode changes from V1 to V2, the charge of Cpn × (V1−V2) flows out of V1 and flows into V2 (see E). Here, since V0−V1 = V1−V2, the charge flowing into V1 is equal to the charge flowing out from V1. Therefore, the flow of charge into and out of V1 is deducted to zero, and as a result, the charge of Cpn × (V0−V2) flows out of V0 and flows into V2 (see F). This electric charge finally flows into the GND through the operational amplifier OP2 (see G). However, this charge does not work effectively in the path that travels through OP2 and reaches GND, but merely generates heat loss and heats OP2. If the charging / discharging current of the panel in this case is Ipn and GND = 0V, the power consumption by this Ipn is Ipn × VEE. As is apparent from G in FIG. 48, the effective utilization rate of this Ipn is (V0−V2) / VEE. In the case of 1/240 duty, V0-V2 is about 2 × 1.6V, whereas VEE is 20V to 25V, so the effective utilization rate is 16% or less.

  As a second background art, a description will be given of a power supply circuit used in a four-line simultaneous selection driving liquid crystal display device. The basic concept of a driving method (MLS driving) for simultaneously selecting a plurality of Y electrodes (row electrodes) is described in Reference 1 (A GENERALIZED ADDRESSING TECHNIQUE FOR RMS RESPONDING MATRIX LCDS. 1988 INTERNAL DISPLAY RESEARCH CON. Or USP 5,262,881. When the response of the liquid crystal is made faster by simple one line line sequential driving, a decrease in contrast becomes a problem. However, MLS driving can solve this problem.

  When the L line (L is a positive integer of 2 or more) is simultaneously selected by MLS driving, the Y electrode needs a potential of VM and a total of three levels of VH and VL having the VM as a midpoint potential. Here, VM is used as a non-selection potential, and VH and VL are used as selection potentials. The X electrode requires a potential of (L + 1) level centered on VM. As L increases, the voltage width VH-HL for driving the Y electrode decreases, and conversely, a large voltage width is required for driving the X electrode.

  FIG. 49 shows an example of a power supply circuit conceivable when the 4-line simultaneous selection method is used. The voltages required for driving the panel are VH and VL that are the selection voltages of the Y electrode, VM that is the non-selection voltage of the Y electrode, and Vx0 to Vx4 that are the drive voltages of the X electrode. VM is the central potential of the voltage applied to the panel, and the relationship of VH-VM = VM-VL, Vx0-Vx1 = Vx1-Vx2 = Vx2-Vx3 = Vx3-Vx4 is established. Further, the central potential Vx2 on the X electrode side is the same potential as VM. For example, in a panel corresponding to 1/240 duty, VH-VL is about 25V and Vx0-Vx1 is about 1.6V.

  The voltage input from the outside to the liquid crystal display device is VCC for the logic part of the driver IC and VEE (= VH−VL) for creating the liquid crystal panel drive voltage with GND as the reference potential (0V). As described above, VEE is considerably higher voltage than VCC. In FIG. 49, VDDy and VSSy are voltages of the logic part of the Y driver, and VCC and GND are connected as they are. VDDx and VSSx are voltages of the logic part of the X driver. When GND = 0V, VDDx−VSSx = VCC. The withstand voltage required for the X driver is Vx0-Vx4. For example, a panel equivalent to 1/240 duty requires about 7V. VEE and GND are used as they are for VH and VL, respectively. As Vx0 to Vx4 and VSSX, a voltage obtained by dividing the voltage between VEE and GND by resistors R1 to R6 and subjected to low impedance conversion by operational amplifiers OP1 to OP6 is used. In order to establish the relationship of VDDx−VSSx = VCC, the resistance values of R7 to R10 are set so that R7 = R8 and R9 = R10. OP1 to OP6 operate with a VEE system voltage, and VCC is not directly involved in forming the panel drive voltage itself.

  Hereinafter, power consumption when the power supply circuit shown in FIG. 49 is used will be described. The voltage applied to the Y electrode when not selected is VM, and the voltages applied to the X electrode are Vx0 to Vx4. As in the case of the one-line line sequential driving described above, most of the consumption current of the liquid crystal panel itself is a charge / discharge current flowing between the X electrode and the non-selected Y electrode. The power consumption due to the charging / discharging current Ipn of the panel is Ipn × VEE with GND = 0V. However, as described above, the voltage difference between Vx0 to Vx4 and VM is considerably smaller than the voltage difference between VEE and GND. Accordingly, the effective utilization rate of Ipn is extremely low, and most of the Ipn moves through the operational amplifier and reaches the GND, resulting in only heat loss and heating the operational amplifier.

  Furthermore, if the current consumption in the logic part or the like of the X driver is IXD, the resulting power consumption is IXD × VEE instead of IXD × VCC. The part of IXD × (VEE-VCC) is also moved through the operational amplifier and reaches the GND, resulting in heat loss and heating the operational amplifier. According to the multiple line simultaneous selection method, the operating voltage width of the X driver can be reduced, but this background technology cannot utilize this advantage at all for reducing power consumption.

As a third background art, a power supply circuit of a liquid crystal display device using a two-terminal nonlinear switching element will be described. A driving method of such a liquid crystal display device is described in Japanese Patent Publication No. 5-34655, and a power circuit used in this case is described in Japanese Patent Publication No. 5-46954 and US Pat. No. 5,101,116. There is. Hereinafter, the operation of this power supply circuit will be described with reference to FIG. 50 (the drive voltage waveform described in FIG. 1A of USP 5, 101, 116 is transcribed) and FIG. 51 (the circuit described in FIG. 2B is transcribed). The configuration will be described. In FIG. 50, TPy (y = 1, 2,..., N) is a voltage waveform for driving the Y electrode, VD2 is a positive selection voltage, VS2 is a negative selection voltage, and VM ⁺ is after selecting VD2. The non-selection voltage VM ⁻ is a non-selection voltage after selecting VS2. VD2-VS2 is about 40V, and the relationship of VD2-VM ⁺ = VM ^-- VS2 is substantially established. That is, if the center voltage of VD2 and VS2 and VC, VD2 and VS2 are substantially symmetrical with respect to VC, VM ⁺ and VM ^- also substantially symmetric with respect to VC.

VM ⁺ -VM ^- is considerably smaller than VD2-VS2. In the MLS driving described above, both the positive side and negative side selection voltages are always required. On the other hand, in a liquid crystal display device using a two-terminal nonlinear switching element, only one selection voltage VD2 or VS2 is necessary at a certain time, and both selection voltages are required at the same timing. No. FIG. 51 shows an example of a circuit designed with attention paid to this point so that the withstand voltage of the Y driver is about half that of VD2-VS2. At the timing when VD2 is necessary, the transistor 250 is turned on and the transistor 252 is turned off. As a result, VD (t) becomes VD2 that is higher than VM ⁺ , and VS (t) becomes VS1 that is higher than VS2 due to capacitive coupling. When VS2 is necessary, the transistor 252 is turned on and the transistor 250 is turned off. Thus, VS (t) is VM ^- than VS2 becomes a low voltage, VD (t) becomes VD1 is a voltage lower than VD2 by capacitive coupling. When only one of the positive voltage and negative voltage needs to be applied at the same timing, the withstand voltage of the Y driver can be reduced to about half of VD2-VS2 by shaking the power supply voltage applied to the Y driver in this way. It is possible to finish. Hereinafter, the driving method in which the power supply voltage is shaken in this way is referred to as a shaking power supply method. At present, this swaying power supply system is mainly used in liquid crystal panels using a two-terminal nonlinear switching element.

  As described above, the shaking power supply method has the advantage that the withstand voltage of the Y driver is about half that of VD2-VS2, but nevertheless has the disadvantage of extremely increasing the power consumption of the liquid crystal display device. One of the reasons for the increase in power consumption is that all the capacitance parasitic to the Y driver is charged / discharged with a voltage width that is shaken, and that a current flows in the Y driver in a short time at the time when it is shaken. Another cause is that the power consumption of the power supply circuit itself is large, and there is no good method for reducing the power consumption of the power supply circuit itself.

  In summary, the power supply circuit configured as shown in FIGS. 48 and 49 has the following problems.

  (1) The reactive power consumption when supplying the charging / discharging current of the panel is large.

  (2) Since the current consumption in the logic part of the X driver is also supplied from the high voltage VEE, the power consumption further increases.

  (3) Since a high-voltage VEE is used as the power source of the operational amplifier, the power consumption due to the idling current of the operational amplifier that constantly flows from VEE to GND is large.

  (4) A high-priced low-power high-voltage operational amplifier must be used as the operational amplifier used in the power supply circuit.

  Further, the power consumption cannot be reduced even in the power supply circuit / driving system configured as shown in FIG.

  An object of the present invention is to provide a power supply circuit, a liquid crystal display device, and an electronic device that have low power consumption and are inexpensive.

  In order to solve the above-described problems, the present invention is a power supply circuit that is supplied with an input power supply voltage and supplies first to Nth (N ≧ 4) potentials for driving a liquid crystal panel of a liquid crystal display device. A charge pump circuit that performs a charge pump operation based on a clock generated by a pulsed clock including a pulse that is generated automatically and supplies any one of the first to Nth potentials directly or via an adjustment means; , Means for stopping charging of the pumping capacitor included in the charge pump circuit and charging of the backup capacitor by the pumping capacitor during the pulse generation period of the pulsed clock, and a display off control signal of the liquid crystal panel is input If so, the given clock supplied to the charge pump circuit is stopped to stop the charge pump. Characterized in that it comprises a means for stopping the operation.

  According to the present invention, during the pulse generation period of the pulsed clock, charging of the pumping capacitor and the backup capacitor is stopped, thereby preventing charge escape at the transition timing. As the pulsed clock, a latch pulse used for a driver IC is optimal. Further, according to the present invention, display off control can be performed with only a slight increase in the number of elements, and current consumption when display is off can be reduced to almost zero.

  The present invention is also a power supply circuit that is supplied with an input power supply voltage and supplies first to Nth (N ≧ 4) potentials for driving a liquid crystal panel of a liquid crystal display device, and is charged based on a given clock. A charge pump circuit that performs pumping operation and supplies any one of the first to Nth potentials directly or via an adjustment means, charging of a pumping capacitor included in the charge pump circuit, and backup by the pumping capacitor The means for charging the capacitor every horizontal scanning period in driving the liquid crystal panel and the given pump supplied to the charge pump circuit when the display off control signal of the liquid crystal panel is inputted. And a means for stopping the charge pump operation by stopping the clock.

  According to the present invention, it is possible to complete the charge pump operation every horizontal period, thereby effectively preventing display unevenness and the like. Further, according to the present invention, display off control can be performed with only a slight increase in the number of elements, and current consumption when display is off can be reduced to almost zero.

  The present invention also provides the first and Nth potentials when the given clock supplied to the charge pump circuit is stopped when the display off control signal is inputted and the charge pump operation is stopped. And a means for discharging residual charges in a circuit portion to which a voltage is supplied by at least one of the above.

  According to the present invention, it is possible to prevent a situation in which a high voltage is continuously applied to the display element, and to improve reliability.

  The present invention is also a power supply circuit which is supplied with an input power supply voltage and supplies first to Nth (N ≧ 4) potentials for driving a display element, and performs charge pump operation based on a given clock. A charge pump circuit for supplying any one of the first to Nth potentials directly or via adjusting means; charging of a plurality of pumping capacitors included in the charge pump circuit; and backup by a plurality of pumping capacitors Means for charging the capacitor every horizontal scanning period in driving the display element, and charging the first pumping capacitor of the plurality of pumping capacitors in one horizontal period And the electric charge charged in the second pumping capacitor among the plurality of pumping capacitors, Charging a backup capacitor in a horizontal period subsequent to the one horizontal period, and charging the second pumping capacitor with the charge charged in the first pumping capacitor. The charge pump circuit performs a charge pump operation in which a backup capacitor is alternately charged every horizontal period by the plurality of pumping capacitors.

  By charging the backup capacitor alternately every horizontal period with a plurality of pumping capacitors in this way, it becomes possible to complete the charge pump operation every horizontal period, effectively generating display unevenness, etc. Can be prevented.

  The present invention also provides a power supply circuit according to any one of the above, a liquid crystal panel including a liquid crystal layer controlled by a plurality of data line electrodes and a plurality of scanning line electrodes, and a potential supplied by the power supply circuit. A data line driver that controls the data line electrode based on the data line driver; and a scan line driver that controls the scan line electrode based on a potential supplied by the power supply circuit.

  According to the present invention, not only the power consumption of the power supply circuit itself but also the power consumption of the liquid crystal display device can be reduced, and a liquid crystal display device optimal for portable electronic devices and the like can be provided.

  In the liquid crystal display device according to the present invention, the power supply circuit may use any one of the first to Nth potentials as the first input potential on the high potential side and the second input potential on the low potential side included in the input power supply voltage. And a charge pump circuit that performs a charge pump operation based on a given clock and supplies any one of the first to Nth potentials directly or via an adjustment means, The first and second input potentials are used as power supply voltages for at least one of the data line driver and the scanning line driver.

  According to the present invention, the first and second input potentials are used as any of the first to Nth potentials, and are also used as the power supply voltage of the logic unit of the data line driver or the scanning line driver. As a result, it is not necessary to separately supply a power supply voltage for a logic unit such as a data line driver, and convenience for the user of the apparatus can be achieved. In addition, the power consumption of the apparatus can be further reduced.

  According to the present invention, the power supply circuit generates a potential different from the first and second input potentials by a charge pump operation based on a given clock, and the generated potential is any one of the first to Nth potentials. It includes a charge pump circuit supplied as

  According to the present invention, for example, when the potential difference between the power supply voltage of the logic unit and the Gth and Jth potentials (1 <G, J <N) used for driving the liquid crystal is different, the charge pump circuit makes them the same. It becomes possible to adjust so that it becomes. This makes it easier to use the first and second input potentials as the power supply voltage of the logic portion of the driver.

  In the liquid crystal display device according to the present invention, the power supply circuit performs a charge pump operation based on a clock generated by the latch pulse for the data line driver or the shift clock for the scanning line driver, It includes a charge pump circuit that supplies any one of the Nth potentials directly or via adjustment means.

  The latch pulse and the shift clock are pulsed clocks including periodically generated pulses, and are optimal for generating a charge pump circuit clock. Therefore, by using these, it is possible to achieve both maintenance of display quality of the liquid crystal display device and low power consumption.

  The present invention also provides a power supply circuit that is supplied with an input power supply voltage and supplies first to Nth (N ≧ 4) potentials for driving a display element, and is provided on the high potential side included in the input power supply voltage. Means for supplying a first input potential as a Gth potential (1 <G <N) among the first to Nth potentials; and a second input potential on a low potential side included in the input power supply voltage, A means for supplying the first to Nth potentials as a Jth potential (1 <J <N) and a charge pump operation based on a given clock, and the first potential on the high potential side is directly or A charge pump circuit supplied via the adjusting means; and a charge pump circuit that performs charge pump operation based on a given clock and supplies the Nth potential on the low potential side directly or via the adjusting means; It is characterized by including.

  In the case of driving a display element such as a liquid crystal, generally, the current consumption that needs to be supplied by the first potential on the high potential side and the N potential on the low potential side is small, and the G potential and Jth potential are intermediate potentials. There is much current consumption that must be supplied by the potential. According to the present invention, the first and Nth potentials are supplied by a charge pump circuit with low output capability but high efficiency, and the Gth and Jth potentials are supplied by an input power supply voltage having high output capability. . As a result, according to the present invention, both maintenance of display quality and low power consumption can be achieved, and a power supply circuit optimal for a liquid crystal display device aiming at low power consumption can be provided.

  The present invention also provides a charge pump circuit that performs charge pump operation on a potential other than the first, G, J, and N potentials among the first to Nth potentials based on a given clock. It is characterized by being supplied by a given operational amplifier.

  If all potentials other than the first, Gth, Jth, and Nth potentials are supplied by the charge pump circuit, the power consumption can be further reduced. On the other hand, even if an operational amplifier with a high output capability is used to supply these potentials, the present invention has an advantage that the power consumption does not deteriorate so much because the operational voltage of the operational amplifier can be lowered.

  In the present invention, the first to Nth potentials are different from the first input potential, the second input potential, the midpoint potential of the first and second input potentials, and the first and second input potentials. It is characterized in that it is formed symmetrically with respect to either the generated potential when the potential is generated or the midpoint potential of the first or second input potential.

  That is, according to the present invention, the first to Nth potentials are symmetrical with respect to the first input potential, symmetrically with respect to the second input potential, or with respect to the midpoint potential of the first and second input potentials. Or symmetrically with respect to the midpoint potential of the generated potential and the first or second input potential.

  According to the present invention, a potential different from the first and second input potentials is generated based on either the first or second input potential, and the generated potential is set to any one of the Gth and Jth potentials. Features.

  For example, consider a case where the required potential difference between the Gth and Jth potentials is larger than the potential difference between the first and second input potentials. In this case, according to the present invention, for example, the Gth and Jth potentials having a desired potential difference can be obtained by generating a higher potential from the first input potential. As a result, the logic voltage can be lowered.

  The present invention is also a power supply circuit which is supplied with an input power supply voltage and supplies first to Nth (N ≧ 4) potentials for driving a display element, and is K times (K ≧ K) based on a given clock. 2) A charge pump circuit that performs a boosting charge pump operation and supplies any one of the first to Nth potentials directly or via an adjusting means, and L / M times (provided that a given clock is used) (L / M is not an integer) including a charge pump circuit that performs a charge pump operation of step-down or M / L double step-up and supplies any one of the first to Nth potentials directly or via an adjustment means It is characterized by that.

  According to the present invention, it is possible to realize a power supply circuit in which, for example, a 6-fold booster circuit and a 1 / 3-fold buck circuit are mixed. As a result, various voltage groups required for driving the display element can be supplied with low power consumption.

  The present invention is also a power supply circuit which is supplied with an input power supply voltage and supplies first to Nth (N ≧ 4) potentials for driving a display element, and is K times (K ≧ K) based on a given clock. 2) Charge pump operation of step-up or L / M times (where L / M is not an integer) step-down or M / L times step-up is performed, and any one of the first to Nth potentials is directly or via an adjustment means. And a charge pump circuit for supplying the charge pump circuit, and means for changing the step-up or step-down ratio of the charge pump circuit.

  According to the present invention, the step-up or step-down ratio performed by the charge pump circuit can be changed. For example, a 6-fold boost circuit can be changed to a 5-fold boost circuit. For example, by changing the step-up magnification according to the characteristics of the display element and the value of the input power supply voltage, various necessary drive voltage groups can be formed. Note that it is desirable that the step-up / step-down magnification can be changed using an external terminal or the like.

  The present invention is also a power supply circuit which is supplied with an input power supply voltage and supplies first to Nth (N ≧ 4) potentials for driving a display element, and performs charge pump operation based on a given clock. A charge pump circuit for supplying the first potential on the high potential side or the Nth potential on the low potential side directly or via the adjusting means, and a given period after the input power supply voltage is applied, And a means for stopping the supply of the first potential or the Nth potential by a charge pump circuit.

  According to the present invention, it is possible to start supplying the first or Nth potential after a given period has elapsed after the input power supply voltage is turned on and the control circuit or the like operates normally. As a result, the system can be started up normally.

  The present invention also provides a power supply circuit that is supplied with an input power supply voltage and supplies first to Nth (N ≧ 4) potentials for driving a display element, and is provided on the high potential side included in the input power supply voltage. Means for supplying a first input potential as a Gth potential (1 <G <N) among the first to Nth potentials; and a second input potential on a low potential side included in the input power supply voltage, Means for supplying as a Jth potential (1 <J <N) of the first to Nth potentials, and is included in the input power supply voltage and is on a higher potential side or a lower potential side than the first and second input potentials. Means for supplying a third input potential as either the first potential on the high potential side or the Nth potential on the low potential side; and a charge pumping operation based on a given clock; A charge pump circuit that supplies any of the N potentials directly or via a regulating means, and a given Charge pump operation based on the lock, and supply the F-th potential (1 <F <N) higher or lower than the G-th and J-th potentials directly or via adjustment means A charge circuit that includes a pump circuit and charges and pumps potentials other than the first, F, G, J, and N potentials among the first to N potentials based on a given clock; -It is supplied by a pump circuit.

  According to the present invention, the first to Nth potentials can be supplied by a circuit and means having an output capability corresponding to a required current consumption, and both maintenance of display quality and low power consumption can be achieved.

  The present invention is also a power supply circuit which is supplied with an input power supply voltage and supplies first to Nth (N ≧ 4) potentials for driving a display element, and performs charge pump operation based on a given clock. A charge pump circuit for supplying any one of the first to N-th potentials directly or via an adjustment means, and a supply stop of the input power supply voltage, a supply stop of the given clock, or a display-off control signal. And a means for discharging residual charges of a circuit portion to which a voltage is supplied by at least one of the first and Nth potentials when at least one of the inputs is made.

  According to the present invention, it is possible to prevent a situation in which a high voltage is continuously applied to the display element, and to improve reliability.

  The electronic apparatus according to the present invention includes the liquid crystal display device.

  According to the present invention, not only a liquid crystal display device but also an electronic device including the liquid crystal display device can be reduced in power consumption. This makes it possible to extend the battery life of electronic devices such as portable information devices.

  Embodiments of the present invention will be described below with reference to the drawings. Note that the description will be made assuming that the GND potential is 0 V for convenience unless otherwise noted.

[Example 1]
FIG. 1 is a block diagram of a power supply circuit according to the first embodiment. This power supply circuit has a function of generating the same output voltage as the power supply circuit of FIG.

  The input power supply voltage of this power supply circuit is only Vcc (first input potential) and GND (second input potential) and is a single power supply input. A latch pulse LP composed of pulses generated every horizontal scanning period is input. The clock forming circuit 1 forms several clock signals having different timings necessary for the charge pump circuit based on LP, and uses Vcc and GND as power sources. The negative-direction 6-fold booster circuit 2 generates a voltage VEE obtained by boosting GND 6 times in the negative direction with reference to Vcc by a charge pump operation. When Vcc is 3.3V, VEE becomes -16.5V. The contrast adjustment circuit 3 generates a selection voltage VL that provides an optimum contrast based on VEE. This VL becomes the negative side selection voltage of the Y electrode. The double booster circuit 4 generates a positive selection voltage VH obtained by boosting GND twice with reference to VL by a charge pump operation. The negative direction double boosting circuit 5 generates -V3, which is a voltage obtained by boosting GND twice in the negative direction with reference to Vcc, by a charge pump operation. The 1/2 step-down circuits 6 and 7 generate V2 which is a voltage obtained by dividing Vcc-GND into two and -V2 which is a voltage obtained by dividing GND-(-V3) by two by a charge pump operation. As the central potential VC, GND is used as it is. Further, Vcc is used as it is for V3 which is a potential symmetrical to −V3 with respect to GND. Thus, the voltage for driving the liquid crystal panel was formed. In this power supply circuit, the output voltages VH, V3, V2, VC, -V2, -V3, and VL are symmetric with respect to GND (second input potential). The circuit 8 forms a voltage higher than V L by Vcc and supplies this as the logic voltage VDDy of the Y driver. Since VDDy itself is not directly applied to the panel, it is not subject to voltage symmetry.

  The present embodiment described above has the following structural features.

  (1) In this embodiment, the first input potential Vcc on the high potential side and the second input potential GND on the low potential side included in the input power supply voltage are set to the first among the first to Nth potentials (N ≧ 4). The G potential V3 and the J potential VC are used as they are. Further, charge pump operation is performed based on a given clock, and the first potential VH on the high potential side and the Nth potential VL on the low potential side are supplied directly or via the adjusting means (contrast adjusting circuit 3) 2 A double booster circuit 4 and a negative direction 6-fold booster circuit 2 are included.

  As described in the background art, most of the current consumption of the liquid crystal panel itself flows between the non-selection voltage VC of the Y electrode and the drive voltages V3, V2, -V2, and -V3 of the X electrode. . For example, in the case of 1/240 duty, there are only four Y electrodes in the selected state, while the remaining 236 lines are all in the non-selected state. In this embodiment, paying attention to this point, the first potential VH and the Nth potential VL are supplied by a high-efficiency charge pump circuit with low output capability (current supply capability), and the Gth potential which is an intermediate potential. Input power supply voltages Vcc and GND having high output capability are connected to V3 and the J-th potential VC. By doing in this way, both maintenance of display quality and low power consumption can be achieved. On the other hand, the power supply circuit of FIG. 49 has a configuration in which all current flows between the first potential VEE and the Nth potential GND. Therefore, the circuit forming the VEE must have high output capability. Therefore, it is almost impossible to supply VEE with a charge pump circuit, and it is impossible to achieve both maintenance of display quality and low power consumption.

  (2) In this embodiment, the potentials V2, -V2, and -V3 other than the first, G, J, and N potentials among the first to Nth potentials are charged based on a given clock. The voltage is supplied by the 1/2 step-down circuits 6 and 7 that perform the pump operation and the negative-direction double step-up circuit 5. Thus, V2, -V2, and -V3 are also supplied by the charge pump circuit, thereby further reducing power consumption. In addition, according to the present embodiment, since the clock required for the charge pump operation can be shared between the charge pump circuits, the control is easy and the increase in the circuit scale can be minimized.

  FIG. 2 shows a block diagram when V2 and -V2 are supplied by operational amplifiers OP1 and OP2. R1 and R3 are bleeder resistors for dividing the voltage between V3 and VC (GND), and R2 and R4 are bleeder resistors for dividing the voltage between VC and -V3. OP1 and OP2 are operational amplifiers for outputting the voltage divided by the bleeder resistance with low impedance. R11 and R12 are resistors for limiting the output currents of OP1 and OP2 to stabilize the operation and reducing power consumption. C1 to C4 are smoothing capacitors for suppressing fluctuations in V2 and -V2. It is. OP1 operates with V3 and VC as power sources, and OP2 operates with VC and -V3 as power sources. C1 may be arranged between V3 and VC, and C4 may be arranged between VC and -V3. Thus, even if V2 and -V2 are supplied by the operational amplifiers OP1 and OP2, the OP1 and OP2 operate with a small power supply voltage unlike the power supply circuit of FIG. 49, so that the power consumption of this portion is kept within an allowable range. be able to.

  (3) In the present embodiment, a charge pump operation of K times (K ≧ 2) boosting is performed based on a given clock, and any one of the first to Nth potentials is directly or adjusting means (contrast adjusting circuit) 3) Negative direction 6 × booster circuit 2, 2 × booster circuit 4, negative direction 2 × booster circuit 5, and L / M times (where L / M is not an integer) step-down based on a given clock Alternatively, it includes ½ step-down circuits 6 and 7 that perform a charge pump operation of M / L times and supply any one of the first to Nth potentials directly or via adjustment means. As described above, in this embodiment, the charge pump circuit that performs K-fold voltage boosting and the charge pump circuit that performs L / M-fold voltage buck and the like are mixed. As a result, various voltages can be supplied from the single input power supply (Vcc, GND) with low power consumption.

  Next, the contrast adjustment circuit 3 will be described with reference to FIG. The contrast adjustment circuit 3 includes a fixed resistor Rfix and a variable resistor Rvol inserted in series connection between GND and VEE, a bipolar transistor Tr, and a capacitor CVL. In the liquid crystal display device driven by the power supply circuit of this embodiment, since the current flowing through the output voltage VL is small, the base current of Tr can be small. As a result, Rfix and Rvol may be as high as 500 KΩ to 1 MΩ, and power consumption by this resistance can be suppressed to about 0.2 mW to 0.4 mW.

  In FIG. 1, the contrast adjustment circuit 3 is provided only on the VL side. However, it may be provided only on the VH side or on both the VH side and the VL side. In FIG. 1, the contrast adjustment circuit 3 is provided only on one side, and VH is generated by the double booster circuit 4 based on the voltage VL obtained by the contrast adjustment circuit 3. This configuration has an advantage that VH can be automatically adjusted by adjusting VL by the contrast adjusting circuit 3. On the other hand, the configuration in which the contrast adjustment circuit 3 is provided on both sides of VH and VL has an advantage that VH and VL can be adjusted independently. Nonlinear switching elements such as MIM have the characteristic that the ease of current flow differs depending on the direction in which the voltage is applied. Therefore, in a liquid crystal display device using MIM or the like, it may be preferable to lower | VH | by about 0.5 V with respect to | VL |. Therefore, in such a case, it is desirable to provide contrast adjustment circuits on both the VH side and the VL side. Specifically, a diode or the like may be included in the contrast adjustment circuit on the VH side, and VH may be stepped down using the forward voltage of this diode.

  In FIG. 1, the 1/2 step-down circuits 6 and 7 are provided to obtain a voltage of 7 levels. However, if the desired voltage is 5 levels, the 1/2 step-down circuits 6 and 7 may be omitted. .

  According to the present embodiment having the above configuration, the power consumption of the liquid crystal display device driven by the 4-line simultaneous selection method can be reduced for the following reason.

  The first reason is that the power consumption due to the charging / discharging current of the panel is ultimately reduced. Consider the charge / discharge current that occupies most of the panel current, that is, the charge / discharge current flowing between the X electrode and the non-selected Y electrode. The charge / discharge currents flowing between the X electrode voltages V3, -V3, V2, and -V2 and the Y electrode voltage VC are IP3, IM3, IP2, and IM2, respectively. Then, the power consumption by IP3 is Vcc × IP3. Further, since the charge pump circuit is extremely efficient, the power consumption by IM3 is almost Vcc × IM3, and the power consumption by IP2 and IM2 is also almost (1/2) × Vcc × IP2, (1/2) × Vcc, respectively. XIM2. On the other hand, in the background example of FIG. 49, when the high voltage is VEE, the power consumption by these currents is VEE × IP3, VEE × IM3, VEE × IP2, and VEE × IM2. Since VEE is about 25V and Vcc is about 3.3V, power consumption by IP3 and IM3 is 1/7 or less of the background example, and power consumption by IP2 and IM2 is 1/14 or less.

  Next, consider the charge / discharge current flowing between the X electrode and the selected Y electrode. Charge / discharge currents flowing between the voltages VH and VL of the Y electrode and the X electrode are IVH and IVL, respectively. Then, due to the high efficiency of the charge pump circuit, the power consumption by IVH and IVL is approximately 5 × Vcc × IVH and 5 × Vcc × IVL, respectively, which is smaller than the power consumption of the background example.

  The second reason is that the power consumption in the logic part of the X driver that operates at high speed and consumes a large amount of current is reduced. As described above, in the power supply circuit of the background example, since the consumption current in the logic unit of the X driver is supplied from the high voltage VEE, the power consumption becomes VEE × consumption current. On the other hand, in this embodiment, the power consumption is Vcc × current consumption, which is 1/7 or less of the background example.

  The third reason is that the power consumption of the booster circuit that forms the high voltage VEE is small. Generally, a charge pump type booster circuit has a small boosting capability, and when a large current is taken out, the output voltage is lowered. In the liquid crystal display device driven by the power supply circuit of the background example, the current of the high voltage system is large, so that the charge pump type booster circuit is insufficient to form the VEE. Therefore, in the background example, a switching regulator type DC-DC converter that rectifies a high voltage generated when the current flowing through the coil is interrupted to form a high voltage VEE is used. The efficiency of the DC-DC converter of the switching regulator type is 5V input, usually about 80%, and 3.3V input is about 60% very low. For this reason, the power consumption of the liquid crystal display device driven by the power supply circuit of the background example is very large, including the booster circuit that forms the VEE. On the other hand, the liquid crystal display device driven by the power supply circuit of this embodiment has a small high voltage system current. Therefore, the high voltage VEE can be supplied by a charge pump type booster circuit having a small output capability but a high efficiency, and power consumption including the booster circuit forming the VEE can be greatly reduced.

  The above is the reason why the power consumption of the liquid crystal display device can be reduced by the power supply circuit of this embodiment. Actually, when driving a two-screen liquid crystal display device having a dot number of 640 × 480 and a dot pitch of 0.2 mm with the power supply circuit of the system shown in FIG. 1, a typical power consumption is about 12 mW as expected. Value.

  In the case where the power supply circuit of this embodiment is made into an IC, the VL can be formed by incorporating an operational amplifier type regulator in the IC, instead of the above-described system using an external bipolar transistor. In order to reduce the withstand voltage of the IC, it is also practical to integrate a transistor for switching VH-GND among the elements constituting the double booster circuit 4 for VH formation, and to integrate the other transistors into one chip. Means.

  In the power supply circuit of this embodiment, most of the configuration is formed by the charge pump circuit, which gives an impression that a large number of capacitors are required. However, in practice, it is possible to omit a part of the backup capacitor included in the charge pump circuit or to use a capacitor having a small capacitance value of about 0.1 μF. This is presumably because the capacitance of the liquid crystal panel itself acts as a backup capacitor.

[Example 2]
The second embodiment is an embodiment relating to the clock forming circuit 1 of FIG. 1, FIG. 4 shows an example of its configuration, and FIG. 5 is a timing chart for explaining its operation. This entire circuit operates in a Vcc-GND system. Further, a latch pulse LP including a pulse generated every horizontal scanning period (1H) is used as the basic clock signal. In the D type flip-flop DF, the / Q output is connected to the write data input D, and thus toggles at the rising edge of LP. The NOR circuits Nor1 and Nor2 are for forming the two-phase clock signals A and B, and the inverter circuits Inv1, Inv2 and Inv3 are the signals / A, / B and Doff are formed.

(1) Pulsed clock In this embodiment, a charge pump circuit (in the negative direction of FIG. 1) is generated based on a clock generated by a pulsed clock LP including periodically generated pulses (P1, P2, etc. in FIG. 5). The charge pumping operation is performed by the 6 × booster circuit 2 or the like. The charging of the pumping capacitor included in the charge pump circuit and the charging of the backup capacitor by the pumping capacitor are stopped during the pulse generation period of the pulsed clock LP. That is, as indicated by Tp in FIG. 5, both the signal A and the signal B are set to the low level during the LP pulse generation period (the period when the LP is at the high level). When the signals A and B are at a low level, all the switch groups (transistor groups) forming the charge pump circuit are turned off, thereby preventing charge escape at the transition timing.

  However, if the switch group off time at this transition timing is too long (the Tp period is too long), the time required to charge the pumping capacitor and the backup capacitor is shortened. Disappear. Since LP is a pulsed clock having a pulse width of usually about 100 ns to 300 ns and a period of about several tens of μs to 100 μs, it is convenient as a basic clock for this circuit. Further, since charging / discharging of the panel occurs in one horizontal scanning (1H) cycle, it is reasonable to charge the panel driving voltage in 1H cycle using LP. Although it is possible to internally generate a basic clock with a CR oscillator circuit etc. without inputting LP, the circuit becomes simpler if the latch pulse input to the driver IC is also diverted to the basic clock of this power supply circuit. preferable.

  The pulsed clock used in this embodiment is not limited to LP, which is a latch pulse for the X driver, and for example, a shift clock YSCL for the Y driver may be used. When a pulse clock is not used, a period Tp for turning off the switch group may be created using a delay circuit or the like.

(2) Clock Stop Function In this embodiment, while the display-off control signal / Doff is at a low level, the signal A and the signal B are both set at a low level so that the operation of the charge pump circuit is stopped. That is, the power supply circuit has a function of stopping the clock supplied to the charge pump circuit. By adding this function, the power consumption of the power supply circuit during display off control can be made substantially zero. Further, since the output of the selection voltage is stopped at the same time, even if a Y driver without a display off control function is used, the liquid crystal display device as a whole can have a display off control function. In the example of FIG. 4, in consideration of testability when the power supply circuit is integrated into an IC, the generation of the clock is stopped by resetting DF, and the operation of the charge pump circuit is stopped. However, the operation of the charge pump circuit can also be stopped by using a method in which LP and / Doff are input to a given AND circuit and the obtained signal is used as a new basic clock.

Example 3
The third embodiment relates to a charge pump circuit such as the negative-direction six-fold booster circuit 2 and the two-fold booster circuit 4 shown in FIG.

(1) Basic Concept FIG. 6 is the most basic conceptual diagram of the charge pump circuit. In FIG. 6, SWa and SWb are interlocking switches, and while one of them is tilted to the A side, the other is also tilted to the A side. In FIG. 6, SWa and SWb are represented by mechanical switches. Actually, the switches SWa and SWb control the conduction / cutoff between the MOS transistor for controlling conduction / cutoff with the A side and the conduction / cutoff with the B side. Usually, it can be composed of two MOS transistors.

  While SWa and SWb are switched to the A side, the pumping capacitor Cp is charged with a voltage of Vb−Va. Next, when SWa and SWb are switched to the B side, the electric charge charged in Cp is transferred to the backup capacitor Cb. By repeating this switching operation, the voltage applied to Cb, that is, the voltage between Ve and Vd approaches a value substantially equal to the voltage between Vb and Va. At this time, when Vd is a certain voltage, a voltage higher than Vd by Vb−Va is generated at Ve. Conversely, when Ve is a certain voltage, a voltage lower than Ve by Vb−Va is generated in Vd. The above is the basic operation of the charge pump circuit. As will be described below, this circuit functions as a step-up circuit or a step-down circuit depending on where Va, Vb, Vd, and Ve are connected.

(2) Double Boosting FIG. 7 is a conceptual diagram of a double boosting charge pump circuit in which Vd is connected to Vb in FIG. That is, for the reason described above, Ve−Vd = Ve−Vb = Vb−Va because SWa and SWb repeat the interlocking switching operation, so Ve−Va = (Ve−Vb) + (Vb−Va) = 2. X (Vb−Va) is established. That is, when Va is a reference level of potential (0 V), Ve = 2 × Vb, and Ve is a voltage obtained by boosting Vb twice.

(3) Negative direction double boosting FIG. 8 is a schematic diagram of the charge pump circuit for negative direction double boosting in which Ve is connected to Va in FIG. Since SWa and SWb repeat the interlocking switching operation, Ve−Vd = Va−Vd = Vb−Va, so that Vb−Vd = (Vb−Va) + (Va−Vd) = 2 × (Vb−Va) To establish. That is, when Vb is set to a reference level (0 V) of potential, Vd = 2 × Va, and Vd is a voltage obtained by boosting Va in the negative direction twice.

(4) 1/2 step-down FIG. 9 is a conceptual diagram of a 1/2 step-down charge pump circuit in which the input voltage is changed from Vb-Va to Vb-Vd in FIG. Ve is the output voltage, and the current consumed by the load connected to Ve is supplied from the backup capacitor Cb. First, when SWa and SWb are electrically connected to the B side, Cp and Cb are connected in parallel, so the voltages applied to Cp and Cb are equal. Next, when SWa and SWb are switched to the A side, Cp and Cb connected in series enter between input voltages Vb and Vd, and the voltage applied to Cp and Cb becomes half of the input voltage. Next, when SWa and SWb are switched again to the B side, Cp and Cb are connected in parallel, so the charge stored in Cp is supplied to Cb, and the voltage applied to Cp is equal to the voltage applied to Cb. Therefore, if the charge that can be stored in Cp and Cb is sufficiently larger than the charge carried away by the load current of Ve, SWa and SWb repeat the interlocking switching operation, and Ve has 1 / of the input voltage. An output voltage close to 2 will be generated.

(5) Negative direction 6-fold boosting FIG. 10 is a conceptual diagram showing an example of a negative-direction 6-fold boosting charge pump circuit. FIGS. 11A and 11B respectively show SWa1 to SWa3 and SWa1 to SWa3. It is a connection relation figure when SWb1-SWb3 is switched to the A side and the B side. SWa1 to SWa3 and SWb1 to SWb3 are interlocking switches, Cp1 to Cp3 are pumping capacitors, and Cb1 and Cb23 are backup capacitors.

  By the same operation as the above-described negative direction double boosting circuit, −2 × (Vcc−GND), which is a voltage obtained by boosting GND twice in the negative direction with respect to Vcc, is generated in −V3B. When all the switches are switched to the A side, as shown in FIG. 11A, Cp2 and Cp3 are connected in parallel, so that Cp2 and Cp3 are approximately 2 × (Vcc−GND) respectively. It will be charged.

  Next, when all switches are switched to the B side, Cp2 and Cp3 connected in series are connected in parallel to Cb23 as shown in FIG. 11B. Cp2 and Cp3 are charged at 2 × (Vcc−GND) as described above. Accordingly, a voltage of 4 × (Vcc−GND) is generated between −V3B and VEE, and Cb23 is charged with this voltage. For the above reasons, when all the switches repeat the interlock switching operation, a voltage obtained by boosting GND six times in the negative direction with respect to Vcc, that is, Vcc-6 × (Vcc-GND) is generated in VEE. For example, when Vcc = 3V, a voltage of −3V is generated at −V3B and −15V is generated at VEE.

  FIG. 12 is a conceptual diagram showing another example of a negative-direction 6-fold boosting charge pump circuit. FIGS. 13A and 13B show that SWa1 to SWa3 and SWb1 and SWb23 are on the A side, respectively. It is a connection relation figure at the time of switching to the B side. Cp1 to Cp3 are pumping capacitors, and Cb1 to Cb3 are backup capacitors.

  Similar to the circuit of FIG. 10, −2 × (Vcc−GND), which is a voltage obtained by boosting GND twice in the negative direction with respect to Vcc, is generated in −V3B. When all the switches are switched to the A side, as shown in FIG. 13A, Cp2 is charged with a voltage of approximately 2 × (Vcc−GND). As shown in FIG. 12, the circuit composed of Cp2, Cb2, SWb23, and SWa2 is a negative double boosting circuit, similarly to the circuit composed of Cp1, Cb1, SWb1, and SWa1. Therefore, Cb2 is also charged with a voltage of 2 × (Vcc−GND), and a voltage of −4 × (Vcc−GND) is generated in VEM. As a result, Cp3 is charged with a voltage of 4 × (Vcc−GND).

  Next, when all the switches are switched to the B side, as shown in FIG. 13B, a connection relationship in which CP3 is inserted between −V3B and VEE is established. The voltage of −V3B is −2 × (Vcc−GND), and Cp3 is charged with a voltage of 4 × (Vcc−GND). Therefore, a voltage obtained by boosting GND six times in the negative direction with respect to Vcc, that is, a voltage of Vcc-6 × (Vcc-GND) is eventually generated in VEE.

  Unlike the circuit of FIG. 12, the circuit of FIG. 10 does not require VEM, which is a stable voltage between −V3B and VEE, and therefore requires one less capacitor than the circuit of FIG. There are advantages. On the other hand, the circuit shown in FIG. 12 uses the switch connected to the positive electrodes of Cp2 and Cp3 in common, so that the number of switches required (one as the number of transistors) may be less than that of the circuit shown in FIG. There is. Further, by forming the intermediate voltage VEM, the drain withstand voltage of the transistor may be lower than that of the circuit of FIG. 10, and there is an advantage that the size of the transistor can be reduced.

(6) 3/2 Boosting FIGS. 14A and 14B are conceptual diagrams of a charge pump circuit for 3/2 boosting. CpH and CpL are pumping capacitors, and Cb is a backup capacitor. As shown in FIGS. 14A and 14B, in this circuit, the state in which CpH, CpL, and Cb are connected in series and the state in which Cb, CpH, and CpL are connected in parallel are alternated. Repeated. When the voltages applied to CpH and CpL are expressed as VcpH and VcpL, respectively, since CpH and CpL are connected in parallel in FIG. 14B, VcpH = VcpL. Further, as shown in FIG. 14A, when CpH and CpL are connected in series between Vcc and GND, CpH and CpL are charged with a voltage of 1/2 of Vcc. After that, when the connection state shown in FIG. 14B is reached, the charges stored in CpH and CpL are supplied to Cb. By repeating this operation many times, the voltages applied to Cb, CpH, and CpL all approach ½ of Vcc, and as a result, a voltage obtained by boosting Vcc to 3/2 times is generated in the output voltage. To do.

(7) Negative direction 3 / 2-fold voltage boosting FIGS. 15A and 15B are conceptual diagrams of a negative direction 3 / 2-fold voltage boosting charge pump circuit. Since the operating principle is the same as that of the above-mentioned 3/2 times boosting, detailed description is omitted. As in the case of 3/2 times boosting, the pumping capacitors CpH and CpL are connected in series with the backup capacitor Cb, and the state of FIG. 15A and Cb, CpH and CpL are connected in parallel. By alternately repeating the state of FIG. 15B, it is possible to obtain a boosted voltage −3 / 2 × Vcc in the direction opposite to the above 3 / 2-fold boost. A driver IC of a liquid crystal display device often requires a logic voltage and a voltage on the negative side of the logic voltage. By applying this circuit to such a liquid crystal display device, the low-voltage of the liquid crystal display device can be obtained. Power consumption can be reduced.

(8) 2 / 3-times Step-Down Voltage FIGS. 16A and 16B are conceptual diagrams of a 2 / 3-times step-down charge pump circuit. Also in this circuit, the pumping capacitors CpH and CpL are connected in series with the backup capacitor Cb in FIG. 16A, and Cb, CpH and CpL are connected in parallel in FIG. 16B. The state is repeated alternately. The voltages applied to Cb, CpH, and CpL are all the same because they are connected in parallel in FIG. 16B, and when connected in series as shown in FIG. A voltage of approximately 1/3 of Vcc is charged. By repeating this operation many times, the voltages applied to Cb, CpH, and CpL all approach about 1/3 of Vcc, and as a result, the output has a voltage that is (1/3) × Vcc lower than Vcc. That is, a voltage is generated by reducing Vcc by 2/3.

(9) Negative direction 2/3 times step-down FIG. 17A and FIG. 17B are conceptual diagrams of negative direction 2/3 times step-down charge pump circuits. Since the operation principle is the same as that of the above 2/3 times step-down, detailed description is omitted. As in the case of 2/3 step-down, CpH and CpL are connected in series with the backup capacitor Cb, and the state shown in FIG. 17A is connected in parallel with Cb, CpH, and CpL. By alternately repeating the state of B), it is possible to obtain a step-down voltage −2 / 3 × Vcc in the direction opposite to that in the case of step-down by 2/3.

(10) Specific Example of Charge Pump Circuit FIG. 18 shows an example in which the basic part of the negative-direction double boosting charge pump circuit shown in FIG. 8 is configured with individual components (configured with discrete components). . Vx is an input voltage, Vy is an output voltage, and Vx> 0. At timing T1 (see FIG. 19), the PMOS transistors Trp1 and Trp2 are turned on, and the pumping capacitor Cp is charged with the voltage of Vx-GND. At this time, the N-MOS transistors Trn1 and Trn2 are off. At the next timing T2, Trp1 and Trp2 are turned off and Trn1 and Trn2 are turned on to transfer the charge charged in the pumping capacitor Cp to the backup capacitor Cb. If the source electrode of Trn1 is connected to GND as shown in FIG. 18, a voltage symmetrical to Vx with respect to GND is generated in the output Vy by alternately repeating the operations at the timings T1 and T2.

  In FIG. 18, signals / A1, / A2, B, and B2 entering the gate of the transistor are, for example, phase and voltage signals as shown in FIG. If the level of these signals is not between VC and GND, means for level shifting the signals is required. A simple level shift method in the case of using individual parts is a method using a coupling capacitor Cs and a diode D as shown in FIGS. 20 (A) and 20 (B). The capacitance of the coupling capacitor Cs may be about 470 pF. With the connection shown in FIG. 20A, a gate signal / Ax having the same phase and the same amplitude as the signal / A and capable of turning on / off the PMOS transistor Trp can be obtained. 20B, the gate signal Bx having the same phase and the same amplitude as the signal B and capable of turning on / off the NMOS transistor Trn can be obtained. Rp is a resistance of several MΩ, and functions to compensate for the leakage current of the diode and stabilize the voltage of the gate signal.

  The above describes the case where the charge pump circuit is configured using individual components. On the other hand, when the charge pump circuit is formed as a monolithic IC, a known configuration / means more suitable for the monolithic IC may be adopted as the transistor configuration and level shift means of the charge pump circuit.

(11) Charge Pump Circuit Using Diode FIG. 21 shows a configuration example of a charge pump circuit when diodes D1 and D2 are used as switching elements instead of transistors. V1 is a stable input voltage, and Vx is a clock having a high drive capability with an amplitude voltage of Vp. According to this circuit, when the forward voltage of the diode is about 0.6 V, the output voltage V2 = V1− (clock amplitude voltage Vp−about 0.6 V) can be efficiently generated.

  Next, the operation will be described with reference to the timing chart of FIG. In order to simplify the description, the forward voltage of the diodes D1 and D2 is assumed to be 0V. In the period Tc, Vx = Va, and since D1 is a forward bias, Vd = V1. Therefore, the capacitor Cp is charged with a voltage of V1-Va. In the period Td, the level of Vd is pulled by Cp and falls by Vp, which is the voltage drop of Vx. As a result, current flows through the route of V1, Cb, D2, Cp, and Vx, and Cb is charged. By repeating the operations in the above periods Tc and Td, the output voltage V2 = V1−Vp can be obtained.

  As shown in FIG. 23, when the circuit of FIG. 21 is stacked in two stages, a voltage of V1-2 × (Vp−about 0.6 V) can be obtained as V3. Similarly, if three stages are stacked, a voltage of V1-3 × (Vp−about 0.6 V) can be obtained.

  As described above, as the charge pump circuit of the present invention, various devices such as a device using a diode as well as a device using a transistor can be adopted.

Example 4
The fourth embodiment relates to a technique for increasing the output capability (current supply capability) of the charge pump circuit. Basically, the output capability can be increased by lowering the on-resistance of the transistors forming the charge pump circuit and increasing the capacitance value of the capacitor. However, there are cases where other methods are more efficient. As one of the methods, a method of preparing a plurality of pumping capacitors and charging a backup capacitor alternately with the plurality of pumping capacitors is conceivable. As another method, it is possible to add a circuit for doubling the LP frequency and perform a charge operation and a pump operation every half cycle of the LP. For example, -V3 in FIG. 1 causes a double voltage drop due to the current consumed by the circuit portion connected to -V3 and the current consumed by the circuit portion connected to -V2. Therefore, it is desirable that the charge pump circuit for supplying -V3 has a large output capability by the various methods described above.

  FIG. 24 shows a circuit example in which a plurality of pumping capacitors Cp1 and Cp2 are provided to increase the output capability. Here, as in FIG. 18, an example in which a circuit is configured with individual components is shown.

  Signals A, / A, B, and / B are signals formed by the clock forming circuit described with reference to FIG. 4, and Vx is an input voltage. A period in which A is at a high level is T1, and a period in which B is at a high level is T2. During the period T1, Trn1, Trn2, Trp3, and Trp4 are off, and Trp1 and Trp2 are on. Thereby, Cp1 is charged with the voltage Vx. Since Trn3 and Trn4 are also on, the charge previously charged in Cp2 moves to Cb. Next, in the period T2, Trp1, Trp2, Trn3, and Trn4 are off, and Trp3 and Trp4 are on. Thereby, Cp2 is charged with the voltage Vx. Since Trn1 and Trn2 are also on, the charge previously charged in Cp1 moves to Cb. In this way, by supplying the charge to Cb alternately by the two charge pump capacitors Cp1 and Cp2, a charge pump circuit with higher output voltage smoothness and higher output capability can be realized.

  Note that the portion indicated by H in FIG. 24 is a level shift means for forming a signal having a voltage and phase necessary for driving the gates of the transistors Trp2, Trp4, Trn2, and Trn4 from the signals A and / B. It is. Cs1 and Cs2 are coupling capacitors having a capacitance of about 470 pF, D1 and D2 are diodes, Inv3 to 6 are inverters, and Rf1 and Rf2 are resistors of about 1 KΩ. Inv3, Inv4, and Rf1 form one hold circuit, and Inv5, Inv6, and Rf2 form another hold circuit. When the positive power supply terminals of Inv3-6 are connected to GND as shown in FIG. 24, a voltage lower than GND by Vx is generated at the negative power supply terminals of Inv3-6. In-phase / anti-phase signals having the same amplitude as B are obtained from the outputs of Inv3-6. It is preferable to insert a smoothing capacitor Cx of about 0.1 μF between the power terminals of Inv 3 to 6. This level shift means has an advantage that the decrease in amplitude of the signal is smaller than the level shift means described with reference to FIGS. 20 (A) and 20 (B).

  In this embodiment, a plurality of pumping capacitors are prepared in order to improve the output capability, but this method is also effective in improving display quality. For example, according to the method using the latch pulse LP, as shown in FIG. 25A, charging of the pump capacitor Cp (charging operation) and charging of the back-up capacitor Cb by Cp (pumping operation) are performed in two horizontal scans. This is repeated every period (2H). When the charge pump circuit having such a configuration is used in, for example, the negative-direction double booster circuit 5 of FIG. 1, there is a possibility that uneven display of horizontal stripes with a period of 8 lines (dark 4 lines + light 4 lines) may occur. This is because the negative direction double booster circuit 5 supplies current consumed by both −V2 and −V3, and −V2 and −V3 consume more current than VH and VL. . Therefore, if the negative direction double booster circuit 5 is configured to have a plurality of pumping capacitors as shown in FIG. 24, the occurrence of display unevenness as described above can be effectively prevented. The reason is that in this way, as shown in FIG. 25B, charging of Cp1 or Cp2 and charging of Cb by Cp2 or charging of Cb by Cp1 are performed every horizontal period. .

  In order to prevent the occurrence of display unevenness as described above, at least charging of the pumping capacitor and charging of the backup capacitor by the pumping capacitor may be performed every horizontal period. Therefore, for example, if the charge pump operation is performed as shown in FIG. 25C using a signal having a frequency twice that of the latch pulse LP, the display unevenness can be prevented.

Example 5
The fifth embodiment relates to a change in the step-up magnification and step-down magnification of the charge pump circuit. In the negative direction 6-fold booster circuit described with reference to FIGS. 10 and 12, the boost magnification is fixed to 6 times. The reason why the boosting factor is 6 times is that in a liquid crystal display device with a duty of 1/240, when Vcc drops to 3 V, VEE is insufficient in the negative direction 5 times boosting voltage (that is, VEE = −12 V). This is because about 13.5V is required. VEE required for the same liquid crystal display device is about -12V when Vcc is 3.3V and about -10.5V when Vcc is 3.6V. The reason why the required VEE differs depending on the voltage of Vcc is as follows. That is, in this embodiment, Vcc or a half step-down voltage is used as it is as a voltage for driving the X electrode. Therefore, when Vcc increases, the effective voltage applied to the liquid crystal during the non-selection period increases, and the selection voltage needs to be decreased accordingly. Conversely, when Vcc is lowered, the effective voltage applied to the liquid crystal during the non-selection period is also lowered, and it is necessary to increase the selection voltage accordingly. For the above reasons, the boosting factor of the negative direction 6-fold booster circuit 2 of FIG. 1 is not 5 times when Vcc is higher than 3.3V, but 5 times is sufficient. Rather, it is 5 times when Vcc is high. It is preferable to switch automatically because power consumption is reduced. Further, in a 1/200 duty liquid crystal display device, even when Vcc drops to 3V, a negative five-fold boost is sufficient. Therefore, it is preferable that the external terminal can be switched from 5 times to 6 times and from 6 times to 5 times.

  The change of the step-up magnification and the step-down magnification can be realized as follows. For example, in the circuit shown in FIG. 10 described above, the configuration shown in FIG. That is, the magnification changing circuit 20 is provided, and the contact A of SWa2 may be connected to -V3B in the case of 6 times boosting, and the contact A of SWa2 may be connected to GND in the case of 5 times boosting. Alternatively, the magnification changing circuit 22 may be provided, and the contact B of SWb2 may be connected to -V3B in the case of 6-fold boosting, and the contact B of SWb2 may be connected to GND in the case of 5-fold boosting. On the other hand, with the circuit shown in FIG. 12 described above, the configuration shown in FIG. In other words, the magnification changing circuit 24 is provided, and the contact A of SWa2 is connected to −V3B in the case of negative direction 6-fold boosting, and the contact A of SWa2 is connected to GND in the case of negative direction 5-fold boosting.

  In order to change the 3/2 times step-up to 2/3 times step-down, the following steps may be taken. That is, in the 3 / 2-fold booster circuit shown in FIGS. 14A and 14B, the output terminal is connected to the + terminal of Cb, and Vcc is connected to the − terminal. As shown in FIG. 16B, switching means may be provided that connects the + terminal of Cb to Vcc and the-terminal to the output terminal.

  As described above, according to this embodiment, the charge pump circuit performs the charge pump operation of K-fold (K ≧ 2) boost or L / M times (where L / M is not an integer) step-down or M / L times boost. And means for changing the step-up or step-down ratio of the charge pump circuit. As a result, for example, the current consumed unnecessarily by the contrast adjustment circuit 3 in FIG. 1 can be reduced, and the power consumption can be further reduced.

  In the negative-direction 6-fold booster circuit shown in FIGS. 10 and 12, −V3B is formed. This −V3B corresponds to a voltage obtained by boosting GND twice in the negative direction with reference to Vcc. On the other hand, the output voltage −V3 of the negative direction double booster circuit 5 in FIG. 1 also corresponds to a voltage obtained by boosting GND twice in the negative direction with reference to Vcc. Therefore, for example, the output voltage −V3 of the negative double boosting circuit 5 may be shared as −V3B of FIGS. 10 and 12 without providing the circuit composed of SWb1, SWa1, Cp1, and Cp2 in FIGS. Is possible. Or, conversely, -V3B of the negative direction double boosting circuit 2 can be shared as -V3 without providing the negative direction double boosting circuit 5. However, since the output voltage drop due to the load current becomes large when sharing, it is preferable to select whether to share depending on the panel size.

Example 6
The sixth embodiment is an embodiment in which means for stopping the supply of the high voltage by the charge pump circuit is provided for a given period after the input power supply voltage is turned on.

  When a high voltage (first potential VH, Nth potential VL in FIG. 1) is generated using a charge pump circuit, generation of the high voltage is not stopped for a given period after the input power supply voltage is turned on. The system may not start up normally. One of the reasons is that if the logic part of the driver IC (data line driver, scanning line driver) is not operating normally before the high voltage is generated, the output circuit in the driver IC is short-circuited. Because there are cases. In order to prevent such a situation, for example, a supply stop circuit 26 is provided in the negative direction 6-fold booster circuit 2 of FIG. 1 as shown in FIG. Then, between -V3Bin and -V3Bout may be cut off for a given period after the input power supply voltage is turned on. FIG. 28B shows an example of a specific configuration of the supply stop circuit 26. After Vcc is turned on, Tr is turned off for a given period determined by the time constant of C × R, and between −V3Bin and −V3Bout is cut off. Furthermore, a resistance of about 10Ω is inserted in the path for directly using the input power supply voltage as the output voltage of the power supply circuit, that is, the path between Vcc and V3 and the path between GND and VC in FIG. Is desirable.

  In the configuration of FIG. 1, when supply of VL (Nth potential) is stopped by the supply stop circuit 26 provided in the negative direction 6-fold booster circuit 2, supply of VH (first potential) is also stopped. Therefore, it is not necessary to provide a supply stop circuit in the double booster circuit 4. On the other hand, for example, when VH is supplied using a circuit that boosts Vcc six times with reference to GND, a supply stop circuit may be provided in the six-fold booster circuit.

Example 7
FIG. 29 is a block diagram of a power supply circuit according to the seventh embodiment. This power supply circuit has a function of generating a voltage obtained by shifting the output voltage of the power supply circuit of the first embodiment shown in FIG. 1 to the high potential side as a whole by Vcc-GND. In the first embodiment of FIG. 1, the first to Nth potentials are formed symmetrically with respect to the second input potential GND on the low potential side, but in FIG. 29, the first input potential Vcc is set to the first input potential Vcc on the high potential side. It is formed symmetrically.

  In order to simplify the description, only the parts different from the first embodiment will be mainly described. The negative-direction five-fold booster circuit 32 generates a voltage VEE obtained by boosting GND five times in the negative direction with reference to Vcc by a charge pump operation. When Vcc is 3.3V, VEE becomes -13.2V. The double booster circuit 34 generates a voltage VH obtained by boosting Vcc twice with reference to VL. The double booster circuit 35 generates a voltage V3 obtained by boosting Vcc twice with reference to GND. The 1/2 voltage step-down circuits 36 and 37 generate V2 which is a voltage obtained by dividing V3-Vcc into two equal parts, and -V2 which is a voltage obtained by dividing Vcc-GND into two equal parts. Thus, the voltage for driving the liquid crystal panel was formed. Note that Vcc is used as it is for the central potential VC, and GND is used as it is for -V3. This power supply circuit is characterized in that the level of the output voltage is symmetric with respect to the input power supply voltage Vcc on the high potential side. According to the power supply circuit having such a configuration, the power consumption of the liquid crystal display device driven by the 4-line simultaneous selection method can be reduced for the same reason as described in the first embodiment.

  In this way, when the output voltage necessary for driving the liquid crystal has a central potential and most of the current consumption flows between the central potential and another voltage, the central potential matches the first and second input potentials. In addition, by using a configuration in which the output voltage is formed by a circuit mainly including a charge pump circuit, power consumption of the liquid crystal display device can be reduced. According to such a configuration, current consumption at the high voltages VH and VL is reduced, so that these high voltages VH and VL can be easily formed by a charge pump circuit having a low output capability. By forming these high voltages with a charge pump circuit with low power loss, the power consumption of the liquid crystal display device can be further reduced.

  In the seventh embodiment, the negative five-fold booster circuit can be changed to a positive booster circuit, and VH can be double boosted in the negative direction after VH is formed by the contrast adjustment circuit to form VL. is there.

Example 8
FIG. 30 shows a block diagram of a power supply circuit according to the eighth embodiment. This power supply circuit has a function of generating a voltage obtained by shifting the output voltage of the power supply circuit of the first embodiment to the high potential side as a whole by ½ × (Vcc−GND). In the eighth embodiment, the first to Nth potentials are formed symmetrically with respect to the midpoint potential of the first input potential Vcc and the second input potential GND.

  The 1/2 step-down circuit 46 is a circuit that generates a voltage VC obtained by equally dividing Vcc-GND by a charge pump operation, and this VC becomes the center potential of the first to Nth potentials. The negative-direction five-fold booster circuit 42 generates a voltage VEE obtained by boosting GND five times in the negative direction with reference to Vcc. The double booster circuit 44 generates a voltage VH obtained by boosting VC twice with reference to VL. The negative direction double boosting circuit 45 generates -V3 of a voltage obtained by boosting GND twice in the negative direction with reference to VC. The double booster circuit 49 generates a voltage V3 obtained by boosting Vcc twice in the positive direction with reference to VC. Thus, the voltage for driving the liquid crystal panel was formed. Note that Vcc is used as it is for V2, and GND is used as it is for -V2. This power supply circuit has a feature that the output voltage is symmetrical with respect to the midpoint potential VC of the first input potential and the second input potential. According to the eighth embodiment, the power consumption of the liquid crystal display device driven by the four-line simultaneous selection method can be reduced for the same reason as described in the first embodiment.

  If the desired voltage is 5 levels, the double booster circuit 49 and the negative double booster circuit 45 in FIG. 30 may be omitted.

Example 9
FIG. 31 shows a block diagram of a power supply circuit according to the ninth embodiment. In the ninth embodiment, the output voltage of the power supply circuit is formed symmetrically with respect to the midpoint potential of the first and second input potentials Vcc and GND. The power supply circuit according to the ninth embodiment is a circuit that drives a liquid crystal panel using a two-terminal nonlinear switching element. The power supply circuit described with reference to FIG. 51 is a system that fluctuates the power supply voltage applied to the Y driver, whereas the power supply circuit of the ninth embodiment outputs a steady voltage that does not fluctuate. FIG. 32 shows an example of a panel drive waveform when this power supply circuit is used.

  First, FIG. 32 will be described first. VSH is a positive selection voltage, and VSL is a negative selection voltage. VNH is a non-selection voltage after selecting VSH, and VNL is a non-selection voltage after selecting VSL. Each voltage has a relationship of VSH−VNH = VNL−VSL, in other words, a relationship in which the midpoint potential between VNH and VNL is equal to the midpoint potential between VSH and VSL. The horizontal axis t is a time axis, and one scale corresponds to the length t1H of one selection period. The column electrode drive waveform is an example when the gradation means is a pulse width gradation. As shown in FIG. 32, by making the voltage for driving the column electrode coincide with the non-selection voltage for the row electrode, the configuration of the power supply circuit is remarkably facilitated.

  Next, the circuit of FIG. 31 will be described. The logic driving voltages Vcc and GND are used as they are for the non-selection voltage and the column electrode driving voltage VNH and VNL at the same time. The negative-direction five-fold booster circuit 52 generates a voltage VEE obtained by boosting GND five times in the negative direction with reference to Vcc. When Vcc is 5V, VEE becomes -20V. The booster circuit 60 boosts the same voltage difference as VNL-VSL using VNH as a reference to generate VSH. Thus, the voltage for driving the liquid crystal panel was formed. The power supply circuit having this configuration is characterized in that the output voltage is symmetrical with respect to the midpoint potential of the first and second input potentials.

  When a liquid crystal panel using a two-terminal type non-linear switching element is driven by the power supply circuit having the above configuration, the operating voltage of the power supply circuit and the Y driver is nearly twice as high as that in the case of the shaking power supply method. The power consumption of the display device can be reduced. One reason for this is that the voltage applied to the Y driver is static, so that problems that occur in the shaking power supply method do not occur. That is, the problem that the entire parasitic capacitance of the Y driver is charged / discharged with a swinging voltage width, and the problem that a current flows in the Y driver in a short time at the swinging timing do not occur in this embodiment. Even if the high voltage is nearly doubled, the charge / discharge current and short-circuit current of the high voltage system of the Y driver during one selection period occur only in one of several hundred outputs. The increase in current due to the conversion is negligible. Another reason is that the power consumption of the power supply circuit itself is extremely small. This is because the output voltage is generated by a highly efficient charge pump type booster circuit. According to the present embodiment, it becomes possible to drive a liquid crystal panel using a two-terminal nonlinear switching element with about half the power consumption of the shaking power supply method.

  In the present embodiment, the negative direction five-fold booster circuit 52 is used. However, when using a low-voltage liquid crystal, the negative-direction five-fold booster circuit 52 may be a negative-direction four-fold booster circuit. Further, Vcc may be lowered to 3.3 V, and the negative direction fivefold booster circuit 52 may be replaced with a negative direction sixfold booster circuit as necessary. In this embodiment, the gradation display means is described as being based on the pulse width modulation method, but the frame thinning method may be used.

  If the desired voltage is 5 levels, a half voltage step-down circuit may be added between VCC and GND in FIG. 31 to generate the central potential.

Example 10
FIG. 33 is a block diagram of the power supply circuit according to the tenth embodiment. In the tenth embodiment, unlike the ninth embodiment, VNL that is different from the first and second input potentials Vcc and GND is generated. The output voltage of the power supply circuit is formed symmetrically with respect to the midpoint potential of this VNL and Vcc or GND.

  In the tenth embodiment, Vcc, which is a logic driving voltage, is used as it is as VNH which is a non-selection voltage and also a column electrode driving voltage. The negative direction 3/2 times booster circuit 61 generates a voltage VNL obtained by boosting GND 3/2 times in the negative direction with reference to Vcc. The configuration example of the negative direction 3 / 2-fold booster circuit 61 is as already described with reference to FIGS. 15 (A) and 15 (B). The negative-direction five-fold booster circuit 62 generates a voltage VEE obtained by boosting VNL five times in the negative direction with reference to Vcc. When Vcc is 3.3 V, Vcc-VNL is 4.95 V and VNL-VEE is 19.8 V. In Example 9, an output voltage almost equal to that when Vcc is 5 V is obtained. The booster circuit 70 boosts the same voltage difference as VNL−VSL in the positive direction with VNH as a reference, and generates VSH. Thus, the voltage for driving the liquid crystal panel was formed. This power supply circuit is characterized in that a potential VNL different from the first and second input potentials is generated by the charge pump circuit, and the output voltage is symmetric with respect to the midpoint potential of Vcc and VNL. According to the tenth embodiment having the above-described configuration, the logic voltage can be lowered, so that the liquid crystal panel using the two-terminal nonlinear switching element can be driven with lower power consumption than the ninth embodiment.

Example 11
FIG. 34 is a block diagram of the power supply circuit according to the eleventh embodiment. The difference from the first embodiment shown in FIG. 1 is that the input power supply voltage includes the third input potential Vee in the eleventh embodiment. In other words, the single power supply configuration (Vcc, GND) is used in the first embodiment, whereas the dual power supply configuration (Vee, Vcc, GND) is used in the eleventh embodiment.

  The negative-direction double booster circuit 72 generates a voltage VL obtained by boosting GND twice in the negative direction based on the third input potential Vee by a charge pump operation. The negative direction double boosting circuit 73 generates a voltage −V3 obtained by boosting GND twice in the negative direction with reference to the first input potential Vcc. The 1/2 step-down circuits 74 and 75 generate a voltage V2 obtained by equally dividing Vcc-GND and a voltage -V2 obtained by equally dividing GND-(-V3). Further, Vcc is used as it is for V3, and GND is used as it is for VC. With the power supply circuit having the above configuration, for example, a necessary voltage can be formed by the 4-line simultaneous selection method. The configuration of the charge pump type 1/2 step-down circuit has already been described with reference to FIG.

  FIG. 35 is a block diagram in the case where 1/3 step-down circuits 76 and 77 are provided instead of the 1/2 step-down circuits 74 and 75. The 1/3 step-down circuits 76 and 77 generate voltages V1, V2 obtained by dividing Vcc-GND by 1/3, and voltages -V1, -V2 obtained by dividing 1/3 each of GND-(-V3). To do. With this power supply circuit, for example, a necessary voltage can be formed by a 6-line simultaneous selection method.

  In this embodiment, for ease of understanding, the case where both Vee and Vcc are positive potentials with respect to GND has been described. However, both Vee and Vcc do not need to be positive potentials, and as shown in FIG. One or both of Vee and Vcc may be negative with respect to GND.

  The present embodiment described above has the following structural features.

  That is, in this embodiment, the first input potential Vcc on the high potential side and the second input potential GND on the low potential side included in the input power supply voltage are set to the Gth potential among the first to Nth potentials (N ≧ 4). V3 is used as it is as the J-th potential VC. Further, the third input potential Vee on the higher potential side or the lower potential side than the first and second input potentials is used as either the first potential VH on the higher potential side or the Nth potential VL on the lower potential side. Further, a charge pump circuit that performs a charge pump operation based on a given clock and supplies either the first or Nth potential VH or VL directly or through an adjusting means (negative double boosting circuit 72) A charge pump circuit (negative-direction double booster circuit) that supplies the F-th potential (1 <F <N) higher or lower than the G-th and J-th potentials directly or via the adjusting means 73). Further, a charge pump circuit (1) that performs a charge pump operation on potentials other than the first, F, G, J, and N potentials among the first to Nth potentials based on a given clock. / 2 step-down circuits 74 and 75 and 1/3 step-down circuits 76 and 77). According to the above configuration, the first potential VH or the Nth potential VL, which does not require so much output capability, is supplied by the charge pump circuit with low output capability but high efficiency, and the Gth potential V3, Jth potential. The potential VC is connected to input power supply voltages Vcc and GND having high output capability. Further, voltages such as V2 and -V2 are supplied by a charge pump circuit. Thereby, both maintenance of display quality and reduction in power consumption can be achieved. The configuration of the present embodiment also has a configuration feature described in (3) of the first embodiment, that is, a configuration feature in which charge pump circuits such as a K-fold booster and an L / M-fold buck are mixed. is doing.

  Next, the power consumption of the present embodiment will be described. Assuming that the current consumption of the V3-VC system of the load circuit downstream of the power supply circuit is Ic and the current consumption of the -V3-VC system is Id, according to this embodiment, the power consumption by Ic is Ic × Vcc. . Further, by making the negative direction double booster circuit 73 an efficient booster circuit, the power consumption by Id is approximately Id × Vcc. On the other hand, in the power supply circuit of FIG. 49, the power consumption by Ic is Ic × VEE, and the power consumption by Id is Id × VEE. If Vcc = 5V and VEE = 20V, the power consumption of the power supply circuit of FIG. 49 is (Ic + Id) × 20V, and the power consumption of this embodiment is (Ic + Id) × 5V. Therefore, power consumption can be reduced to about 1/4.

  Although the above has been described with attention paid only to the intermediate voltage, the same applies to the power consumption at VH and VL. That is, if the current consumption of the VH-VC system of the load circuit downstream of the power supply circuit is Ia and the current consumption of the VL-VC system is Ib, the power consumption by Ia and Ib is (Ia + Ib) × 20V. On the other hand, in this embodiment, by making the negative-direction double booster circuit 72 an efficient booster circuit, the power consumption becomes approximately (Ia + Ib) × 10 V, which can be reduced to about half. As can be seen from the above description, in this embodiment, when the load circuit requires a center voltage and most of the consumed current flows between the center voltage and another voltage, a significant reduction in power consumption can be achieved. It becomes possible.

  In the eleventh embodiment, as in the first embodiment, a charge pump operation can be performed by generating a clock using LP which is a pulsed clock. Also in the eleventh embodiment, charge pump circuits having various configurations as described in the second embodiment can be employed. Further, various methods as described in the third to sixth embodiments can be adopted to reduce power consumption. Further, in FIGS. 34 and 35, the output voltage is symmetric with respect to GND, but symmetric with respect to Vcc, symmetric with respect to the midpoint voltage of Vcc and GND, a given generated voltage and Vcc or GND. It is also possible to form the output voltage symmetrically with respect to the midpoint voltage. In FIG. 34, the 1/2 step-down circuits 74 and 75 are provided in order to obtain a 7-level voltage. However, if the desired voltage is 5 levels, the 1/2 step-down circuits 74 and 75 may be omitted. . Furthermore, when performing 1/2 step-down, 1/3 step-down, etc. using an operational amplifier, the configuration shown in FIG.

Example 12
In the twelfth embodiment, when at least one of the supply of the input power supply voltage is stopped, the supply of the given clock is stopped, or the display off control signal is input, the voltage is supplied by at least one of the first and Nth potentials. It is an Example which discharges the residual charge of a circuit part.

  FIG. 37 shows a circuit example for discharging VH and VL residual charges when the supply of the input power supply voltage is stopped or the supply of the clock is stopped. In FIG. 37, signals / A and A are clock signals having opposite phases. Trp8 and Trp9 are PMOS transistors, and repeat the operation that one of the transistors is turned on and the other is turned off while the clock is supplied. When Trp8 is turned on, the capacitor Cc1 is charged with the voltage Vcc, and when TrP9 is turned on, the charge of Cc1 is transferred to Cc2. If the time constant of Cc2 and the resistor Rc is set sufficiently larger than the cycle of the clock signal, the input of the buffer Buf becomes a level substantially close to the voltage Vcc. Since one of the transistors is always turned off when the clock stops, the input of Buf becomes GND level by Rc, and the output of Buf also becomes GND level. Even when the supply of the voltage Vcc is stopped, the input and output of the Buf are at the GND level.

  Trn5 and Trn6 are NMOS transistors, and Trp5, Trp6 and Trp7 are PMOS transistors. Ra1, Ra2, and Rb1 are resistances on the order of several MΩ, and are set to resistance values that are larger than the resistances when Trn5 and TrP5 are on. Therefore, even when these transistors are on, the consumption current flowing through these resistors is small. When the voltage Vcc is supplied and the clock is supplied, Trn5 is turned on because the output of Buf is at the Vcc level. When Trn5 is turned on, the gate of Trp7 becomes the low side, Trp7 is turned on, and the voltage Vee is supplied to VH. Further, the gate of Trn6 becomes the GND level and Trn6 is turned off. The voltage −V3 is an inverted output of the voltage Vcc (see FIGS. 1 and 34), and is approximately at the level of −Vcc when the voltage Vcc is supplied and the clock is operating. As a result, Trp5 is turned on and Trp6 is turned off.

  When the supply of the voltage Vcc is stopped or the supply of the clock is stopped, the output of Buf and the voltage −V3 become the GND level, and both Trn5 and Trp5 are turned off. When Trn5 is turned off, the gate of Trp7 becomes Vee level, Trp7 is turned off, and the supply from Vee to VH is cut off. The gate of Trn6 is also turned on at the Vee level, and the charge remaining in the VH system is discharged to GND through the resistor Ra3 of about 10 KΩ. When Trp5 is turned off, the gate of Trp6 is turned to the low side, Trp6 is turned on, and the charge remaining in the VL system is discharged to GND through the resistor Rb2 of about 10 KΩ.

  As described above, according to the present embodiment, when the supply of the voltage Vcc or the clock is stopped, the supply of the voltage Vee is cut off, and the residual charge of the circuit portion to which the voltage is supplied by the voltages VH and VL is discharged. Can be realized with almost no increase in power consumption. As a result, it is possible to prevent an abnormal situation in which a high DC voltage is continuously applied to the circuit portion.

  FIG. 38 shows an example of a circuit for discharging VH and VL charges by a display on / off signal. The main difference from FIG. 37 is that the signal Don is input to the gate of Trn5. The signal Don is a signal for controlling on / off of the display of the liquid crystal display device, and is a signal that is at a high level (Vcc) when the display is on and at a low level (GND) when the display is off. When Don is at a high level, Trn5 is turned on, whereby the gate of Trp7 becomes low and Trp7 is turned on. As a result, the voltage Vee is supplied to VH.

  On the other hand, when Don is at a low level, Trn5 is turned off, whereby the gate of Trp7 becomes the same level as Vee and Trp7 is turned off. Thereby, supply of the voltage Vee to VH is interrupted. At the same time, the gate of Trn6 becomes the same level as Vee and Trn6 is turned on. As a result, the charge remaining in the VH system is discharged.

  As described above, by inputting the display on / off control signal to the power supply circuit of this embodiment, the display on / off of the liquid crystal display device can be easily controlled without increasing the current consumption. Instead of directly inputting the signal Don to the gate of Trn5 as described above, a method of adding a circuit for stopping the clock when Don is low is used to discharge the VH residual charge and display the liquid crystal display device. It may be turned off. Further, as shown in FIG. 4, the liquid crystal display device may be turned off by controlling the reset terminal of the DF to stop the clock and stopping the operation of the charge pump circuit.

  39A and 39B show circuit examples for discharging VH and VL charges when the input power supply is turned off. For example, in FIG. 39A, when the input power is turned off and Vcc = GND, Trn10 is turned off and the gate of Trn11 is set to the high side. Thereby, Trn11 is turned on, and the VH charge is discharged to GND. In FIG. 39B, when Vcc = GND, Trp10 is turned off and the gate of Trp11 is on the low side. As a result, Trp11 is turned on, and the VL charge is discharged to Vcc.

  FIGS. 40A and 40B show circuit examples for discharging VH and VL charges when the input power supply is turned off and when a display off signal is inputted. Doff is a signal that becomes high level (= Vcc) when the display is off. When Doff becomes high level, its inversion signal / Doff becomes low level (= GND), whereby Trn10 is turned off and the gate of Trn11 becomes high side. Thereby, Trn11 is turned on, and the VH charge is discharged to GND. In FIG. 40B, when Doff becomes high level, Trp10 is turned off and the gate of Trp11 is set to the low side. As a result, Trp11 is turned on, and the VL charge is discharged to Vcc.

Example 13
FIG. 41 shows a configuration example of a liquid crystal display device including the power supply circuit described in Embodiments 1 to 12. The liquid crystal display device includes a liquid crystal panel 88 including a liquid crystal layer driven by a plurality of data line electrodes and a plurality of scanning line electrodes, a power supply circuit 91, and a data line electrode based on a voltage supplied by the power supply circuit 91. An X driver IC (data line driver) 90 for driving and a Y driver IC (scanning line driver) 89 for driving the scanning line electrodes based on the voltage supplied by the power supply circuit are included.

  VCC-GND is a power input for driving the logic part of the driver IC, and VEE-GND is a high voltage power input for forming a selection voltage. When the power supply circuit is configured as shown in FIG. 1, VEE is not necessary. LP is a latch pulse for the X driver IC, and is usually also used as a shift clock for the Y driver IC including a shift register. Other timing signals and data signals are not shown for the sake of clarity.

  FIG. 42 shows an example of a driving voltage waveform when the liquid crystal panel is driven by the circuit of FIG. This driving waveform corresponds to the driving waveform when V111 = V122 is set in the driving method described in claim 1 of JP-B-57-57718. Here, VH and VL are voltages applied to the selected scanning line electrodes, and VC (VM) is a voltage applied to the non-selected scanning line electrodes. Vx0 and Vx1 are voltages applied to the X electrode in accordance with ON / OFF of display data. M is a control signal for AC driving of the liquid crystal, and the polarity of the voltage applied to the liquid crystal panel is inverted by the high / low of the signal M. t1H indicates the length of time for which one scanning line electrode is selected.

  The voltage necessary for this driving method can be formed by the power supply circuit described in the first to twelfth embodiments. For example, the outputs VC, VH, and VL of the power supply circuit 91 are used for the non-selection level VC and the selection levels VH and VL. Further, V2 may be used for Vx0 for driving the X electrode, and -V2 may be used for Vx1. For example, when the duty is 1/240, VH is normally about 20V, and V2 is about 1.6V, which is about 1/2 of the logic voltage 3.3V. Therefore, a voltage obtained by stepping down the logic voltage to ½ can be used as V2.

  As a logic voltage of the X driver IC 90, VCC-GND may be used as it is. As the logic voltage of the Y driver IC 89, VCC-GND may be used as it is when it is in the middle of the driver output voltage like the gate line driver IC for TFT panel. However, when the low level of the logic voltage matches VL as in the case of a normal driver IC for an STN panel, for example, it is necessary to separately form the logic voltage VDD for the Y driver IC 89. FIG. 43 shows an example of a Y driver logic voltage generation circuit used in this case, which basically performs the same operation as the portion indicated by H in FIG. That is, B is the signal shown in FIG. 5 and is a signal driven using VCC-GND as a power source. Cs1 and Cs2 are coupling capacitors having a capacitance of about 470 pF, D1 and D2 are diodes, Buf1 and Buf2 are buffers, and Rf1 and Rf2 are resistors of about 1 KΩ. Buf1 and Rf1 form one hold circuit, and Buf2 and Rf2 form another hold circuit. If the negative power supply terminal of the buffer is connected to VL in the connection as shown in FIG. 37, a voltage VDDy higher than VCC by VCC is generated at the positive power supply terminal of the buffer. Therefore, this VDDy may be used as a logic power source for the Y driver IC 89. The operating frequency of the Y driver IC 89 is about 1/80 of that of the X driver IC 90, and the current consumption of the logic part of the Y driver IC 89 is extremely small. Therefore, it can be sufficiently driven by the power supply voltage formed by the simple method as described above. The circuit of FIG. 43 also has a function of shifting the level of the signal LP to form a Y driver shift clock YSCL. A smoothing capacitor Cx of about 0.1 μF is preferably inserted between the power supply terminals of the buffer.

  In the above description, VCC is 3.3V. However, when VCC is 5V, it is more effective to reduce power consumption by converting VCC to a lower voltage using an operational amplifier or the like and driving the power supply circuit 91, Y driver IC 89, and X driver IC 90. preferable. When VCC is about 1.5 V, this VCC is used as it is as Vx0, and the inverted boosted voltage of VCC (double boosted voltage in the negative direction) may be used as Vx1.

  In the liquid crystal display device having the above configuration, the power supply circuit itself has low power consumption. Furthermore, the charging / discharging current that occupies most of the panel current, that is, the charging / discharging current flowing between the X electrode and the non-selected Y electrode is not supplied from the high voltage system, but a lower logic unit driving voltage. Supplied from the system. Therefore, the power consumption due to the panel current is also greatly reduced, and the power consumption can be significantly reduced as a whole.

Example 14
FIG. 44A illustrates another configuration example of a liquid crystal display device. Since the configuration is basically the same as that of the thirteenth embodiment, only portions different from the thirteenth embodiment will be described. In this embodiment, the Y electrode is driven by the 2-line simultaneous selection method.

  FIG. 44B shows voltages necessary to be applied to the liquid crystal panel in this driving method. For driving the Y electrode, as in the thirteenth embodiment, the non-selection level VC (VM) and the selection levels VH and VL are required. Here, VH and VL are symmetric with respect to VC. For driving the X electrode, three levels of voltages Vx0 to Vx2 are required. Vx1 is at the same potential as VC, and Vx0 and Vx2 are symmetrical with each other about Vx1. For example, in the case of using a normal liquid crystal in which the number of Y electrodes scanned within one frame period is about 240 and Vth (threshold voltage) has an effective value of about 2 V, when VC is 0 V, VH is about 16V and Vx0 are about 2V. That is, the differences from the thirteenth embodiment are only that the center potential is added as the drive voltage for the X electrode, and that VH slightly decreases and Vx0 slightly increases. The power supply circuit of this embodiment is suitable for generating such a symmetrical voltage with low power consumption.

  When VCC is 3.3 V, a low voltage liquid crystal having an effective value of Vth of about 1.6 V may be used. When VCC is about 1.5V, low voltage liquid crystal is used, and this VCC can be used as it is as Vx0.

  In the liquid crystal display device of this embodiment, the power supply circuit itself has low power consumption, and the power consumption due to the panel current is greatly reduced for the same reason as described in the thirteenth embodiment. In addition, the maximum voltage required for driving can be lower than that of the thirteenth embodiment, and further power consumption can be reduced. In the comparative example of FIG. 49, if the current consumption in the logic part of the X driver is IXD, the power consumption due to this is IXD × VEE. On the other hand, in this embodiment, the power consumption is only IXD × VCC, and the power consumption can be significantly reduced as compared with the comparative example.

Example 15
FIG. 45A illustrates another configuration example of a liquid crystal display device. In this embodiment, the Y electrode is driven by the 4-line simultaneous selection method.

  FIG. 45B shows voltages necessary to be applied to the liquid crystal panel in this driving method. The driving of the Y electrode requires VC as a non-selection level and VH and VL as selection levels, and VH and VL are in a symmetrical relationship with respect to VC. Driving the X electrode requires five levels of voltages Vx0 to Vx4, and Vx2 is at the same potential as VC. Vx0 and Vx4 and Vx1 and Vx3 are symmetrical with respect to Vx2, and satisfy Vx0−Vx1 = Vx1−Vx2 = Vx2−Vx3 = Vx3−Vx4. For example, when a normal liquid crystal having about 240 Y electrodes scanned within one frame period and Vth having an effective value of about 2 V is used, VH is about 11.3 V when the voltage of VC is 0 V. Vx0 is about 2.9V. That is, the difference from the fourteenth embodiment is that a two-level voltage symmetrical to the center potential is added as the drive voltage for the X electrode, and that VH slightly decreases and Vx0 slightly increases.

  In particular, when VCC is 3.3 V, since VCC and Vx0 are relatively close to each other, VCC can be used as Vx0 as it is as shown in FIG. In this case, the contrast can be easily adjusted by using a liquid crystal having a slightly higher Vth or setting VEE a little lower.

Example 16
FIG. 46A illustrates another configuration example of a liquid crystal display device. In this embodiment, the Y electrode is driven by the 6-line simultaneous selection method.

  FIG. 46B shows voltages necessary to be applied to the liquid crystal panel in this driving method. The driving of the Y electrode requires VC as a non-selection level and VH and VL as selection levels, and VH and VL are in a symmetrical relationship with respect to VC. To drive the X electrode, 7 level voltages Vx0 to Vx6 are required, Vx3 is the same potential as VC, and Vx0 to Vx6 are Vx0−Vx1 = Vx1−Vx2 = Vx2−Vx3 = Vx3−Vx4 = Vx4-Vx5 = Vx5-Vx6 is satisfied. For example, when a normal liquid crystal having about 240 Y electrodes scanned within one frame period and Vth having an effective value of about 2 V is used, VH is about 9.2 V when the voltage of VC is 0 V, Vx0 is about 3.6V. That is, the difference from the fifteenth embodiment is that a two-level voltage symmetrical to the center potential is added as the driving voltage for the X electrode, and that VH slightly decreases and Vx0 slightly increases.

  In particular, when VCC is 3.3 V, since VCC and Vx0 are relatively close to each other, VCC can be used as it is as Vx0 as shown in FIG. In this case, the contrast can be easily adjusted by using a liquid crystal having a slightly lower Vth or setting VEE a little higher.

  The following describes how practical the number of Y electrodes simultaneously selected is. For example, when the number of Y electrodes scanned within one frame period is about 240, when the number of lines to be simultaneously selected is 15 to 16, the maximum voltage width necessary for driving the Y electrodes and the driving of the X electrodes The required maximum voltage width is equal. When a normal liquid crystal having an effective value of Vth of about 2V is used, this voltage is less than 6V. In other words, when the number of simultaneously selected lines is 16 or less, the driving method with a larger number of Y electrodes to be selected simultaneously requires a lower maximum voltage, which is advantageous in reducing power consumption. However, on the contrary, the number of voltage levels required for driving increases and the power supply circuit becomes complicated, and the cost of the X driver IC also increases. Therefore, the number of lines to be simultaneously selected is practically 8 or less. I can say that.

  In the thirteenth to sixteenth embodiments described above, for example, as shown in FIG. 46A, the first and second input potentials VCC and GND are set to V3, V2, V1, VC, -V1, -V2,- It is used as one of V3 (first to Nth potentials) and also used as a power supply voltage for the logic part of the driver IC. In addition to the input power supply voltage (VEE, VCC, GND or VCC, GND) used in the power supply circuit 91, it is better to prepare another power supply voltage for driving the logic part of the driver IC. It is preferable in terms of driving. However, an increase in the number of input power supply voltages is not preferable for a user of a liquid crystal display device. As described in the thirteenth to sixteenth embodiments, VCC and GND are used as any one of V3, V2 to -V2, and -V3, and even slightly used as the power supply voltage of the logic part of the driver IC. Although it is driven by a voltage deviating from the voltage, it is possible to display an image with no problem in practice. Therefore, it becomes more practical to suppress the increase in the number of input power supply voltages as in the thirteenth to sixteenth embodiments.

  If none of V3, V2 to -V2, or -V3 matches VCC or GND, a voltage different from VCC or GND is generated by the charge pump operation as described in FIG. This generated voltage may be used as any one of V3, V2 to -V2, and -V3.

  As shown in FIG. 41 and the like, in the thirteenth to sixteenth embodiments, the X driver latch pulse signal LP or the Y driver shift clock YSCL is used as the pulsed clock input to the power supply circuit 91. The reason why the signal forming the clock of the power supply circuit 91 is preferably a periodic pulse clock is as already described in the second embodiment. Usually, the latch pulse signal for the X driver is a periodic pulsed clock signal having a period of about 30 μs to 100 μs and a pulse width of about 100 ns to 300 ns, so that it can be used without any problem as a pulsed clock for the power supply circuit 91. In some liquid crystal display devices, the Y driver shift clock is input separately from the X driver latch pulse. In this case, the Y driver shift clock is a periodic pulsed clock signal similar to the X driver latch pulse. Therefore, there is no problem using this clock. Among timing signals input to the liquid crystal display device, these signals are most appropriate. Since most of the consumption current of the liquid crystal display device is a current that flows every switching of one horizontal scanning period, a charge pump circuit that supplies the current is used for an X driver that is a pulsed clock for each horizontal scanning period. It makes sense to operate in synchronization with a latch pulse or a Y driver shift clock. A clock signal having a longer period than this is insufficient for boosting capability. On the other hand, a pulsed clock signal with a shorter period is preferable for ensuring the boosting capability, but such a signal is not input to the liquid crystal display device and must be created separately. Leads to.

Example 17
FIG. 47 shows an example in which the liquid crystal display device of the present invention is mounted on an electronic device. The μPU (micro micro processor unit) 112 controls the entire electronic device, and the LCD controller 113 sends out necessary timing signals and display data to the liquid crystal display device 115. A memory (VRAM) 114 stores display data, and a battery 116 is a power source of the electronic device. The DC / DC converter 117 generates a high voltage necessary for the liquid crystal display device 115 from the voltage of the battery 116. The DC / DC converter 117 may be incorporated in the liquid crystal display device, and in the case of incorporating it, it is desirable to use a charge pump type DC-DC converter as in the present invention. By using the liquid crystal display device of the present invention for such an electronic device, the power consumption of the electronic device can be significantly reduced.

  In addition, this invention is not limited to the said Example 1- Example 17, Various deformation | transformation implementation is possible within the range of the summary of this invention.

  For example, the method of using a pulsed clock, the method of changing the boost ratio, the method of performing the charge pump for each horizontal period, etc. are not limited to the power supply circuit having the configuration shown in FIGS. Any power supply circuit including a charge pump circuit for supplying the Nth potential can be applied.

  The configuration of the charge pump circuit is not limited to that shown in FIGS.

  In the above embodiment, the charge pump circuit using the latch pulse LP has been described as an example. However, when LP is not used, a non-overlapping clock may be generated using a delay circuit or the like.

1 is a block diagram of a power supply circuit according to Embodiment 1. FIG. It is a block diagram at the time of using an operational amplifier for generation of V2 and -V2. It is a circuit diagram which shows an example of a contrast adjustment circuit. It is a circuit diagram which shows an example of a clock formation circuit. 6 is a timing chart for explaining the operation of the clock forming circuit. It is a basic conceptual diagram of a charge pump circuit. It is a conceptual diagram of a charge pump circuit for double boosting. It is a conceptual diagram of a negative direction double boosting charge pump circuit. It is a conceptual diagram of a 1/2 step-down charge pump circuit. It is a conceptual diagram of the negative direction 6 times boosting charge pump circuit. 11A and 11B are diagrams for explaining the operation of the circuit of FIG. It is a conceptual diagram of the other example of the charge pump circuit for negative direction 6 times boosting. 13A and 13B are diagrams for explaining the operation of the circuit of FIG. 14 (A) and 14 (B) are conceptual diagrams of a charge pump circuit for 3/2 times boosting. FIGS. 15A and 15B are conceptual diagrams of charge pump circuits for boosting in the negative direction 3/2 times. FIGS. 16A and 16B are conceptual diagrams of a charge pump circuit for 2 / 3-fold voltage step-down. FIG. 17A and FIG. 17B are conceptual diagrams of a negative direction 2/3 times step-down charge pump circuit. It is a circuit diagram which shows the specific example of a negative direction double booster circuit. It is a figure for demonstrating operation | movement of the circuit of FIG. 20A and 20B are circuit diagrams showing an example of the level shift means. It is a circuit diagram which shows an example of the charge pump circuit using a diode. It is a figure for demonstrating operation | movement of the circuit of FIG. It is a circuit diagram which shows the application example of the circuit of FIG. It is a circuit diagram which shows the example of the charge pump circuit which provided two pumping capacitors. FIG. 25A, FIG. 25B, and FIG. 25C are diagrams for explaining a method of performing a charge pump operation for each horizontal scanning period. It is a circuit diagram which shows the example of the charge pump circuit which provided the step-up / step-down magnification change part. It is a circuit diagram which shows the other example of the charge pump circuit which provided the step-up / step-down magnification change part. 28A and 28B are circuit diagrams illustrating an example in which the supply of high voltage is stopped for a given period after the power is turned on. FIG. 10 is a block diagram of a power circuit according to a seventh embodiment. FIG. 10 is a block diagram of a power circuit according to an eighth embodiment. FIG. 10 is a block diagram of a power circuit according to a ninth embodiment. It is a figure which shows the example of a panel drive waveform. FIG. 10 is a block diagram of a power circuit according to a tenth embodiment. FIG. 10 is a block diagram of a power circuit according to an eleventh embodiment. FIG. 20 is a block diagram illustrating another example of a power supply circuit according to Example 11. It is a figure for demonstrating the electric potential relationship of an input power supply voltage. It is a circuit diagram which shows the example which discharges the VH and VL type | system | group residual charge. It is a circuit diagram which shows the other example which discharges the VH and VL type | system | group residual charge. FIGS. 39A and 39B are circuit diagrams illustrating another example of discharging the VH and VL residual charges. FIGS. 40A and 40B are circuit diagrams showing another example of discharging VH and VL residual charges. FIG. 20 is a block diagram illustrating an example of a liquid crystal display device according to Example 13; FIG. 42 is a diagram for explaining a drive waveform of the liquid crystal display device of FIG. 41. It is a circuit diagram which shows an example of a level shift means. FIG. 44A is a block diagram illustrating an example of a liquid crystal display device according to Embodiment 14, and FIG. 44B is a diagram for explaining a potential relationship of drive voltages. FIG. 45A is a block diagram illustrating an example of a liquid crystal display device according to the fifteenth embodiment, and FIG. 45B is a diagram for explaining a potential relationship of drive voltages. FIG. 46A is a block diagram illustrating an example of a liquid crystal display device according to the sixteenth embodiment, and FIG. 46B is a diagram for explaining a potential relationship of drive voltages. FIG. 20 is a block diagram illustrating an example of an electronic apparatus according to a seventeenth embodiment. It is a circuit diagram which shows an example of the power supply circuit of a 1st background example. It is a circuit diagram which shows an example of the power supply circuit of a 2nd background example. It is a figure which shows an example of the panel drive waveform for demonstrating the power supply circuit of the 3rd background example. It is a circuit diagram which shows an example of the power supply circuit of a 3rd background example.

Explanation of symbols

LP latch pulse Vcc first input potential GND second input potential VH first potential V3 G potential VC J potential VL Nth potential 1 clock forming circuit 2 negative direction 6 × boosting circuit 3 contrast adjusting circuit 4 2 × boosting circuit 5 Negative direction double booster circuit 6 1/2 step-down circuit 7 1/2 step-down circuit

Claims (6)

A power supply circuit that is supplied with an input power supply voltage and supplies first to Nth (N ≧ 4) potentials for driving a liquid crystal panel of a liquid crystal display device,
A charge pump circuit that performs a charge pump operation based on a clock generated by a pulsed clock including a periodically generated pulse, and supplies any one of the first to Nth potentials directly or via an adjusting means When,
Means for stopping charging of the pumping capacitor included in the charge pump circuit and charging of the backup capacitor by the pumping capacitor during the generation of the pulse of the pulsed clock;
Means for stopping the charge pump operation by stopping the given clock supplied to the charge pump circuit when a display off control signal of the liquid crystal panel is input;
A power supply circuit comprising: A power supply circuit that is supplied with an input power supply voltage and supplies first to Nth (N ≧ 4) potentials for driving a liquid crystal panel of a liquid crystal display device,
A charge pump circuit that performs a charge pump operation based on a given clock, and supplies any one of the first to Nth potentials directly or via an adjustment means;
Means for charging the pumping capacitor included in the charge pump circuit and charging the backup capacitor by the pumping capacitor every one horizontal scanning period in driving the liquid crystal panel;
Means for stopping the charge pump operation by stopping the given clock supplied to the charge pump circuit when a display off control signal of the liquid crystal panel is input;
A power supply circuit comprising: In claim 1 or 2,
When the given clock supplied to the charge pump circuit is stopped when the display off control signal is input and the charge pump operation is stopped, a voltage is applied by at least one of the first and Nth potentials. A power supply circuit comprising means for discharging a residual charge of a circuit portion to which is supplied. A power supply circuit which is supplied with an input power supply voltage and supplies first to Nth (N ≧ 4) potentials for driving a display element,
A charge pump circuit that performs a charge pump operation based on a given clock, and supplies any one of the first to Nth potentials directly or via an adjustment means;
Means for charging a plurality of pumping capacitors included in the charge pump circuit and charging a backup capacitor by the plurality of pumping capacitors every horizontal scanning period in driving the display element,
The first pumping capacitor of the plurality of pumping capacitors is charged with charge in one horizontal period, and the charge charged in the second pumping capacitor of the plurality of pumping capacitors is Charge the backup capacitor,
Charging the second pumping capacitor with a charge in the horizontal period following the one horizontal period, and charging the backup capacitor with the charge charged in the first pumping capacitor;
The power supply circuit, wherein the charge pump circuit performs a charge pump operation in which a backup capacitor is alternately charged every horizontal period by the plurality of pumping capacitors.   5. The power supply circuit according to claim 1, a liquid crystal panel including a liquid crystal layer controlled by a plurality of data line electrodes and a plurality of scanning line electrodes, and a potential supplied by the power supply circuit. And a data line driver for controlling the data line electrode, and a scanning line driver for controlling the scanning line electrode based on a potential supplied by the power supply circuit.   An electronic apparatus comprising the liquid crystal display device according to claim 5.

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