JP2006195019A - Liquid crystal display apparatus, and driving circuit and driving method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display apparatus capable of generating a common voltage Vcom with a simple circuit configuration and obtaining the stable common voltage Vcomwithout increasing power consumption, and to provide a driving circuit and a driving method for the display apparatus. <P>SOLUTION: A common driver 500 alternately sets the common voltage Vcom to a high voltage level VDD and a low voltage level VSS which are supplied from a power source 100 for an external control circuit. At that time, the common driver 500 switches over the common voltage Vcom between the high voltage level VDD and the low voltage level VSS for each one horizontal scanning period, based on a first polarity inversion signal FRP1 and a second polarity inversion signal FRP2 which are supplied from a display control circuit 200. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an active matrix liquid crystal display device, and more specifically, a monolithic liquid crystal display in which a driving circuit for driving a liquid crystal display device is formed on a substrate constituting a display panel for displaying an image. The present invention relates to a driving circuit and a driving method of an apparatus.

  2. Description of the Related Art Conventionally, an active matrix type liquid crystal display device including a TFT (Thin Film Transistor) as a switching element is known. This liquid crystal display device includes a liquid crystal panel composed of two insulating substrates facing each other. On one substrate of the liquid crystal panel, scanning signal lines (gate bus lines) and video signal lines (source bus lines) are provided in a lattice pattern, and TFTs are provided in the vicinity of intersections between the scanning signal lines and the video signal lines. It has been. The TFT is composed of a gate electrode connected to the scanning signal line, a source electrode connected to the video signal line, and a drain electrode. The drain electrode is connected to pixel electrodes arranged in a matrix on the substrate in order to form an image. The other substrate of the liquid crystal panel is provided with an electrode (hereinafter referred to as “common electrode”) for applying a voltage to the pixel electrode through the liquid crystal layer. The pixel electrode, the common electrode, and the liquid crystal Individual pixel forming portions are realized by the layers. Then, when the gate electrode of each TFT receives an active scanning signal from the scanning signal line, the common electrode and a potential (hereinafter referred to as “source potential”) indicated by the video signal received by the source electrode of the TFT from the video signal line. A voltage is applied to the liquid crystal layer of the pixel formation portion based on the potential difference with the potential (hereinafter referred to as “common potential”). As a result, the liquid crystal is driven and a desired image is displayed on the screen.

  FIG. 16 is a diagram showing the relationship between the common potential Vcom and the source potential Vs in the conventional active matrix liquid crystal display device. As for driving of the common electrode, there are conventionally a configuration in which AC driving is performed and a configuration in which the common potential Vcom is constant. FIG. 16A shows the relationship between the common potential Vcom and the source potential Vs in a configuration in which the common electrode is AC driven. In this configuration, the amplitude of the source potential Vs is small, but the amplitude of the common potential Vcom is large. On the other hand, FIG. 16B shows the relationship between the common potential Vcom and the source potential Vs in a configuration in which the common potential Vcom is constant. In this configuration, the common potential Vcom is constant, but the amplitude of the source potential Vs is large.

  FIG. 17 is a block diagram showing a configuration for generating a common potential Vcom in a conventional active matrix liquid crystal display device. FIG. 17A shows a configuration in which the power supply 100, the DC / DC converter 700, and the common driver 500 are provided outside the display panel 600. According to this configuration, the DC / DC converter 700 generates a potential higher than the common potential by boosting the power supply voltage, and the common driver 500 generates the common potential Vcom by stepping down the potential using a voltage dividing circuit or the like. . Alternatively, the DC / DC converter 700 boosts the power supply voltage to generate a potential equal to the common potential, and the common driver 500 outputs a voltage signal at that potential. FIG. 17B shows a configuration in which the power supply 100 and the DC / DC converter 700 are provided outside the display panel 600 and the common driver 500 is provided inside the display panel 600. Also with this configuration, the DC / DC converter 700 generates a potential higher than the common potential by boosting the power supply voltage, and the common driver 500 generates the common potential Vcom by stepping down the potential using a voltage dividing circuit or the like. . Alternatively, the DC / DC converter 700 boosts the power supply voltage to generate a potential equal to the common potential, and the common driver 500 outputs a voltage signal at that potential. FIG. 17C shows a configuration in which the power supply 100 is provided outside the display panel 600 and the DC / DC converter 700 and the common driver 500 are provided inside the display panel 600. Also with this configuration, the DC / DC converter 700 generates a potential higher than the common potential by boosting the power supply voltage, and the common driver 500 generates the common potential Vcom by stepping down the potential using a voltage dividing circuit or the like. . Alternatively, the DC / DC converter 700 boosts the power supply voltage to generate a potential equal to the common potential, and the common driver 500 outputs a voltage signal at that potential.

With respect to such an active matrix display device, the following techniques for reducing costs are disclosed. Japanese Laid-Open Patent Publication No. 2003-99008 discloses a technique for reducing the number of output terminals of a controller as compared with the prior art by using a gate control signal generated by a gate driver as a polarity inversion instruction signal for determining a common potential. ing. Japanese Patent Laid-Open No. 2002-174823 discloses a technique for forming a common electrode voltage generation circuit for driving a common electrode on the same substrate as the display portion.
JP 2003-99008 A JP 2002-174823 A

  According to a conventional active matrix liquid crystal display device, a power supply circuit such as a DC / DC converter is required to generate a common potential, and the potential boosted by the DC / DC converter or the like is shared by resistance voltage division or the like. It is also necessary to step down with a driver. For this reason, there is a problem that a load for circuit design or the like is large and a power consumption of the display device is large. Another problem is that a stable common potential cannot be obtained because the common potential is generated by once boosting the power supply voltage and then reducing the boosted voltage. Furthermore, when the common electrode is configured to be AC driven as shown in FIG. 16A, power consumption is increased because the amplitude of the common potential needs to be increased. On the other hand, when the common potential is made constant as shown in FIG. 16B, it is necessary to increase the amplitude of the source potential, so that the power consumption cannot be reduced.

  Accordingly, the present invention provides a display device capable of generating a common potential with a simple circuit configuration and obtaining a stable common potential without increasing power consumption, and a driving circuit and a driving method thereof. With the goal.

According to a first aspect of the present invention, a plurality of video signal lines for respectively transmitting a plurality of video signals representing images to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of video signals A plurality of switch elements arranged in a matrix corresponding to intersections of the lines and the plurality of scanning signal lines, a plurality of pixel electrodes respectively connected to the plurality of switch elements, and the plurality of pixel electrodes. A drive circuit for a display device including a display unit that includes the plurality of pixel electrodes provided in common and a common electrode that forms a predetermined capacitance and displays the image;
A video signal line driving circuit for supplying the plurality of video signals to the plurality of video signal lines, a scanning signal line driving circuit for selectively driving the plurality of scanning signal lines, and a common electrode for driving the common electrode Drive circuit,
The common electrode drive circuit alternately sets the potential of the common electrode to a high potential voltage level and a low potential voltage level supplied from a power supply for an external control circuit at a predetermined cycle. To do.

According to a second invention, in the first invention,
The video signal line driving circuit includes:
When the potential of the common electrode is set to the high potential voltage level, the potential indicated by the plurality of video signals is set to a potential lower than the potential of the common electrode,
When the potential of the common electrode is set to the low potential voltage level, the potential indicated by the plurality of video signals is set to a potential higher than the potential of the common electrode,
The upper limit value of the potential indicated by the plurality of video signals set to a potential higher than the potential of the common electrode is the upper limit value of the potential indicated by the plurality of video signals set to a potential lower than the potential of the common electrode. Higher than
The lower limit value of the potential indicated by the plurality of video signals set to a potential higher than the potential of the common electrode is the lower limit value of the potential indicated by the plurality of video signals set to a potential lower than the potential of the common electrode. It is characterized by being lower than.

According to a third invention, in the first invention or the second invention,
The video signal line driving circuit includes:
A first gradation voltage group composed of a plurality of voltages showing different gradations, and a second gradation voltage group composed of a plurality of voltages corresponding to each of the plurality of voltages included in the first gradation voltage group; A gradation voltage generating circuit that outputs
When the potential of the common electrode is set to the high potential voltage level, a voltage selected from the second gradation voltage group is supplied to the video signal line as the video signal,
When the potential of the common electrode is set to the low potential voltage level, a voltage selected from the first gradation voltage group is supplied to the video signal line as the video signal.

According to a fourth invention, in the third invention,
The gradation voltage generation circuit is constituted by a voltage dividing circuit including a plurality of resistors connected in series with each other,
The voltage dividing circuit generates the first gradation voltage group and the second gradation voltage group.

According to a fifth invention, in the third invention,
The gradation voltage generation circuit includes a plurality of resistors connected in series, a first voltage dividing circuit that generates the first gradation voltage group, and a plurality of resistors connected in series. And a second voltage dividing circuit for generating a second gradation voltage group.

The sixth invention is the first invention or the second invention,
The video signal line drive circuit includes a drive video signal generation circuit that generates the plurality of video signals based on an image signal sent from the outside,
The drive video signal generation circuit includes:
When the potential of the common electrode is set to the voltage level of the low potential, based on a first reference voltage for setting the potential indicated by the plurality of video signals to a potential higher than the potential of the common electrode. Generating the plurality of video signals;
When the potential of the common electrode is set to the high potential voltage level, based on a second reference voltage for setting the potential indicated by the plurality of video signals to a potential lower than the potential of the common electrode. The plurality of video signals are generated.

According to a seventh invention, in the first to sixth inventions,
The display unit, the video signal line driving circuit, the scanning signal line driving circuit, and the common electrode driving circuit are provided on the same substrate.

The eighth invention is an active matrix type liquid crystal display device,
Any one of the drive circuits of the first to seventh inventions;
A display control circuit for controlling the drive circuit,
The common electrode drive circuit sets the potential of the common electrode to a voltage level of the power supply using the power supply of the display control circuit as a power supply for the external control circuit.

According to a ninth aspect of the present invention, a plurality of video signal lines for respectively transmitting a plurality of video signals representing images to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of video signals A plurality of switch elements arranged in a matrix corresponding to intersections of the lines and the plurality of scanning signal lines, a plurality of pixel electrodes respectively connected to the plurality of switch elements, and the plurality of pixel electrodes. A display panel of a display device for displaying the image, comprising a plurality of pixel electrodes provided in common and a common electrode forming a predetermined capacitance,
A video signal line driving circuit for supplying the plurality of video signals to the plurality of video signal lines, a scanning signal line driving circuit for selectively driving the plurality of scanning signal lines, and a common electrode for driving the common electrode Drive circuit,
The common electrode drive circuit alternately sets the potential of the common electrode to a high potential voltage level and a low potential voltage level supplied from a power supply for an external control circuit at a predetermined cycle. To do.

According to a tenth aspect of the present invention, a plurality of video signal lines for respectively transmitting a plurality of video signals representing images to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of video signals A plurality of switch elements arranged in a matrix corresponding to intersections of the lines and the plurality of scanning signal lines, a plurality of pixel electrodes respectively connected to the plurality of switch elements, and the plurality of pixel electrodes. A display panel of a display device for displaying the image, comprising the plurality of pixel electrodes provided in common and a common electrode forming a predetermined capacitance,
The potential of the common electrode is alternately set at a predetermined cycle between a high potential voltage level and a low potential voltage level supplied from a power supply for an external control circuit,
The potentials indicated by the plurality of video signals are:
When the potential of the common electrode is set to the high potential voltage level, it is set to a potential lower than the potential of the common electrode,
When the potential of the common electrode is set to the voltage level of the low potential, it is set to a potential higher than the potential of the common electrode,
The upper limit value of the potential indicated by the plurality of video signals set to a potential higher than the potential of the common electrode is the upper limit value of the potential indicated by the plurality of video signals set to a potential lower than the potential of the common electrode. Higher than
The lower limit value of the potential indicated by the plurality of video signals set to a potential higher than the potential of the common electrode is the lower limit value of the potential indicated by the plurality of video signals set to a potential lower than the potential of the common electrode. It is characterized by being lower than.

In an eleventh aspect based on the tenth aspect,
A video signal line driving circuit that sets potentials indicated by the plurality of video signals and supplies the plurality of video signals to the plurality of video signal lines, and a scanning signal line driving circuit that selectively drives the plurality of scanning signal lines. And a common electrode driving circuit for setting the potential of the common electrode and driving the common electrode,
The display panel, the video signal line driving circuit, the scanning signal line driving circuit, and the common electrode driving circuit are provided on the same substrate.

In a twelfth aspect, a plurality of video signal lines for respectively transmitting a plurality of video signals representing images to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, and the plurality of video signals A plurality of switch elements arranged in a matrix corresponding to intersections of the lines and the plurality of scanning signal lines, a plurality of pixel electrodes respectively connected to the plurality of switch elements, and the plurality of pixel electrodes. A common electrode provided in common with the plurality of pixel electrodes to form a predetermined capacitance; the plurality of video signal lines; the plurality of scanning signal lines; the plurality of switch elements; the plurality of pixel electrodes; and the common electrode. A display unit that displays the image, a video signal line driving circuit that supplies the plurality of video signals to the plurality of video signal lines, and a drive that selectively drives the plurality of scanning signal lines. A signal line driver circuit, a driving method of a display device and a common electrode driving circuit for driving the common electrode,
Setting the potential of the common electrode to a high potential voltage level supplied from a power source for an external control circuit;
Setting the potential of the common electrode to a low potential voltage level supplied from a power supply for an external control circuit.

In a thirteenth aspect based on the twelfth aspect,
Setting the potential indicated by the plurality of video signals to a potential lower than the potential of the common electrode when the potential of the common electrode is set to the high potential voltage level;
Setting the potential indicated by the plurality of video signals to a potential higher than the potential of the common electrode when the potential of the common electrode is set to the low potential voltage level;
The upper limit value of the potential indicated by the plurality of video signals set to a potential higher than the potential of the common electrode is the upper limit value of the potential indicated by the plurality of video signals set to a potential lower than the potential of the common electrode. Higher than
The lower limit value of the potential indicated by the plurality of video signals set to a potential higher than the potential of the common electrode is the lower limit value of the potential indicated by the plurality of video signals set to a potential lower than the potential of the common electrode. It is characterized by being lower than.

  According to the first aspect, the potential of the common electrode is set to the voltage level of the power supply voltage for the external control circuit. This eliminates the need for a circuit for boosting the voltage level of the power supply voltage and a circuit for stepping down the voltage level after the boosting to the potential of the common electrode. As a result, a power supply circuit such as a DC / DC converter becomes unnecessary, and the circuit configuration is simplified. As a result, the cost can be reduced and the display device can be downsized, and the burden of circuit design and the like can be reduced. In addition, since it is only necessary to alternately set the potential of the common electrode to a high potential voltage level and a low potential voltage level supplied from a power supply for an external control circuit, a stable potential can be obtained, Power consumption is also reduced as compared with the prior art.

  According to the second aspect of the invention, the potential indicated by the video signal is set so as to have an opposite phase to the potential of the common electrode. Here, since the potential of the common electrode is set to the voltage level of the power supply voltage for the external control circuit, the amplitude of the potential of the common electrode is smaller than the configuration in which the conventional common electrode is AC driven, The power consumption for driving the common electrode is reduced. In addition, since the amplitude of the potential indicated by the video signal is reduced as compared with the conventional configuration in which the potential of the common electrode is constant, power consumption for generating the video signal is reduced. Thus, a stable potential of the common electrode can be obtained with a simple circuit configuration without increasing power consumption.

  According to the third aspect of the invention, a voltage as a video signal is selected from two types of gradation voltage groups composed of a plurality of voltages showing different gradations, and the voltage is applied to the video signal line. Thereby, the video signal can be applied to the video signal line according to the voltage level set to the potential of the common electrode.

  According to the fourth aspect of the invention, two types of gradation voltage groups are generated by the voltage dividing circuit. For this reason, the drive circuit which has an effect of the above-mentioned 3rd invention is realized by the simple composition conventionally known.

  According to the fifth aspect of the invention, two types of gradation voltage groups are generated by the two voltage dividing circuits of the first voltage dividing circuit and the second voltage dividing circuit. Since the length of each voltage dividing circuit may be shorter than the length of the voltage dividing circuit of the fourth invention, the layout area of the voltage dividing circuit as a whole can be reduced.

  According to the sixth aspect, the video signal is generated by the driving video signal generation circuit based on two different reference voltages. Thereby, the video signal can be applied to the video signal line according to the voltage level set to the potential of the common electrode.

  According to the seventh aspect, the display unit, the video signal line driving circuit, the scanning signal line driving circuit, and the common electrode driving circuit are provided on the same substrate. Thus, a drive circuit that achieves the same effects as the first to sixth inventions and can be miniaturized is realized.

  According to the eighth aspect of the invention, an active matrix liquid crystal display device that achieves the effects of the first to seventh aspects of the invention is realized.

  According to the ninth aspect, in the display panel of the display device, the potential of the common electrode is set to the voltage level of the power supply voltage for the external control circuit. This eliminates the need for a circuit for boosting the voltage level of the power supply voltage and a circuit for stepping down the voltage level after the boosting to the potential of the common electrode. As a result, a power supply circuit such as a DC / DC converter becomes unnecessary, and the circuit configuration is simplified. As a result, the cost can be reduced and the display device can be downsized, and the burden of circuit design and the like can be reduced. In addition, since it is only necessary to alternately set the potential of the common electrode to a high potential voltage level and a low potential voltage level supplied from a power supply for an external control circuit, a stable potential can be obtained, Power consumption is also reduced as compared with the prior art.

  According to the tenth aspect of the invention, in the display panel of the display device configured to AC drive the common electrode, the potential of the common electrode is set to the voltage level of the power supply voltage for the external control circuit. This eliminates the need for a circuit for boosting the voltage level of the power supply voltage and a circuit for stepping down the voltage level of the boosted voltage to the common electrode potential. As a result, a power supply circuit such as a DC / DC converter becomes unnecessary, and the circuit configuration is simplified. As a result, the cost can be reduced and the display device can be downsized, and the burden of circuit design and the like can be reduced. In addition, since it is only necessary to alternately set the potential of the common electrode to a high potential voltage level and a low potential voltage level supplied from a power supply for an external control circuit, a stable potential can be obtained, Power consumption is also reduced as compared with the prior art.

  According to the eleventh aspect, the display panel, the video signal line driving circuit, the scanning signal line driving circuit, and the common electrode driving circuit are provided on the same substrate. Thus, the display panel of the display device that achieves the same effect as that of the tenth aspect and can be miniaturized is realized.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
<1. First Embodiment>
<1.1 Overall Configuration and Operation of Liquid Crystal Display>
FIG. 1 is a block diagram showing the overall configuration of an active matrix liquid crystal display device according to a first embodiment of the present invention. The liquid crystal display device includes a power supply 100, a display control circuit 200, and a display panel 600. The display panel 600 includes a source driver (video signal line driving circuit) 300, a gate driver (scanning signal line driving circuit) 400, a common driver (common electrode driving circuit) 500, a plurality of video signal lines 30, and a plurality of scanning signal lines 40. And a structure called a monolithic type in which a drive circuit is formed on a substrate constituting the display panel 600. A TFT 61 is provided corresponding to each of the intersections of the plurality of video signal lines 30 and the plurality of scanning signal lines 40, and the TFT 61 is connected to the pixel electrode 62. A common electrode 700 is provided to face the pixel electrode 62.

  The power supply 100 outputs a predetermined voltage. In this embodiment, a voltage of 2.7 V (hereinafter referred to as “high potential side power supply voltage”) VDD and a voltage of 0 V (ground potential) (hereinafter referred to as “low potential side power supply voltage”) VSS are the power supplies. 100. The display control circuit 200 receives image data Dv sent from the outside, a digital image signal Da, a source start pulse signal SSP, a source clock signal SCK, and a latch strobe signal for controlling the timing for displaying an image on the display panel 600. LS, gate start pulse signal GSP, first gate clock signal GCK1, and second gate clock signal GCK2, and first polarity inversion signal FRP1 and second polarity inversion signal FRP2 for setting common potential Vcom Is output. The source driver 300 includes a digital image signal Da, a source start pulse signal SSP, a source clock signal SCK, a latch strobe signal LS, a first gate clock signal GCK1, and a second gate clock signal GCK2 output from the display control circuit 200. In order to drive the display panel 600, a driving video signal is applied to each video signal line 30. The gate driver 400 sequentially selects the scanning signal lines 40 one horizontal scanning period at a time in accordance with the gate start pulse signal GSP, the first gate clock signal GCK1, and the second gate output from the display control circuit 200. Based on the clock signal GCK2, the application of the active scanning signal to each scanning signal line 40 is repeated with one vertical scanning period as a cycle. Based on the first polarity inversion signal FRP1 and the second polarity inversion signal FRP2 output from the display control circuit 200, the common driver 500 sets the high potential side power supply voltage VDD and the low potential side power supply voltage VSS to a predetermined level. The signals are sequentially output in a cycle to set the common potential Vcom.

<1.2 Configuration and operation of common driver>
FIG. 2 is a configuration diagram of the common driver 500 in the present embodiment. The common driver 500 includes four input terminals 51 to 54, one output terminal 55, a first switch circuit 56, and a second switch circuit 57. The first polarity inversion signal FRP1, the high potential side power supply voltage VDD, the low potential side power supply voltage VSS, and the second polarity inversion signal FRP2 are input to the input terminals 51 to 54, respectively. On the other hand, a voltage signal indicating the common potential Vcom is output from the output terminal 55. The first switch circuit 56 receives the high potential side power supply voltage VDD, the first polarity inversion signal FRP1, and the second polarity inversion signal FRP2. When the first polarity inversion signal FRP1 is at the high level and the second polarity inversion signal FRP2 is at the low level, the high potential side power supply voltage VDD is output from the first switch circuit 56. The second switch circuit 57 receives the low-potential-side power supply voltage VSS, the first polarity inversion signal FRP1, and the second polarity inversion signal FRP2. When the first polarity inversion signal FRP1 is at a low level and the second polarity inversion signal FRP2 is at a high level, the low potential side power supply voltage VSS is output from the second switch circuit 57.

  FIG. 3 is a signal waveform diagram in the common driver 500. As described above, in the present embodiment, a voltage of 2.7 V is input to the common driver 500 as the high potential side power supply voltage VDD, and a voltage of 0 V is input as the low potential side power supply voltage VSS. Further, a first polarity inversion signal FRP1 and a second polarity inversion signal FRP2 in which the voltage level on the high potential (high level) side is 8.2V and the voltage level on the low potential (low level) side is −4.7V. Is input to the common driver 500. As shown in FIG. 3, the first polarity inversion signal FRP1 and the second polarity inversion signal FRP2 are inverted every horizontal scanning period (1H) so as to have opposite polarities. Therefore, when the high potential side power supply voltage VDD is output from the first switch circuit 56 shown in FIG. 2, the low potential side power supply voltage VSS is not output from the second switch circuit 57. Further, when the low potential side power supply voltage VSS is output from the second switch circuit 57, the high potential side power supply voltage VDD is not output from the first switch circuit 56. As described above, when the first polarity inversion signal FRP1 is at the high level and the second polarity inversion signal FRP2 is at the low level, the common potential Vcom is set to 2.7 V that is the voltage level of the high potential side power supply voltage VDD. On the other hand, when the first polarity inversion signal FRP1 is at the low level and the second polarity inversion signal FRP2 is at the high level, the common potential Vcom is set to 0 V, which is the voltage level of the low potential side power supply voltage VSS.

<1.3 Configuration and operation of source driver>
FIG. 4 is a block diagram showing the configuration of the source driver 300 in this embodiment. The source driver 300 includes a shift register 31, a sampling / latch circuit 32, a first selection circuit 33, a second selection circuit 34, a buffer circuit 35, and a gradation voltage generation circuit 36. . The source start pulse signal SSP and the source clock signal SCK are input to the shift register 31, and the shift register 31 transmits each pulse included in the start pulse signal SSP from the input end to the output end based on these signals SSP and SCK. And transfer sequentially. In response to this transfer, sampling pulses are sequentially input to the sampling and latch circuit 32. The sampling / latch circuit 32 samples the digital image signal Da sent from the display control circuit 200 at the timing of these sampling pulses, and collectively outputs it as an internal image signal at the timing of the latch strobe signal LS.

  The gradation voltage generation circuit 36 is based on two kinds of reference voltages VH and VL given from a predetermined power supply circuit (not shown), and the voltage of the driving video signal when the polarity is positive with respect to the common potential Vcom. Grayscale voltage group (hereinafter referred to as “positive grayscale voltage group”) GVH and the grayscale voltage group (hereinafter referred to as the voltage of the video signal for driving when the polarity is negative with respect to the common potential Vcom). "Negative gray scale voltage group") GVL is output. The gradation voltage group for positive polarity (first gradation voltage group) GVH and the gradation voltage group for negative polarity (second gradation voltage group) GVL are, for example, 64 pieces corresponding to 64 gradation levels, respectively. Consists of voltage. The positive polarity grayscale voltage group GVH output from the grayscale voltage generation circuit 36 is input to the first selection circuit 33, and the negative polarity grayscale voltage group GVL is input to the second selection circuit 34. FIG. 5 is a configuration diagram of the gradation voltage generation circuit 36 in the present embodiment. The gradation voltage generating circuit 36 is configured by a voltage dividing circuit including a series of resistors connected in series called “R-STRING”. The gradation voltage generation circuit 36 divides the difference VH−VL between the reference voltages VH and VL input to both ends of the voltage dividing circuit, thereby dividing the positive gradation voltage group GVH and the negative gradation voltage. A group GVL is generated. In the present embodiment, the positive polarity gradation voltage group GVH is generated in the range of 1.5 to 4V, and the negative polarity gradation voltage group GVL is generated in the range of −1.3 to 1.2V.

  In the first selection circuit 33, one of the voltages of the positive polarity gradation voltage group GVH generated as described above is selected based on the internal image signal output from the sampling / latch circuit 32. Is output. The second selection circuit 34 selects one of the negative polarity gradation voltage groups GVL generated as described above based on the internal image signal output from the sampling / latch circuit 32. Is output. The buffer circuit 35 is based on the first gate clock signal GCK1 and the second gate clock signal GCK2 output from the display control circuit 200, or the voltage output from the first selection circuit 33 or the second selection circuit 34. Is selected and applied to each video signal line 30 as a drive video signal. The configuration of the buffer circuit 35 can be the same as that of the common driver 500 shown in FIG. 2, for example. That is, when the first gate clock signal GCK1 is at a high level and the second gate clock signal GCK2 is at a low level, the voltage output from the second selection circuit 34 is output from the buffer circuit 35, and the first gate clock signal When GCK1 is at low level and the second gate clock signal GCK2 is at high level, the voltage output from the first selection circuit 33 can be output from the buffer circuit 35.

<1.4 Action>
Next, the operation in this embodiment will be described. With the configuration and operation as described above, the relationship between the common potential Vcom and the source potential (potential indicated by the drive video signal) Vs is as shown in FIG. The common potential Vcom is set to the potential (2.7 V) of the high potential side power supply voltage VDD and the potential (0 V) of the low potential side power supply voltage VSS every horizontal scanning period. Here, when the common potential Vcom is set to 0 V, the grayscale voltage selected from the positive polarity grayscale voltage group GVH is output from the buffer circuit 35 as the drive video signal, so that the source potential Vs is 1 It will be in the range of 5-4V. On the other hand, when the common potential Vcom is set to 2.7 V, the grayscale voltage selected from the negative polarity grayscale voltage group GVL is output from the buffer circuit 35 as the drive video signal, so that the source potential Vs is It becomes the range of -1.3-1.2V. In the conventional example shown in FIG. 16, the potential difference between the common potential Vcom and the source potential Vs when displaying white is 1.5 V, and the potential difference between the common potential Vcom and the source potential Vs when displaying black is It was 4V. Also in the present embodiment, as shown in FIG. 6, a potential difference of 1.5 to 4 V can be generated between the common potential Vcom and the source potential Vs, and white display, black display, or an intermediate gray level thereof can be generated. Can be displayed.

<1.5 Effect>
As described above, according to the present embodiment, the voltage levels of the voltages (the high-potential-side power supply voltage VDD and the low-potential-side power supply voltage VSS) output from the power supply for the control circuit outside the drive circuit are the common potential Vcom. Set to Therefore, unlike the prior art, a power supply circuit such as a DC / DC converter for boosting the power supply voltage is not required, and the circuit configuration for generating the common potential Vcom is simplified. As a result, the cost can be reduced and the size of the display device can be reduced, and the burden required for circuit design and the like is reduced. In addition, with respect to generation of the common potential Vcom, conventionally, after boosting the power supply voltage by a DC / DC converter or the like, it is necessary to further step down the boosted voltage by the common driver 500. On the other hand, according to the present embodiment, it is only necessary to alternately set the common potential Vcom to the high potential side power supply voltage VDD and the low potential side power supply voltage VSS, so that it is possible to obtain a stable common potential Vcom as compared with the conventional case. Can do.

  The source potential Vs is set to have an opposite phase to the common potential Vcom. Here, since the amplitude of the common potential Vcom is small as compared with the configuration in which the common electrode 700 is AC driven, the power consumption for driving the common electrode 700 is small. The video signal line also needs to be AC driven. However, since the common electrode 700 is AC driven, it is not necessary to increase the amplitude of the source potential Vs as compared with the configuration in which the common potential Vcom is constant. For this reason, the structure which concerns on this embodiment is realizable, without increasing power consumption compared with the past.

<1.6 Modification>
Next, a modification of the above embodiment will be described. FIG. 7 is a configuration diagram of the gradation voltage generation circuit 36 in a modification of the above embodiment. As shown in FIGS. 7A and 7B, the gradation voltage generation circuit 36 includes two series of resistors connected in series called R-STRING. As shown in FIG. 7A, reference voltages VH1 and VL1 are input to both ends of one resistor (first voltage dividing circuit). Then, by dividing the reference voltages VH1 and VL1, a positive polarity gradation voltage group GVH composed of a plurality of gradation voltages in a range of 1.5 to 4V is generated. As shown in FIG. 7B, reference voltages VH2 and VL2 are input to both ends of the other resistor (second voltage dividing circuit). Then, by dividing the reference voltages VH2 and VL2, a negative polarity grayscale voltage group GVL composed of a plurality of grayscale voltages in the range of −1.3 to 1.2V is generated. The positive polarity gradation voltage group GVH is input to the first selection circuit 33 shown in FIG. 4, and the negative polarity gradation voltage group GVL is input to the second selection circuit 34 shown in FIG.

  According to this modification, four types of reference voltages VH1, VL1, VH2, and VL2 must be input to the gradation voltage generating circuit 36, but one voltage dividing circuit generates the positive-polarity gradation voltage group GVH. And the other voltage dividing circuit only needs to be able to generate the gradation voltage group GVL for negative polarity. Therefore, a configuration having two short resistors as compared with the above-described embodiment is sufficient, and the layout area of the circuit can be reduced. In addition, the power consumed by the resistor can be reduced.

<2. Second Embodiment>
<2.1 Configuration and operation of liquid crystal display device>
Next, a second embodiment of the present invention will be described. FIG. 8 is a block diagram showing the overall configuration of the active matrix liquid crystal display device according to the present embodiment. The liquid crystal display device includes a power supply 100, a display control circuit 200, and a display panel 600. The display panel 600 includes a source driver (video signal line driving circuit) 300, a gate driver (scanning signal line driving circuit) 400, a common driver (common electrode driving circuit) 500, a plurality of video signal lines 30, and a plurality of scanning signal lines 40. As in the first embodiment, the structure is called a monolithic type. A TFT 61 is provided corresponding to each of the intersections of the plurality of video signal lines 30 and the plurality of scanning signal lines 40, and the TFT 61 is connected to the pixel electrode 62. A common electrode 700 is provided to face the pixel electrode 62.

  The power supply 100 outputs a high potential side power supply voltage VDD of 2.7 V and a low potential side power supply voltage VSS of 0 V (ground potential). The display control circuit 200 receives image data Dv sent from the outside, and controls an analog image signal AV, a source start pulse signal SSP, a source clock signal SCK, and a gate start pulse for controlling the timing for displaying an image on the display panel 600. The signal GSP, the first gate clock signal GCK1, and the second gate clock signal GCK2, and a first switch control signal Ssw1 and a second switch for controlling a switch in a driving video signal generation circuit 38 to be described later The control signal Ssw2, the low potential side power supply voltage VSS, and the first polarity inversion signal FRP1 and the second polarity inversion signal FRP2 for setting the common potential Vcom are output. The source driver 300 includes an analog image signal AV output from the display control circuit 200, a source start pulse signal SSP, a source clock signal SCK, a first switch control signal Ssw1, a second switch control signal Ssw2, and a low potential side power source. The drive video signal is applied to each video signal line 30 in order to receive the voltage VSS and drive the display panel 600. The gate driver 400 sequentially selects the scanning signal lines 40 one horizontal scanning period at a time in accordance with the gate start pulse signal GSP, the first gate clock signal GCK1, and the second gate output from the display control circuit 200. Based on the clock signal GCK2, the application of the active scanning signal to each scanning signal line 40 is repeated with one vertical scanning period as a cycle. Based on the first polarity inversion signal FRP1 and the second polarity inversion signal FRP2 output from the display control circuit 200, the common driver 500 sets the high potential side power supply voltage VDD and the low potential side power supply voltage VSS to a predetermined level. The signals are sequentially output in a cycle to set the common potential Vcom.

<2.2 Source driver configuration and operation>
FIG. 9 is a block diagram showing a configuration of the source driver 300 in the present embodiment. Unlike the first embodiment, the source driver 300 in the present embodiment is a drive circuit called an analog driver that receives an analog signal from the outside as an image signal. The source driver 300 includes a shift register 31, an output circuit 37, and a driving video signal generation circuit 38. The source start pulse signal SSP and the source clock signal SCK are input to the shift register 31, and the shift register 31 transmits each pulse included in the start pulse signal SSP from the input end to the output end based on these signals SSP and SCK. And transfer sequentially. In response to this transfer, sampling pulses are sequentially input to the output circuit 37. The driving video signal generation circuit 38 includes an analog image signal AV output from the display control circuit 200, a first switch control signal Ssw1, a second switch control signal Ssw2, a low potential side power supply voltage VSS, and a predetermined power supply circuit. Two types of reference voltages Vref1 and Vref2 given from (not shown) are received, and a driving video signal is generated. The output circuit 37 includes an analog switch (not shown) corresponding to each video signal line, and the analog switches are sequentially turned on in accordance with the sampling pulse. When the analog switches are sequentially turned on, the driving video signals output from the driving video signal generation circuit 38 are sequentially output to the video signal lines.

<2.3 Configuration and Operation of Driving Video Signal Generation Circuit>
Next, a detailed configuration and operation of the drive video signal generation circuit 38 will be described. FIG. 10 is a configuration diagram of the drive video signal generation circuit 38 in the present embodiment. The drive video signal generation circuit 38 includes five input terminals 81 to 85, one output terminal 86, seven switches SW1 to SW7, an operational amplifier 87, and a capacitor C. The inverting terminal of the operational amplifier 87 is connected to the input terminal 81 via the capacitor C and the switch SW1, and is connected to the input terminal 82 via the capacitor C and the switch SW2. One end 91 of the capacitor C is connected to the output terminal 86 via the switch SW7, and the other end 92 is connected to the output terminal 86 via the switch SW6. The non-inverting terminal of the operational amplifier 87 is connected to the input terminal 83 through the switch SW3, the input terminal 84 through the switch SW4, and the input terminal 85 through the switch SW5.

  The first reference voltage Vref1, the low potential power supply voltage VSS, the analog image signal Vin (AV), the second reference voltage Vref2, and the low potential power supply voltage VSS are input to the input terminals 81 to 85, respectively. On the other hand, a driving video signal Vout applied to the video signal line 30 is output from the output terminal 86. The first reference voltage Vref1 is a voltage that serves as a reference when generating a driving video signal whose polarity should be positive with respect to the common potential Vcom (hereinafter referred to as a “positive driving video signal”). It is. The second reference voltage Vref2 is a voltage that serves as a reference when generating a driving video signal whose polarity should be negative with respect to the common potential Vcom (hereinafter referred to as a “negative driving video signal”). It is. The first reference voltage Vref1 and the second reference voltage Vref2 are supplied from a predetermined power supply circuit (not shown).

  Here, in the operational amplifier 87 as shown in FIG. 10, an error generally occurs between the actually output voltage and the ideal output voltage. In an ideal operational amplifier, for example, if the input voltage is 0V, the output voltage is also 0V. However, the actual output voltage is not 0V. Such a voltage error between the actual output voltage and the ideal output voltage is called an “offset voltage”. Further, removing the influence of the offset voltage from the output voltage is called “offset cancellation”. In the present embodiment, the drive video signal generation circuit 38 has a function for canceling the offset, and operates as described later, thereby driving the positive drive video signal as shown in FIG. And the negative driving video signal are output from the driving video signal generation circuit 38.

  FIG. 11 is a signal waveform diagram showing on / off operation timings of the switches SW1 to SW7 in the drive video signal generation circuit 38. Each of the switches SW1 to SW7 operates as follows based on the first switch control signal Ssw1 and the second switch control signal Ssw2. The switches SW1 and SW5 are turned on when the first switch control signal Ssw1 is at a high level, and are turned off when the first switch control signal Ssw1 is at a low level. The switches SW2 and SW4 are turned on when the second switch control signal Ssw2 is at a high level, and are turned off when the second switch control signal Ssw2 is at a low level. The switch SW6 is turned on when the first switch control signal Ssw1 or the second switch control signal Ssw2 is at a high level, and is turned off at other times. The switches SW3 and SW7 are turned on when both the first switch control signal Ssw1 and the second switch control signal Ssw2 are at a low level, and are turned off at other times.

  During the period indicated by the symbol T1, the first switch control signal Ssw1 is at a high level and the second switch control signal Ssw2 is at a low level. Accordingly, the switches SW1, SW5, and SW6 among the switches SW1 to SW7 are turned on. During the period indicated by the symbol T2, both the first switch control signal Ssw1 and the second switch control signal Ssw2 are at a low level. Thereby, the switches SW3 and SW7 among the switches SW1 to SW7 are turned on. During the period indicated by the symbol T3, the first switch control signal Ssw1 is at a low level, and the second switch control signal Ssw2 is at a high level. As a result, among the switches SW1 to SW7, the switches SW2, SW4, and SW6 are turned on. During the period indicated by the symbol T4, both the first switch control signal Ssw1 and the second switch control signal Ssw2 are at a low level. Thereby, the switches SW3 and SW7 among the switches SW1 to SW7 are turned on.

  FIGS. 12 and 13 are diagrams for explaining the operation when the drive video signal generation circuit 38 outputs the drive video signal for the positive polarity. 11, the common potential Vcom changes from the voltage level of the high-potential-side power supply voltage VDD to the voltage level of the low-potential-side power supply voltage VSS, and the on / off states of the switches SW1 to SW7 are as shown in FIG. It becomes as shown in. At this time, the switch SW1 is in the on state and the switches SW2 and SW7 are in the off state, so that the potential at the connection point 91 becomes the voltage level of the first reference voltage Vref1. In addition, since only the switch SW5 among the switches SW3, SW4, and SW5 is in the on state, 0 V (low potential side power supply voltage VSS) is input to the non-inverting terminal of the operational amplifier 87. Further, since the switch SW6 is in the on state, the potential at the connection point 92 is obtained by adding 0 V (low potential side power supply voltage VSS) and the offset voltage Voff. Therefore, the offset voltage Voff is input to the inverting terminal of the operational amplifier 87. In addition, the capacitor C stores electric charge based on the potential difference between the first reference voltage Vref1 and the offset voltage Voff.

  In the period indicated by symbol T2 in FIG. 11, the on / off states of the switches SW1 to SW7 are as shown in FIG. At this time, since only the switch SW3 among the switches SW3, SW4, and SW5 is in the on state, the analog image signal Vin output from the display control circuit 200 is input to the non-inverting terminal of the operational amplifier 87. Further, the voltage Vin + Voff obtained by adding the voltage indicated by the analog image signal Vin and the offset voltage Voff is input to the inverting terminal of the operational amplifier 87. As described above, the capacitor C has the first reference voltage Vref1 and the offset voltage. Charges are stored based on the difference from Voff. As a result, the voltage output from the operational amplifier 87 is Vin + Voff + Vref1−Voff. Therefore, the potential of the driving video signal Vout output from the output terminal 86 is Vin + Vref1.

  FIG. 14 and FIG. 15 are diagrams for explaining the operation when the drive video signal generation circuit 38 outputs the drive video signal for the negative polarity. 11, the common potential Vcom changes from the voltage level of the low-potential-side power supply voltage VSS to the voltage level of the high-potential-side power supply voltage VDD, and the on / off states of the switches SW1 to SW7 are as shown in FIG. It becomes as shown in. At this time, the switch SW2 is in the on state and the switches SW1 and SW7 are in the off state, so that the potential at the connection point 91 is 0 V (low potential side power supply voltage VSS). Further, since only the switch SW4 among the switches SW3, SW4, and SW5 is in the on state, the second reference voltage Vref2 is input to the non-inverting terminal of the operational amplifier 87. Further, since the switch SW6 is in the on state, the potential at the connection point 92 is the sum of the second reference voltage Vref2 and the offset voltage Voff. Therefore, the voltage Vref2 + Voff obtained by adding the second reference voltage Vref2 and the offset voltage Voff is input to the inverting terminal of the operational amplifier 87. As described above, since the potential at the connection point 91 is 0 V, charges are stored in the capacitor C based on the voltage Vref2 + Voff.

  In the period indicated by reference numeral T4 in FIG. 11, the on / off states of the switches SW1 to SW7 are as shown in FIG. At this time, since only the switch SW3 among the switches SW3, SW4, and SW5 is in the on state, the analog image signal Vin output from the display control circuit 200 is input to the non-inverting terminal of the operational amplifier 87. Further, the voltage Vin + Voff obtained by adding the voltage indicated by the analog image signal Vin and the offset voltage Voff is input to the inverting terminal of the operational amplifier 87. As described above, charges are stored in the capacitor C based on the voltage Vref2 + Voff. ing. As a result, the voltage output from the operational amplifier 87 is Vin + Voff− (Vref2 + Voff). Therefore, the potential of the driving video signal Vout output from the output terminal 86 is Vin−Vref2.

  By switching the on / off states of the switches SW1 to SW7 as described above, the driving video signals (positive polarity driving video signal and negative polarity driving video are set to have a phase opposite to the common potential Vcom. Signal) is output from the drive video signal generation circuit 38.

<2.4 Action and effect>
Next, functions and effects in the present embodiment will be described. With the configuration and operation as described above, the relationship between the common potential Vcom and the source potential Vs is as shown in FIG. 6 as in the first embodiment. Here, when the common potential Vcom is set to 0V, the positive driving video generated based on the analog image signal AV (Vin) output from the display control circuit 200 and the first reference voltage Vref1. A signal is output from the drive video signal generation circuit 38. On the other hand, when the common potential Vcom is set to 2.7 V, the negative polarity driving for the negative polarity generated based on the analog image signal AV (Vin) output from the display control circuit 200 and the second reference voltage Vref2. The video signal is output from the driving video signal generation circuit 38. As a result, the video signal for driving at the positive polarity and the video signal for driving at the negative polarity can be generated with one image signal. Therefore, when generating the driving video signal as shown in FIG. It is no longer necessary to generate both the driving video signal for the selection circuit and the driving video signal for the second selection circuit, and the area of the resistor layout can be reduced. Loss power consumption can be reduced. Also in this embodiment, a predetermined potential difference can be generated between the common potential Vcom and the source potential Vs, and white display, black display, or display of intermediate gray levels thereof can be performed.

  According to the present embodiment, since the configuration for generating the common potential Vcom is the same as that of the first embodiment, a power supply circuit such as a DC / DC converter is not necessary. Therefore, the circuit configuration for generating the common potential Vcom becomes simple, and the cost can be reduced and the display device can be downsized. In addition, as in the first embodiment, it is possible to obtain a stable common potential Vcom. For the drive video signal, the drive video signal generation circuit 38 in the source driver 300 generates two types of drive video signals, a positive polarity drive video signal and a negative polarity drive video signal, at a predetermined cycle. It is generated alternately. This makes it possible to generate a driving video signal having an amplitude as shown in FIG. 6, and a sufficiently high voltage can be applied to the liquid crystal layer. In this way, by providing the driving video signal generation circuit 38 between the outside of the driving circuit and the output circuit 37, the present invention can be applied to a digital driver that receives a digital signal from the outside.

1 is a block diagram illustrating a configuration of an active matrix liquid crystal display device according to a first embodiment of the present invention. It is a circuit diagram which shows the structure of the common driver in the said 1st Embodiment. It is a signal waveform diagram of the common driver in the first embodiment. It is a block diagram which shows the structure of the source driver in the said 1st Embodiment. It is a block diagram of the gradation voltage generation circuit in the said 1st Embodiment. FIG. 4 is a diagram illustrating a relationship between a common potential and a source potential in the first embodiment. It is a circuit diagram which shows the structure of the gradation voltage generation circuit in a modification. It is a block diagram which shows the structure of the active matrix type liquid crystal display device which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the source driver in the said 2nd Embodiment. It is a circuit diagram which shows the structure of the drive video signal generation circuit in the said 2nd Embodiment. FIG. 10 is a signal waveform diagram for explaining the operation of the drive video signal generation circuit in the second embodiment. FIG. 10 is a diagram for describing an operation of a driving video signal generation circuit in the second embodiment. FIG. 10 is a diagram for describing an operation of a driving video signal generation circuit in the second embodiment. FIG. 10 is a diagram for describing an operation of a driving video signal generation circuit in the second embodiment. FIG. 10 is a diagram for describing an operation of a driving video signal generation circuit in the second embodiment. In a prior art example, it is a figure which shows the relationship between a common potential and a source potential. FIG. 10 is a block diagram showing a configuration for generating a common potential in a conventional example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 31 ... Shift register 32 ... Sampling latch circuit 33 ... 1st selection circuit 34 ... 2nd selection circuit 35 ... Buffer circuit 36 ... Gradation voltage generation circuit 37 ... Output circuit 38 ... Drive video signal generation circuit 100 ... Power supply DESCRIPTION OF SYMBOLS 200 ... Display control circuit 300 ... Source driver 400 ... Gate driver 500 ... Common driver 600 ... Display panel 700 ... Common electrode Vcom ... Common potential VDD ... High potential side power supply voltage VSS ... Low potential side power supply voltage

Claims (13)

A plurality of video signal lines for respectively transmitting a plurality of video signals representing an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines and the plurality of scannings A plurality of switch elements arranged in a matrix corresponding to the intersections with the signal lines, a plurality of pixel electrodes respectively connected to the plurality of switch elements, and provided in common to the plurality of pixel electrodes, A drive circuit of a display device comprising a display unit that includes a plurality of pixel electrodes and a common electrode that forms a predetermined capacitance and displays the image,
A video signal line driving circuit for supplying the plurality of video signals to the plurality of video signal lines, a scanning signal line driving circuit for selectively driving the plurality of scanning signal lines, and a common electrode for driving the common electrode Drive circuit,
The common electrode drive circuit alternately sets the potential of the common electrode to a high potential voltage level and a low potential voltage level supplied from a power source for an external control circuit at a predetermined cycle. Drive circuit. The video signal line driving circuit includes:
When the potential of the common electrode is set to the high potential voltage level, the potential indicated by the plurality of video signals is set to a potential lower than the potential of the common electrode,
When the potential of the common electrode is set to the low potential voltage level, the potential indicated by the plurality of video signals is set to a potential higher than the potential of the common electrode,
The upper limit value of the potential indicated by the plurality of video signals set to a potential higher than the potential of the common electrode is the upper limit value of the potential indicated by the plurality of video signals set to a potential lower than the potential of the common electrode. Higher than
The lower limit value of the potential indicated by the plurality of video signals set to a potential higher than the potential of the common electrode is the lower limit value of the potential indicated by the plurality of video signals set to a potential lower than the potential of the common electrode. The driving circuit according to claim 1, wherein the driving circuit is lower than the driving circuit. The video signal line driving circuit includes:
A first gradation voltage group composed of a plurality of voltages showing different gradations, and a second gradation voltage group composed of a plurality of voltages corresponding to each of the plurality of voltages included in the first gradation voltage group; A gradation voltage generating circuit that outputs
When the potential of the common electrode is set to the high potential voltage level, a voltage selected from the second gradation voltage group is supplied to the video signal line as the video signal,
When the potential of the common electrode is set to the voltage level of the low potential, a voltage selected from the first gradation voltage group is supplied to the video signal line as the video signal. The drive circuit according to claim 1. The gradation voltage generation circuit is constituted by a voltage dividing circuit including a plurality of resistors connected in series with each other,
4. The drive circuit according to claim 3, wherein the voltage dividing circuit generates the first gradation voltage group and the second gradation voltage group.   The gradation voltage generating circuit includes a plurality of resistors connected in series, a first voltage dividing circuit that generates the first gradation voltage group, and a plurality of resistors connected in series. The drive circuit according to claim 3, wherein the drive circuit is configured by a second voltage dividing circuit that generates a second gradation voltage group. The video signal line drive circuit includes a drive video signal generation circuit that generates the plurality of video signals based on an image signal sent from the outside,
The drive video signal generation circuit includes:
When the potential of the common electrode is set to the voltage level of the low potential, based on a first reference voltage for setting the potential indicated by the plurality of video signals to a potential higher than the potential of the common electrode. Generating the plurality of video signals;
When the potential of the common electrode is set to the high potential voltage level, based on a second reference voltage for setting the potential indicated by the plurality of video signals to a potential lower than the potential of the common electrode. The drive circuit according to claim 1, wherein the plurality of video signals are generated.   The display unit, the video signal line driving circuit, the scanning signal line driving circuit, and the common electrode driving circuit are provided on the same substrate. The drive circuit according to the item. An active matrix liquid crystal display device,
The drive circuit according to any one of claims 1 to 7,
A display control circuit for controlling the drive circuit,
The common electrode driving circuit sets the potential of the common electrode to the voltage level of the power supply using the power supply of the display control circuit as the power supply for the external control circuit. . A plurality of video signal lines for respectively transmitting a plurality of video signals representing an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines and the plurality of scannings A plurality of switch elements arranged in a matrix corresponding to intersections with the signal lines, a plurality of pixel electrodes respectively connected to the plurality of switch elements, and provided in common to the plurality of pixel electrodes, A display panel of a display device for displaying the image, comprising a plurality of pixel electrodes and a common electrode forming a predetermined capacity,
A video signal line driving circuit for supplying the plurality of video signals to the plurality of video signal lines, a scanning signal line driving circuit for selectively driving the plurality of scanning signal lines, and a common electrode for driving the common electrode Drive circuit,
The common electrode drive circuit alternately sets the potential of the common electrode to a high potential voltage level and a low potential voltage level supplied from a power supply for an external control circuit at a predetermined cycle. Display panel. A plurality of video signal lines for respectively transmitting a plurality of video signals representing an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines and the plurality of scannings A plurality of switch elements arranged in a matrix corresponding to intersections with the signal lines, a plurality of pixel electrodes respectively connected to the plurality of switch elements, and provided in common to the plurality of pixel electrodes, A display panel of a display device for displaying the image, comprising a plurality of pixel electrodes and a common electrode forming a predetermined capacity,
The potential of the common electrode is alternately set at a predetermined cycle between a high potential voltage level and a low potential voltage level supplied from a power supply for an external control circuit,
The potentials indicated by the plurality of video signals are:
When the potential of the common electrode is set to the high potential voltage level, it is set to a potential lower than the potential of the common electrode,
When the potential of the common electrode is set to the voltage level of the low potential, it is set to a potential higher than the potential of the common electrode,
The upper limit value of the potential indicated by the plurality of video signals set to a potential higher than the potential of the common electrode is the upper limit value of the potential indicated by the plurality of video signals set to a potential lower than the potential of the common electrode. Higher than
The lower limit value of the potential indicated by the plurality of video signals set to a potential higher than the potential of the common electrode is the lower limit value of the potential indicated by the plurality of video signals set to a potential lower than the potential of the common electrode. Display panel, characterized by being lower than. A video signal line driving circuit that sets potentials indicated by the plurality of video signals and supplies the plurality of video signals to the plurality of video signal lines, and a scanning signal line driving circuit that selectively drives the plurality of scanning signal lines. And a common electrode driving circuit for setting the potential of the common electrode and driving the common electrode,
The display panel according to claim 10, wherein the display panel, the video signal line driving circuit, the scanning signal line driving circuit, and the common electrode driving circuit are provided on the same substrate. A plurality of video signal lines for respectively transmitting a plurality of video signals representing an image to be displayed, a plurality of scanning signal lines intersecting with the plurality of video signal lines, the plurality of video signal lines and the plurality of scannings A plurality of switch elements arranged in a matrix corresponding to intersections with the signal lines, a plurality of pixel electrodes respectively connected to the plurality of switch elements, and provided in common to the plurality of pixel electrodes, A plurality of pixel electrodes and a common electrode forming a predetermined capacitance; the plurality of video signal lines; the plurality of scanning signal lines; the plurality of switch elements; the plurality of pixel electrodes; and the common electrode. A display unit for displaying; a video signal line driving circuit for supplying the plurality of video signals to the plurality of video signal lines; and a scanning signal line driving circuit for selectively driving the plurality of scanning signal lines. , A method of driving a display device and a common electrode driving circuit for driving the common electrode,
Setting the potential of the common electrode to a high potential voltage level supplied from a power source for an external control circuit;
And setting the potential of the common electrode to a low potential voltage level supplied from a power supply for an external control circuit. Setting the potential indicated by the plurality of video signals to a potential lower than the potential of the common electrode when the potential of the common electrode is set to the high potential voltage level;
Setting the potential indicated by the plurality of video signals to a potential higher than the potential of the common electrode when the potential of the common electrode is set to the low potential voltage level;
The upper limit value of the potential indicated by the plurality of video signals set to a potential higher than the potential of the common electrode is the upper limit value of the potential indicated by the plurality of video signals set to a potential lower than the potential of the common electrode. Higher than
The lower limit value of the potential indicated by the plurality of video signals set to a potential higher than the potential of the common electrode is the lower limit value of the potential indicated by the plurality of video signals set to a potential lower than the potential of the common electrode. The driving method according to claim 12, wherein the driving method is lower.

Images