JP2006186035A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP2006186035A
JP2006186035A JP2004376618A JP2004376618A JP2006186035A JP 2006186035 A JP2006186035 A JP 2006186035A JP 2004376618 A JP2004376618 A JP 2004376618A JP 2004376618 A JP2004376618 A JP 2004376618A JP 2006186035 A JP2006186035 A JP 2006186035A
Authority
JP
Japan
Prior art keywords
semiconductor device
electrode plate
casing
electrode
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2004376618A
Other languages
Japanese (ja)
Other versions
JP4424199B2 (en
Inventor
Sukeyuki Furukawa
資之 古川
Akihiro Shibuya
彰弘 渋谷
Mikio Naruse
幹夫 成瀬
Yasuhiro Okada
安弘 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissan Motor Co Ltd
Original Assignee
Nissan Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissan Motor Co Ltd filed Critical Nissan Motor Co Ltd
Priority to JP2004376618A priority Critical patent/JP4424199B2/en
Publication of JP2006186035A publication Critical patent/JP2006186035A/en
Application granted granted Critical
Publication of JP4424199B2 publication Critical patent/JP4424199B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

Landscapes

  • Die Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of dispensing with separate provision of an external terminal and of reducing the number of components and the number of assembling processes. <P>SOLUTION: Semiconductor chips 2, 3 are accommodated in an accommodation space formed with an upper casing 4 and a lower casing 5. The upper casing 4 is formed by insert molding an electrode plate 41 with insulating resin, and a frame member 42 and the electrode plate 41 are integrated. In the same fashion, the lower casing 5 is also formed by insert molding an electrode plate 51 with insulating resin, and a frame member 52 and the electrode plate 51 are integrated. A module 1 is formed by soldering the semiconductor chips 2, 3 onto the electrode plate 51, placing contact electrodes 8 on the semiconductor chips 2, 3 respectively, covering the lower casing 5 with the upper casing 4, and joining the frame members 42, 52 using an adhesive or the like while pressurizing the electrode plates 41, 51 from upper and lower. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、加圧接触型の半導体装置に関する。   The present invention relates to a pressure contact type semiconductor device.

絶縁ゲートバイポーラ型トランジスタ(IGBT)は、パワースイッチングデバイスとして例えば電気自動車のインバータ素子として用いられている。このようなIGBT等の半導体チップをパッケージに組み込んでモジュール化した半導体装置では、放熱性向上や内部配線インダクタンスの抑制を図るために加圧接触型構造としたものが提案されている(例えば、特許文献1参照)。   An insulated gate bipolar transistor (IGBT) is used as a power switching device, for example, as an inverter element of an electric vehicle. In a semiconductor device in which a semiconductor chip such as an IGBT is incorporated into a package to form a module, a pressure contact type structure has been proposed in order to improve heat dissipation and suppress internal wiring inductance (for example, patents). Reference 1).

IGBTではチップ表裏両面に電極が形成されており、特許文献1に記載の加圧接触型半導体装置においては、二つの電極板で半導体チップを挟持して加圧することによりチップ電極との圧接を行っている。半導体装置には、半導体チップを囲むようにセラミックから成る絶縁外筒が設けられており、上下電極板の周縁部分は絶縁外筒の上下端面にそれぞれ接合されている。   In the IGBT, electrodes are formed on both front and back surfaces of the chip. In the pressure contact type semiconductor device described in Patent Document 1, the semiconductor chip is sandwiched between two electrode plates and pressed to perform pressure contact with the chip electrode. ing. The semiconductor device is provided with an insulating outer cylinder made of ceramic so as to surround the semiconductor chip, and the peripheral portions of the upper and lower electrode plates are joined to the upper and lower end surfaces of the insulating outer cylinder, respectively.

特開平7−94673号公報JP-A-7-94673

ところで、上下電極板と絶縁外筒とにより囲まれた封止空間には不活性ガスが充填され、不活性ガスのリークを防止するために、上下電極板と絶縁外筒とは溶接により接合されている。そのため、上下電極板の外筒に接触する部分の熱容量を小さくして、上下電極板と絶縁外筒とを溶接可能とする必要があり、その部分の電極板の厚さを薄くする必要があった。その結果、電極板を半導体装置の外部に延長して外部端子とした場合には、外部端子(延長した電極板)の厚さが薄くなるため、大きな電力を出力するためには電極板から外部へ導出するための外部端子を別に設ける必要があり、装置の大型化やコストアップを招くという問題があった。   By the way, the sealed space surrounded by the upper and lower electrode plates and the insulating outer cylinder is filled with an inert gas, and the upper and lower electrode plates and the insulating outer cylinder are joined by welding in order to prevent the leakage of the inert gas. ing. For this reason, it is necessary to reduce the heat capacity of the portion of the upper and lower electrode plates that contacts the outer cylinder so that the upper and lower electrode plates can be welded to the insulating outer cylinder, and it is necessary to reduce the thickness of the electrode plate in that portion. It was. As a result, when the electrode plate is extended to the outside of the semiconductor device as an external terminal, the thickness of the external terminal (extended electrode plate) is reduced. It is necessary to provide a separate external terminal for leading to the device, resulting in an increase in the size and cost of the device.

本発明は、表裏面に電極が各々形成された半導体チップを、有底筒状体を成す2つの分割ケーシングで構成されるケーシング内に収納した半導体装置であって、有底筒状体の周壁を絶縁部材で形成し、有底筒状体の底部を第1の電極板で形成し、第1の電極板の一部をケーシング外部に延在させて成る第1の外部端子を有する第1の分割ケーシングと、有底筒状体の周壁を絶縁部材で形成し、有底筒状体の底部を第2の電極板で形成し、第2の電極板の一部をケーシング外部に延在させて成る第2の外部端子を有する第2の分割ケーシングとを備え、半導体チップの表裏面を挟持するように第1および第2の電極板を前記半導体チップ方向に加圧して、表裏面に形成された各電極とそれに対向する電極板とを電気的に接続したことを特徴とする。   The present invention relates to a semiconductor device in which semiconductor chips each having electrodes formed on the front and back surfaces are housed in a casing composed of two divided casings forming a bottomed cylindrical body, and a peripheral wall of the bottomed cylindrical body Is formed of an insulating member, the bottom of the bottomed cylindrical body is formed of a first electrode plate, and a first external terminal formed by extending a part of the first electrode plate to the outside of the casing is provided. The divided casing and the peripheral wall of the bottomed cylindrical body are formed of an insulating member, the bottom of the bottomed cylindrical body is formed of the second electrode plate, and a part of the second electrode plate extends outside the casing And a second divided casing having a second external terminal, and pressurizing the first and second electrode plates in the direction of the semiconductor chip so as to sandwich the front and back surfaces of the semiconductor chip, Each formed electrode is electrically connected to the electrode plate facing it. .

本発明によれば、半導体チップが収容されるケーシングを有底筒状体を成す第1および第2の分割ケーシングで構成し、各有底筒状体の底面を各々電極板とし、それらの電極板の一部をケーシング外部に延在させて外部端子としたので、電極板の厚さを薄くすることなく外部へ導出することができ、従来のように別体の外部端子をさらに設ける必要がなく、部品点数の削減、装置の小型化および組み立て工数の低減を図ることができる。   According to the present invention, the casing in which the semiconductor chip is accommodated is constituted by the first and second divided casings that form a bottomed cylindrical body, and the bottom surface of each bottomed cylindrical body is an electrode plate, and the electrodes Since part of the plate is extended to the outside of the casing to be an external terminal, it can be led out without reducing the thickness of the electrode plate, and it is necessary to provide a separate external terminal as in the past Therefore, the number of parts can be reduced, the apparatus can be downsized, and the number of assembly steps can be reduced.

以下、図を参照して本発明を実施するための最良の形態について説明する。図1、2は本発明による半導体装置の一実施の形態を示す図である。図1は半導体装置の概略構成を示す平面図であり、図2は図1のA−A断面図である。図1、2に示す半導体装置は、三相インバータの一相分のモジュール1を示したものであり、モジュール1のケーシング内には半導体チップ2,3が設けられている。インバータに用いられるスイッチング素子としてはIGBTやMOSFETなどがあるが、以下ではIGBTを用いたものを例として説明する。半導体チップ2はIGBTであり、半導体チップ3はダイオードである。41はモジュール1の上面に設けられた電極板(バスバー)であり、図1では電極板41の一部を破断面としている。   Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings. 1 and 2 are diagrams showing an embodiment of a semiconductor device according to the present invention. FIG. 1 is a plan view showing a schematic configuration of a semiconductor device, and FIG. 2 is a cross-sectional view taken along line AA of FIG. The semiconductor device shown in FIGS. 1 and 2 shows a module 1 for one phase of a three-phase inverter, and semiconductor chips 2 and 3 are provided in a casing of the module 1. Examples of the switching element used in the inverter include an IGBT and a MOSFET. Hereinafter, an example using an IGBT will be described. The semiconductor chip 2 is an IGBT and the semiconductor chip 3 is a diode. Reference numeral 41 denotes an electrode plate (bus bar) provided on the upper surface of the module 1. In FIG. 1, a part of the electrode plate 41 has a broken surface.

半導体チップ2,3は、チップの表裏両面に電極が設けられている。IGBTである半導体チップ2の場合には、裏面側にコレクタ電極が設けられ、表面側にエミッタ電極およびゲート電極が設けられている。モジュール1の下面には電極板51が配設されており、半導体チップ2,3は裏面側の電極を電極板51にハンダ付けすることにより、電極板51上に実装されている。符号6で示した部材はハンダである。半導体チップ2のゲート電極は、ボンディングワイヤ7によって制御端子53に接続されている。電極板41,51は導電性および熱伝導性の高い金属材料、例えば銅やアルミニウムやそれらを主成分とする合金が用いられる。   The semiconductor chips 2 and 3 are provided with electrodes on both front and back surfaces of the chip. In the case of the semiconductor chip 2 which is an IGBT, a collector electrode is provided on the back surface side, and an emitter electrode and a gate electrode are provided on the front surface side. An electrode plate 51 is disposed on the lower surface of the module 1, and the semiconductor chips 2 and 3 are mounted on the electrode plate 51 by soldering the electrodes on the back surface side to the electrode plate 51. The member indicated by reference numeral 6 is solder. The gate electrode of the semiconductor chip 2 is connected to the control terminal 53 by a bonding wire 7. The electrode plates 41 and 51 are made of a metal material having high electrical conductivity and thermal conductivity, such as copper or aluminum, or an alloy containing them as a main component.

半導体チップ2,3の上面には、半導体チップ2,3の電極を保護するための接触電極8がそれぞれ載置されている。接触電極8は半導体チップ2,3の表面側電極と電極板41とを電気的・熱的に接続する部材であるが、電極板41と半導体チップ2,3との線膨張差による熱応力を低減する機能も有している。また、半導体チップ2,3の急激な温度上昇を和らげるサーマルマスとしても機能する。   Contact electrodes 8 for protecting the electrodes of the semiconductor chips 2 and 3 are placed on the upper surfaces of the semiconductor chips 2 and 3, respectively. The contact electrode 8 is a member that electrically and thermally connects the surface side electrodes of the semiconductor chips 2 and 3 and the electrode plate 41, but the thermal stress due to the linear expansion difference between the electrode plate 41 and the semiconductor chips 2 and 3 It also has a function to reduce. Also, it functions as a thermal mass that relieves the rapid temperature rise of the semiconductor chips 2 and 3.

例えば、電極板41を銅材で形成した場合、接触電極8も銅ブロックで形成する。そして、銅ブロックのチップ側表面には、線膨張係数が半導体チップ2,3の材料であるSi(シリコン)に近い、Mo(モリブデン)やW(タングステン)等を材料とする金属の層を設けておく。半導体チップ2,3を銅材から成る電極板41に対して直に接触させると、温度変化による膨張や収縮で半導体チップ2,3のチップ表面が擦られるおそれがある。しかし、接触電極8の半導体チップ側と半導体チップ2,3との線膨張係数の差が小さいので、そのような問題の発生を防止することができる。   For example, when the electrode plate 41 is formed of a copper material, the contact electrode 8 is also formed of a copper block. On the chip-side surface of the copper block, a metal layer having a linear expansion coefficient close to Si (silicon), which is the material of the semiconductor chips 2 and 3, and made of Mo (molybdenum) or W (tungsten) is provided. Keep it. If the semiconductor chips 2 and 3 are brought into direct contact with the electrode plate 41 made of a copper material, the chip surfaces of the semiconductor chips 2 and 3 may be rubbed due to expansion or contraction due to temperature change. However, since the difference in the coefficient of linear expansion between the semiconductor chip side of the contact electrode 8 and the semiconductor chips 2 and 3 is small, the occurrence of such a problem can be prevented.

半導体チップ2,3と電極板41との間に接触電極8を挟持するように、電極板41,51を上下から加圧することにより、半導体チップ2,3の表面電極と電極板41とが電気的に接続される。加圧の際にハンダ6が塑性変形することにより、半導体チップ2,3に偏荷重が加わるのを防止することができる。また、半導体チップ2,3の厚さの若干の差違があっても、ハンダ6の塑性変形により寸法差を吸収することができる。なお、加圧機構については図示を省略した。   By pressing the electrode plates 41 and 51 from above and below so that the contact electrode 8 is sandwiched between the semiconductor chips 2 and 3 and the electrode plate 41, the surface electrodes of the semiconductor chips 2 and 3 and the electrode plate 41 are electrically connected. Connected. When the solder 6 is plastically deformed at the time of pressurization, it is possible to prevent an uneven load from being applied to the semiconductor chips 2 and 3. Even if there is a slight difference in the thickness of the semiconductor chips 2 and 3, the dimensional difference can be absorbed by the plastic deformation of the solder 6. Note that the illustration of the pressurizing mechanism is omitted.

本実施の形態では半導体チップ2,3の表面側のみを圧接構造としたが、表面側だけでなく裏面側も圧接構造としても良い。その場合には、半導体チップ2,3の表裏両面に接触電極8を設けるようにする。また、表裏両面の電極をハンダ付けにより電極板41,51に接続するようにしても良い。また、ハンダ6を用いて半導体チップ2,3を下側の電極板51に固着しているが、ハンダ6に代えて銀ペーストや導電性接着剤等を導電性固着手段として用いても良い。   In this embodiment, only the front surface side of the semiconductor chips 2 and 3 has a pressure contact structure, but not only the front surface side but also the back surface side may have a pressure contact structure. In that case, the contact electrodes 8 are provided on both the front and back surfaces of the semiconductor chips 2 and 3. Moreover, you may make it connect the electrode of both front and back to the electrode plates 41 and 51 by soldering. Further, although the semiconductor chips 2 and 3 are fixed to the lower electrode plate 51 using the solder 6, silver paste, conductive adhesive, or the like may be used as the conductive fixing means instead of the solder 6.

本実施の形態では、半導体チップ2,3が収納されるケーシングは、図3に示すような電極板41および枠部材42を一体とした上側ケーシング4と、図4に示すような電極板51および枠部材52を一体とした下側ケーシング5とで構成される。   In the present embodiment, the casing in which the semiconductor chips 2 and 3 are housed is the upper casing 4 in which the electrode plate 41 and the frame member 42 as shown in FIG. 3 are integrated, the electrode plate 51 as shown in FIG. It is comprised by the lower casing 5 with which the frame member 52 was integrated.

図3において、(a)は上側ケーシング4の平面図,(b)は断面図、(c)は下面図である。電極板41はケーシングの一部を構成する矩形部41aと、電極板41を外部と接続するための端子部41bとから成る。枠部材42は、電極板41の矩形部41aの周縁部に、矩形筒状に形成されている。枠部材42には、上下に貫通する孔42aおよびケーシング内外に貫通する孔42bが形成されている。電極板41は、矩形部41aの周縁部が枠部材42の段部42cに載置されるように設けられ、上側ケーシング4の上面側に露出している。   3A is a plan view of the upper casing 4, FIG. 3B is a sectional view, and FIG. 3C is a bottom view. The electrode plate 41 includes a rectangular portion 41a constituting a part of the casing and a terminal portion 41b for connecting the electrode plate 41 to the outside. The frame member 42 is formed in a rectangular cylindrical shape at the peripheral edge of the rectangular portion 41 a of the electrode plate 41. The frame member 42 is formed with a hole 42a penetrating vertically and a hole 42b penetrating inside and outside the casing. The electrode plate 41 is provided such that the peripheral edge of the rectangular portion 41 a is placed on the stepped portion 42 c of the frame member 42, and is exposed on the upper surface side of the upper casing 4.

本実施の形態では、枠部材42は絶縁性の樹脂から成り、上側ケーシング4は、枠部42と電極板41とのインサート成形により一体成形される。また、枠部材42を成形した後に、段部42cに電極板41の矩形部41aを接着することにより、一体の上側ケーシング4を形成するようにしても良い。   In the present embodiment, the frame member 42 is made of an insulating resin, and the upper casing 4 is integrally formed by insert molding of the frame portion 42 and the electrode plate 41. In addition, after the frame member 42 is molded, the integral upper casing 4 may be formed by bonding the rectangular portion 41a of the electrode plate 41 to the stepped portion 42c.

一方、図4は下側ケーシング5を示す図であり、(a)は下側ケーシング5の平面図,(b)は断面図、(c)は下面図である。電極板51も電極板41と同様に、ケーシングの一部を構成する矩形部51aと、電極板51を外部と接続するための端子部51bとを有している。電極板51の矩形部51aの周縁部に設けられた枠部52の上面側には、L字形状の制御端子53が設けられている。制御端子53のボンディング部53aは枠部材52に接して設けられ、図2に示したようにボンディング部53aにボンディングワイヤ7が接続される。電極板51は、矩形部51aの周縁部が枠部材52の段部52aに当接するように設けられ、下側ケーシング5の下面側に露出している。   On the other hand, FIG. 4 is a figure which shows the lower casing 5, (a) is a top view of the lower casing 5, (b) is sectional drawing, (c) is a bottom view. Similarly to the electrode plate 41, the electrode plate 51 also has a rectangular portion 51a constituting a part of the casing and a terminal portion 51b for connecting the electrode plate 51 to the outside. An L-shaped control terminal 53 is provided on the upper surface side of the frame portion 52 provided at the peripheral edge of the rectangular portion 51 a of the electrode plate 51. The bonding portion 53a of the control terminal 53 is provided in contact with the frame member 52, and the bonding wire 7 is connected to the bonding portion 53a as shown in FIG. The electrode plate 51 is provided such that the peripheral edge of the rectangular portion 51 a is in contact with the stepped portion 52 a of the frame member 52, and is exposed on the lower surface side of the lower casing 5.

枠部材52も枠部材42と同様の絶縁性樹脂が用いられる。下側ケーシング5も上側ケーシング4と同様にインサート成形により形成され、枠部52,電極板51および制御電極53が一体成形される。また、下側ケーシング5の場合も、枠部材52を成形した後に、段部52cに電極板51の矩形部51aを接着するとともに、枠部材52の上面に制御電極53を接着固定して一体とするようにしても良い。   The frame member 52 is also made of the same insulating resin as the frame member 42. The lower casing 5 is also formed by insert molding similarly to the upper casing 4, and the frame portion 52, the electrode plate 51 and the control electrode 53 are integrally molded. Also in the case of the lower casing 5, after the frame member 52 is molded, the rectangular portion 51 a of the electrode plate 51 is bonded to the stepped portion 52 c, and the control electrode 53 is bonded and fixed to the upper surface of the frame member 52. You may make it do.

モジュール1は次のような手順で組み立てられる。まず、下側ケーシング5の電極板51上に半導体チップ2,3をハンダ付けし、半導体チップ2の上面に設けられたゲート電極と枠部材52に設けられた制御端子53とをボンディングワイヤ7により接続する。その後、半導体チップ2,3の上面に接触電極8を載置し、上側ケーシング4を下側ケーシング5に装着して接合する。このとき、制御電極53が枠部材42の孔42aに挿入されるように、上側ケーシング4を装着する。ケーシング4,5同士の接合は、枠部材42,52同士を接着したりネジ止めしたりすることにより行われる。   The module 1 is assembled in the following procedure. First, the semiconductor chips 2 and 3 are soldered on the electrode plate 51 of the lower casing 5, and the gate electrode provided on the upper surface of the semiconductor chip 2 and the control terminal 53 provided on the frame member 52 are connected by the bonding wire 7. Connecting. Thereafter, the contact electrode 8 is placed on the upper surfaces of the semiconductor chips 2 and 3, and the upper casing 4 is attached to the lower casing 5 and joined. At this time, the upper casing 4 is mounted so that the control electrode 53 is inserted into the hole 42 a of the frame member 42. The casings 4 and 5 are joined to each other by bonding or screwing the frame members 42 and 52 together.

次いで、枠部材42に形成された貫通孔42bから、密着性および弾力性の高い絶縁性樹脂、例えばシリコンゲルをケーシング内に充填する。充填後、貫通孔42bは封止される。絶縁性樹脂としてはシリコン系に限らず、エポキシ系、ウレタン系等を用いても良い。ケーシング内に空気が有ると電極などが酸化されるが、このように樹脂を充填することにより電極面が樹脂に覆われて酸化を防止できる。また、半導体チップ2の上下両面は異種電極で電位差が大きく、沿面放電が生じるおそれがある。しかし、樹脂を充填して電極間を樹脂で覆うことにより、沿面放電を防止することができる。なお、貫通孔42bを形成せずに、不活性ガス雰囲気中で上下ケーシングを接合することにより、ケーシング内を不活性ガスで満たすようにしても良い。   Next, an insulating resin having high adhesion and elasticity, such as silicon gel, is filled into the casing from the through hole 42 b formed in the frame member 42. After filling, the through hole 42b is sealed. The insulating resin is not limited to silicon, but may be epoxy or urethane. When air is present in the casing, the electrode and the like are oxidized. By filling the resin in this way, the electrode surface is covered with the resin, and oxidation can be prevented. Further, the upper and lower surfaces of the semiconductor chip 2 are different electrodes and have a large potential difference, which may cause creeping discharge. However, creeping discharge can be prevented by filling the resin and covering the space between the electrodes. In addition, you may make it fill the inside of a casing with an inert gas by joining an upper and lower casing in inert gas atmosphere, without forming the through-hole 42b.

[変形例1]
図5〜7は、上述した実施の形態の変形例1を示す図である。図5,6は、それぞれ上側ケーシング4と下側ケーシング5を示す図である。上側ケーシング4には、図5の(b),(c)に示すように、枠部材42の下側ケーシング5との合わせ面に凸部42d,42eが形成されている。さらに、電極板41の下面には、半導体チップ2,3上に載置される接触電極8を位置決めするための位置決め部42fが形成されている。位置決め部42fには、接触電極8が嵌り込む矩形孔H1,H2が半導体チップ2,3と対向する位置に形成されている。
[Modification 1]
5-7 is a figure which shows the modification 1 of embodiment mentioned above. 5 and 6 are views showing the upper casing 4 and the lower casing 5, respectively. As shown in FIGS. 5B and 5C, convex portions 42 d and 42 e are formed on the mating surface of the upper casing 4 with the lower casing 5 of the frame member 42. Furthermore, a positioning portion 42 f for positioning the contact electrode 8 placed on the semiconductor chips 2 and 3 is formed on the lower surface of the electrode plate 41. In the positioning portion 42f, rectangular holes H1 and H2 into which the contact electrodes 8 are fitted are formed at positions facing the semiconductor chips 2 and 3.

一方、下側ケーシング5には、図6の(a),(b)に示すように、枠部材52の上側ケーシング4との合わせ面の上記凸部42d,42eと対向する位置に、凸部42d,42eと系合する凹部52b,52cが形成されている。図7の二点鎖線で示すように下側ケーシング5に上側ケーシング4を装着すると、枠部材42に形成されている凸部42d,42eが、下側ケーシング5の枠部材52に形成されている凹部52b,52cにそれぞれ係合する。   On the other hand, as shown in FIGS. 6A and 6B, the lower casing 5 has convex portions at positions facing the convex portions 42 d and 42 e of the mating surface of the frame member 52 with the upper casing 4. Concave portions 52b and 52c that are mated with 42d and 42e are formed. When the upper casing 4 is attached to the lower casing 5 as shown by a two-dot chain line in FIG. 7, convex portions 42 d and 42 e formed on the frame member 42 are formed on the frame member 52 of the lower casing 5. It engages with the recesses 52b and 52c, respectively.

すなわち、凸部42d,42eが凹部52b,52cに系合することにより、ケーシング4,5間の位置決めが成される。さらに、各接触電極8の上側が上側ケーシング4の位置決め部42fにガイドされるように矩形孔H1,H2に嵌り込むことにより、半導体チップ2,3に対する各接触電極8の位置決めが成される。なお、下側の電極板1上にも、ハンダ6や半導体チップ2,3を位置決めするための位置決め部を形成しても良い。   In other words, the positioning between the casings 4 and 5 is achieved by the convex portions 42d and 42e engaging with the concave portions 52b and 52c. Further, the contact electrodes 8 are positioned with respect to the semiconductor chips 2 and 3 by being fitted into the rectangular holes H1 and H2 so that the upper side of each contact electrode 8 is guided by the positioning portion 42f of the upper casing 4. A positioning portion for positioning the solder 6 and the semiconductor chips 2 and 3 may also be formed on the lower electrode plate 1.

[変形例2]
図8は変形例2を示す図であり、(a)はモジュール1の平面図、(b)は断面図、(c)は下面図である。ケーシング4,5において、上述した実施の形態と同様の部分には同一符号を付し、以下では異なる部分を中心に説明する。図2に示したように、電極板41と半導体チップ2,3との圧接を行わせるために、モジュール1は加圧機構によって上下から加圧される。しかし、内部の接触電極8がケーシング内において固定されているためには、加圧前のモジュール1単体の場合においても、接触電極8が電極板41によって半導体チップ2,3に押圧されている必要がある。
[Modification 2]
FIGS. 8A and 8B are diagrams showing Modification Example 2. FIG. 8A is a plan view of the module 1, FIG. 8B is a cross-sectional view, and FIG. 8C is a bottom view. In the casings 4 and 5, the same parts as those in the above-described embodiment are given the same reference numerals, and different parts will be mainly described below. As shown in FIG. 2, the module 1 is pressurized from above and below by a pressure mechanism in order to cause the electrode plate 41 and the semiconductor chips 2 and 3 to be pressed. However, since the internal contact electrode 8 is fixed in the casing, the contact electrode 8 must be pressed against the semiconductor chips 2 and 3 by the electrode plate 41 even in the case of the module 1 alone before pressurization. There is.

例えば、ケーシング4,5を合わせたときに枠部材42,52間に微少な隙間が形成されるように設定しておき、枠部材同士の接合時に隙間がゼロとなるように電極板41,51をわずかに変形させるような構成とする。このような場合、電極板41,51にはケーシングの外側に押し出されるような反力が作用し、枠部材42,52から電極板41,51が外れるおそれがある。   For example, it is set so that a minute gap is formed between the frame members 42 and 52 when the casings 4 and 5 are combined, and the electrode plates 41 and 51 are set so that the gap is zero when the frame members are joined. Is configured to be slightly deformed. In such a case, a reaction force that is pushed out of the casing acts on the electrode plates 41 and 51, and the electrode plates 41 and 51 may be detached from the frame members 42 and 52.

そこで、変形例2では、電極板41,51の枠部材42,52からの離脱を防止する離脱防止部42g、52gを枠部材42,52に形成した。図8に示す例では、電極板41,51の矩形部41a,51aの全周に枠部材42,52を乗り上げる(言い替えれば、電極板41,51の表裏面を枠部材42,52で覆う)ように形成して、離脱防止部42g、52gを構成したが、一部分に乗り上げる(一部分を覆う)ようにしても良い。このような離脱防止部42g、52gを形成したことにより、反力によって電極板41,51が外側に外れてしまうのを防止することができる。   Therefore, in the second modification, the detachment preventing portions 42g and 52g that prevent the electrode plates 41 and 51 from detaching from the frame members 42 and 52 are formed in the frame members 42 and 52, respectively. In the example shown in FIG. 8, the frame members 42 and 52 are run on the entire circumference of the rectangular portions 41 a and 51 a of the electrode plates 41 and 51 (in other words, the front and back surfaces of the electrode plates 41 and 51 are covered with the frame members 42 and 52). The separation preventing portions 42g and 52g are formed in such a manner as described above. By forming such separation preventing portions 42g and 52g, it is possible to prevent the electrode plates 41 and 51 from being detached outside due to a reaction force.

[変形例3]
図9は変形例3を説明する図である。モジュール1に設けられている電極板41,51は異種電極であるため、沿面放電を防止するために電極板41,51間の絶縁耐圧を半導体チップ2,3の絶縁耐圧以上に設定しておく必要がある。モジュール1ではケーシング内に樹脂が充填されているので、モジュール内での沿面放電は防止されるが、モジュール1の外側は大気に触れているため、沿面絶縁を確保する必要がある。
[Modification 3]
FIG. 9 is a diagram for explaining a third modification. Since the electrode plates 41 and 51 provided in the module 1 are dissimilar electrodes, the withstand voltage between the electrode plates 41 and 51 is set to be higher than the withstand voltage of the semiconductor chips 2 and 3 in order to prevent creeping discharge. There is a need. In the module 1, since the resin is filled in the casing, creeping discharge in the module is prevented, but the outside of the module 1 is exposed to the atmosphere, so that it is necessary to ensure creeping insulation.

そこで、図9に示したモジュール1では、枠部材42,52の外周面42k、52kに凹凸を形成した。具体的には、枠部材42,52の側面を一周する溝を複数形成した。これにより、電極板41と電極板51との間の沿面距離が長くなって沿面絶縁の向上を図ることができ、沿面放電を防止することができる。   Therefore, in the module 1 shown in FIG. 9, irregularities are formed on the outer peripheral surfaces 42 k and 52 k of the frame members 42 and 52. Specifically, a plurality of grooves that circulate around the side surfaces of the frame members 42 and 52 were formed. Thereby, the creeping distance between the electrode plate 41 and the electrode plate 51 is increased, and the creeping insulation can be improved, and the creeping discharge can be prevented.

なお、上述した実施の形態では、枠部材52に制御端子53をモールドして、その制御端子53と半導体チップ2のゲート電極とをボンディングワイヤ7により接続したが、図10に示すように針状のピン100を半導体チップ2のゲート電極に圧接するような構成としても良い。電極板41を貫通するように絶縁樹脂のインサート101を設け、そのインサート101に形成された貫通孔を介してピン100をゲート電極に接触させる。図示は省略したが、ピン100はバネ等の付勢手段によってゲート電極に押圧されている。   In the embodiment described above, the control terminal 53 is molded on the frame member 52, and the control terminal 53 and the gate electrode of the semiconductor chip 2 are connected by the bonding wire 7. However, as shown in FIG. The pin 100 may be in pressure contact with the gate electrode of the semiconductor chip 2. An insulating resin insert 101 is provided so as to penetrate the electrode plate 41, and the pin 100 is brought into contact with the gate electrode through a through hole formed in the insert 101. Although not shown, the pin 100 is pressed against the gate electrode by a biasing means such as a spring.

以上説明した本実施の形態の特徴とまとめると以下のようになる。
(a)電極板41と枠部材42とが一体化された上側ケーシング4と、電極板51と枠部材52とが一体化された下側ケーシング5とを別々に形成し、それらを接合して密封されたケーシングを構成するようにしているので、従来のような封止のために電極板と絶縁外筒とを溶接する必要がない。そして、電極板41,51の一部を端子部41b,51bとして枠部材42,52の側方に延在させるようにしたので、端子部41b,51bの厚さを薄くすることなく外部へ導出することが可能となり、外部端子を別に設ける必要がなく、モジュール1の小型化、部品点数の削減を図ることができる。特に、電極板41と枠部材42、電極板51と枠部材52とを一体成形してケーシング4,5を形成したことにより、組み立て工程の簡略化や、電極板41,51と枠部材42,52との接合の確実性向上を図ることができる。
The characteristics of the present embodiment described above are summarized as follows.
(A) The upper casing 4 in which the electrode plate 41 and the frame member 42 are integrated, and the lower casing 5 in which the electrode plate 51 and the frame member 52 are integrated are separately formed, and they are joined together. Since the sealed casing is configured, it is not necessary to weld the electrode plate and the insulating outer cylinder for the conventional sealing. Since part of the electrode plates 41 and 51 are extended to the sides of the frame members 42 and 52 as terminal portions 41b and 51b, they are led out to the outside without reducing the thickness of the terminal portions 41b and 51b. Therefore, it is not necessary to provide a separate external terminal, and the module 1 can be downsized and the number of parts can be reduced. In particular, the electrode plate 41 and the frame member 42, and the electrode plate 51 and the frame member 52 are integrally formed to form the casings 4 and 5, so that the assembly process can be simplified, and the electrode plates 41 and 51 and the frame member 42, The reliability of joining with 52 can be improved.

(b)電極板41,51に乗り上げる(電極板41,51の表裏面を覆う)ように形成された離脱防止部42g、52gを枠部材42,52に設けたことにより、電極板41,52を加圧した際にそれらが枠部材42,52から外れてしまうのを防止することができる。また、枠部材42,52の外周面42k、52kを凹凸形状としたことにより、電極板41,51間の沿面距離がより長くなり、沿面放電の発生を抑制することができる。さらに、各枠部材42,52の互いに接合される面に、互いに係合する凸部42d,42eおよび凹部52b、52cを形成したので、ケーシング4,5を重ね合わせる際の位置決めが容易となる。 (B) By providing the frame members 42 and 52 with the separation preventing portions 42g and 52g formed so as to ride on the electrode plates 41 and 51 (covering the front and back surfaces of the electrode plates 41 and 51), the electrode plates 41 and 52 are provided. It is possible to prevent them from being detached from the frame members 42 and 52 when they are pressed. In addition, by forming the outer peripheral surfaces 42k and 52k of the frame members 42 and 52 into a concavo-convex shape, the creeping distance between the electrode plates 41 and 51 becomes longer, and the occurrence of creeping discharge can be suppressed. Further, since the convex portions 42d and 42e and the concave portions 52b and 52c that are engaged with each other are formed on the surfaces of the frame members 42 and 52 that are joined to each other, the positioning when the casings 4 and 5 are overlapped is facilitated.

(c)圧接構造であってもハンダ6や導電性接着剤や銀ペースト等の導電性固着手段により半導体チップ2を下側の電極板51に固着しているので、枠部材52に設けられた制御端子53に対して半導体チップ2が固定され、ワイヤボンディング作業が簡単にできる。さらに、ハンダ6を導電性固着手段に用いた場合、圧接時にハンダ6が塑性変形することで、半導体チップ2,3に掛かる偏荷重を緩和することができる。 (C) Even in the pressure contact structure, the semiconductor chip 2 is fixed to the lower electrode plate 51 by means of conductive fixing means such as solder 6, conductive adhesive, or silver paste, so that it is provided on the frame member 52. The semiconductor chip 2 is fixed to the control terminal 53, and wire bonding work can be simplified. Further, when the solder 6 is used as the conductive fixing means, the unbalanced load applied to the semiconductor chips 2 and 3 can be alleviated by the plastic deformation of the solder 6 during the pressure contact.

(d)熱応力緩衝材としての接触電極8を半導体チップ2,3とで電極板41,51との間に設けたので、互いの接触部分における接触電極8と半導体チップ2,3との線膨張係数差が小さく、温度変化による膨張や収縮で半導体チップ2,3のチップ表面が擦られるのを防止することができる。また、上側ケーシング4に置決め部42fを形成したので、上下のケーシング4,5を合わせた際に各接触電極8が置決め部42fによりガイドされ、半導体チップ2,3上に正確に位置決めされる。
(e)上下のケーシング4,5により形成されるケーシング内に絶縁性樹脂を充填するようにしたので、半導体チップ2,3の電極面の酸化や、電極間の沿面放電を防止することができる。
(D) Since the contact electrode 8 as a thermal stress buffer material is provided between the semiconductor chips 2 and 3 and the electrode plates 41 and 51, the line between the contact electrode 8 and the semiconductor chips 2 and 3 in the mutual contact portion. The expansion coefficient difference is small, and it is possible to prevent the chip surfaces of the semiconductor chips 2 and 3 from being rubbed due to expansion and contraction due to temperature changes. Since the positioning portion 42f is formed in the upper casing 4, each contact electrode 8 is guided by the positioning portion 42f when the upper and lower casings 4 and 5 are put together, and is accurately positioned on the semiconductor chips 2 and 3. The
(E) Since the insulating resin is filled in the casing formed by the upper and lower casings 4 and 5, oxidation of the electrode surfaces of the semiconductor chips 2 and 3 and creeping discharge between the electrodes can be prevented. .

以上説明した実施の形態と特許請求の範囲の要素との対応において、枠部材42,52は周壁を、電極板41は第1の電極板を、電極板51は第2の電極板を、上側ケーシング4は第1の分割ケーシングを、下側ケーシング5は第2の分割ケーシングを、端子部41bは第1の外部端子を、端子部51bは第2の外部端子を、凸部42d,42eおよび凹部52b,52cは係合部を、ハンダ6は導電性固着手段を、接触電極8は保護部材をそれぞれ構成する。なお、以上の説明はあくまでも一例であり、発明を解釈する際、上記実施の形態の記載事項と特許請求の範囲の記載事項の対応関係に何ら限定も拘束もされない。   In the correspondence between the embodiment described above and the elements of the claims, the frame members 42 and 52 are peripheral walls, the electrode plate 41 is a first electrode plate, the electrode plate 51 is a second electrode plate, and the upper side. The casing 4 is a first divided casing, the lower casing 5 is a second divided casing, the terminal portion 41b is a first external terminal, the terminal portion 51b is a second external terminal, and convex portions 42d and 42e and The recesses 52b and 52c constitute engaging portions, the solder 6 constitutes a conductive fixing means, and the contact electrode 8 constitutes a protective member. The above description is merely an example, and when interpreting the invention, there is no limitation or restriction on the correspondence between the items described in the above embodiment and the items described in the claims.

本発明による半導体装置の一実施の形態を示す図であり、半導体装置の概略構成を示す平面図である。1 is a diagram illustrating an embodiment of a semiconductor device according to the present invention, and is a plan view illustrating a schematic configuration of the semiconductor device. 図1のA−A断面図である。It is AA sectional drawing of FIG. 上側ケーシング4を示す図であり、(a)は平面図,(b)は断面図,(c)は下面図である。It is a figure which shows the upper casing 4, (a) is a top view, (b) is sectional drawing, (c) is a bottom view. 下側ケーシング5を示す図であり、(a)は平面図,(b)は断面図,(c)は下面図である。It is a figure which shows the lower casing 5, (a) is a top view, (b) is sectional drawing, (c) is a bottom view. 変形例1における上側ケーシング4を示す図であり、(a)は平面図,(b)は断面図,(c)は下面図であるIt is a figure which shows the upper casing 4 in the modification 1, (a) is a top view, (b) is sectional drawing, (c) is a bottom view. 変形例1における下側ケーシング5を示す図であり、(a)は平面図,(b)は断面図,(c)は下面図であるIt is a figure which shows the lower casing 5 in the modification 1, (a) is a top view, (b) is sectional drawing, (c) is a bottom view. 位置決め部42fによる接触電極8の位置決めを説明する図である。It is a figure explaining positioning of the contact electrode 8 by the positioning part 42f. 変形例2におけるモジュール1を示す図であり、(a)は平面図、(b)は断面図、(c)は下面図である。It is a figure which shows the module 1 in the modification 2, (a) is a top view, (b) is sectional drawing, (c) is a bottom view. 変形例3を説明する図である。It is a figure explaining the modification 3. FIG. 半導体チップ2のゲート電極に圧接された針状のピン100を示す図である。FIG. 3 is a diagram showing a needle-like pin 100 that is in pressure contact with a gate electrode of a semiconductor chip 2.

符号の説明Explanation of symbols

1 モジュール
2,3 半導体チップ
4 上側ケーシング
5 下側ケーシング
6 ハンダ
8 接触電極
41,51 電極板
41a,51a 矩形部
41b,51b 端子部
42,52 枠部材
42d,42e 凸部
42f 位置決め部
42g、52g 離脱防止部
42k、52k 外周面
52b,52c 凹部
53 制御端子
H1,H2 矩形孔
1 Module 2, 3 Semiconductor chip 4 Upper casing 5 Lower casing 6 Solder 8 Contact electrode 41, 51 Electrode plate 41a, 51a Rectangular portion 41b, 51b Terminal portion 42, 52 Frame member 42d, 42e Protruding portion 42f Positioning portion 42g, 52g Detachment prevention part 42k, 52k Outer peripheral surface 52b, 52c Recess 53 Control terminal H1, H2 Rectangular hole

Claims (9)

表裏面に電極が各々形成された半導体チップを、有底筒状体を成す2つの分割ケーシングで構成されるケーシング内に収納した半導体装置であって、
前記有底筒状体の周壁を絶縁部材で形成し、前記有底筒状体の底部を第1の電極板で形成し、前記第1の電極板の一部をケーシング外部に延在させて成る第1の外部端子を有する第1の分割ケーシングと、
前記有底筒状体の周壁を絶縁部材で形成し、前記有底筒状体の底部を第2の電極板で形成し、前記第2の電極板の一部をケーシング外部に延在させて成る第2の外部端子を有する第2の分割ケーシングとを備え、
前記半導体チップの表裏面を挟持するように前記第1および第2の電極板を前記半導体チップ方向に加圧して、前記表裏面に形成された各電極とそれに対向する前記電極板とを電気的に接続したことを特徴とする半導体装置。
A semiconductor device in which semiconductor chips each having electrodes formed on the front and back surfaces are housed in a casing composed of two divided casings forming a bottomed cylindrical body,
A peripheral wall of the bottomed cylindrical body is formed of an insulating member, a bottom portion of the bottomed cylindrical body is formed of a first electrode plate, and a part of the first electrode plate is extended outside the casing. A first split casing having a first external terminal comprising:
A peripheral wall of the bottomed cylindrical body is formed of an insulating member, a bottom portion of the bottomed cylindrical body is formed of a second electrode plate, and a part of the second electrode plate extends outside the casing. A second split casing having a second external terminal comprising:
The first and second electrode plates are pressed in the direction of the semiconductor chip so as to sandwich the front and back surfaces of the semiconductor chip, and the electrodes formed on the front and back surfaces and the electrode plates facing the electrodes are electrically connected to each other. A semiconductor device characterized by being connected to a semiconductor device.
請求項1に記載の半導体装置において、
前記絶縁部材として絶縁性樹脂を用い、前記第1および第2の分割ケーシングの前記絶縁部材と前記電極板とを一体成形により形成したことを特徴とする半導体装置。
The semiconductor device according to claim 1,
An insulating resin is used as the insulating member, and the insulating member and the electrode plate of the first and second divided casings are formed by integral molding.
請求項1または2に記載の半導体装置において、
前記周壁に、前記電極板の表裏面を覆って前記加圧による前記電極板の前記周壁からの離脱を防止する離脱防止部を設けたことを特徴とする半導体装置。
The semiconductor device according to claim 1 or 2,
2. A semiconductor device according to claim 1, wherein a separation preventing portion is provided on the peripheral wall so as to cover the front and back surfaces of the electrode plate and prevent the electrode plate from separating from the peripheral wall due to the pressurization.
請求項1〜3のいずれかに記載の半導体装置において、
前記周壁の外周面を凹凸形状としたことを特徴とする半導体装置。
The semiconductor device according to claim 1,
A semiconductor device characterized in that an outer peripheral surface of the peripheral wall has an uneven shape.
請求項1〜4のいずれかに記載の半導体装置において、
前記ケーシングは前記第1および第2の分割ケーシングの前記周壁を互いに突き合わせて接合することにより形成され、前記各周壁の接合部に互いに係合する係合部をそれぞれ形成したことを特徴とする半導体装置。
In the semiconductor device according to claim 1,
The casing is formed by abutting and joining the peripheral walls of the first and second divided casings, and an engagement portion that engages with each other is formed at the joint portion of each peripheral wall. apparatus.
請求項1〜5のいずれかに記載の半導体装置において、
前記半導体チップの表裏面に形成された各電極の少なくとも一方を、それに対向する前記電極板に導電性固着手段により固着したことを特徴とする半導体装置。
In the semiconductor device according to claim 1,
A semiconductor device, wherein at least one of the electrodes formed on the front and back surfaces of the semiconductor chip is fixed to the electrode plate opposed thereto by a conductive fixing means.
請求項6に記載の半導体装置において、
前記導電性固着手段にハンダを用いたことを特徴とする半導体装置。
The semiconductor device according to claim 6.
A semiconductor device characterized in that solder is used for the conductive fixing means.
請求項1〜7のいずれかに記載の半導体装置において、
前記第1および第2の電極板の少なくとも一方と前記半導体チップとの間に配設され、前記半導体チップ接触部との接触面の線膨張係数が前記電極板よりも前記半導体チップに近い材質で形成されて、前記半導体チップの接触面を保護する保護部材と、
前記周壁から半導体装置内部方向へ延びて、前記保護部材を前記半導体チップのチップ面上に位置決めする位置決め部を、前記第1の分割ケーシングおよび第2の分割ケーシングの少なくとも一方に設けたことを特徴とする半導体装置。
In the semiconductor device according to claim 1,
A material that is disposed between at least one of the first and second electrode plates and the semiconductor chip, and has a coefficient of linear expansion of a contact surface with the semiconductor chip contact portion that is closer to the semiconductor chip than the electrode plate. A protective member formed and protecting the contact surface of the semiconductor chip;
A positioning portion extending from the peripheral wall toward the inside of the semiconductor device and positioning the protective member on the chip surface of the semiconductor chip is provided in at least one of the first divided casing and the second divided casing. A semiconductor device.
請求項1〜8のいずれかに記載の半導体装置において、
前記第1および第2の分割ケーシングにより形成される前記ケーシングの半導体チップ収容空間に、絶縁性樹脂を充填したことを特徴とする半導体装置。
The semiconductor device according to claim 1,
A semiconductor device characterized in that an insulating resin is filled in a semiconductor chip housing space of the casing formed by the first and second divided casings.
JP2004376618A 2004-12-27 2004-12-27 Semiconductor device Expired - Fee Related JP4424199B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004376618A JP4424199B2 (en) 2004-12-27 2004-12-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004376618A JP4424199B2 (en) 2004-12-27 2004-12-27 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2006186035A true JP2006186035A (en) 2006-07-13
JP4424199B2 JP4424199B2 (en) 2010-03-03

Family

ID=36738938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004376618A Expired - Fee Related JP4424199B2 (en) 2004-12-27 2004-12-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JP4424199B2 (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008235651A (en) * 2007-03-22 2008-10-02 Fuji Electric Device Technology Co Ltd Semiconductor device and manufacturing method therefor
JP2008252055A (en) * 2007-03-08 2008-10-16 Fuji Electric Device Technology Co Ltd Semiconductor and method for manufacturing the same
JP2012074588A (en) * 2010-09-29 2012-04-12 Rohm Co Ltd Semiconductor power module and method for manufacturing the same
JP2013012642A (en) * 2011-06-30 2013-01-17 Meidensha Corp Power semiconductor module
JP2013239486A (en) * 2012-05-11 2013-11-28 Hitachi Ltd Semiconductor device and manufacturing method of the same
JP2014082274A (en) * 2012-10-15 2014-05-08 Toyota Industries Corp Semiconductor device
JP2014135527A (en) * 2014-04-30 2014-07-24 Rohm Co Ltd Semiconductor power module and method for manufacturing the same
DE102008012703B4 (en) * 2007-03-08 2015-05-28 Fuji Electric Co., Ltd. Semiconductor device and method of making the same
JP2015233168A (en) * 2015-10-01 2015-12-24 ローム株式会社 Semiconductor power module
JP2017092388A (en) * 2015-11-16 2017-05-25 富士電機株式会社 Semiconductor device and semiconductor device manufacturing method
JP2021082714A (en) * 2019-11-19 2021-05-27 富士電機株式会社 Semiconductor device
WO2023276100A1 (en) * 2021-07-01 2023-01-05 三菱電機株式会社 Power module
WO2024062633A1 (en) * 2022-09-22 2024-03-28 株式会社レゾナック Laminate and laminate production method

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008252055A (en) * 2007-03-08 2008-10-16 Fuji Electric Device Technology Co Ltd Semiconductor and method for manufacturing the same
DE102008012703B4 (en) * 2007-03-08 2015-05-28 Fuji Electric Co., Ltd. Semiconductor device and method of making the same
JP2008235651A (en) * 2007-03-22 2008-10-02 Fuji Electric Device Technology Co Ltd Semiconductor device and manufacturing method therefor
US8981542B2 (en) 2010-09-29 2015-03-17 Rohm Co., Ltd. Semiconductor power module and method of manufacturing the same
JP2012074588A (en) * 2010-09-29 2012-04-12 Rohm Co Ltd Semiconductor power module and method for manufacturing the same
JP2013012642A (en) * 2011-06-30 2013-01-17 Meidensha Corp Power semiconductor module
JP2013239486A (en) * 2012-05-11 2013-11-28 Hitachi Ltd Semiconductor device and manufacturing method of the same
JP2014082274A (en) * 2012-10-15 2014-05-08 Toyota Industries Corp Semiconductor device
JP2014135527A (en) * 2014-04-30 2014-07-24 Rohm Co Ltd Semiconductor power module and method for manufacturing the same
JP2015233168A (en) * 2015-10-01 2015-12-24 ローム株式会社 Semiconductor power module
JP2017092388A (en) * 2015-11-16 2017-05-25 富士電機株式会社 Semiconductor device and semiconductor device manufacturing method
JP2021082714A (en) * 2019-11-19 2021-05-27 富士電機株式会社 Semiconductor device
JP7427927B2 (en) 2019-11-19 2024-02-06 富士電機株式会社 semiconductor equipment
WO2023276100A1 (en) * 2021-07-01 2023-01-05 三菱電機株式会社 Power module
WO2024062633A1 (en) * 2022-09-22 2024-03-28 株式会社レゾナック Laminate and laminate production method
WO2024062649A1 (en) * 2022-09-22 2024-03-28 株式会社レゾナック Laminate, method for manufacturing laminate, and conductive laminate

Also Published As

Publication number Publication date
JP4424199B2 (en) 2010-03-03

Similar Documents

Publication Publication Date Title
JP4581885B2 (en) Semiconductor device
JP5339800B2 (en) Manufacturing method of semiconductor device
TWI404177B (en) Electric power semiconductor circuit device and method for making same
JP4499577B2 (en) Semiconductor device
JP5206822B2 (en) Semiconductor device
JP4424199B2 (en) Semiconductor device
US20020109152A1 (en) Power semiconductor module
WO2015174158A1 (en) Power semiconductor module and composite module
JP5659938B2 (en) Semiconductor unit and semiconductor device using the same
WO2005119896A1 (en) Inverter device
JP4403665B2 (en) Semiconductor device
US11961780B2 (en) Semiconductor module, power conversion device, and manufacturing method of semiconductor module
JP2006186170A (en) Semiconductor device
JP4100332B2 (en) Electronic device and manufacturing method thereof
JP2009164647A (en) Semiconductor device
JP2018060902A (en) Mold resin sealed power semiconductor device
WO2019003718A1 (en) Power semiconductor device and power conversion device using same
JPWO2019044177A1 (en) Power semiconductor devices and their manufacturing methods
JP4258391B2 (en) Semiconductor device
JP7103437B2 (en) Semiconductor devices and manufacturing methods for semiconductor devices
JP4864990B2 (en) Semiconductor device
JP7118204B1 (en) semiconductor equipment
WO2023047451A1 (en) Power semiconductor device and method for manufacturing power semiconductor device
JP2004128265A (en) Semiconductor module and plate-like lead
US20230245948A1 (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20071128

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20080624

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20080605

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20081014

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090821

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090825

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091023

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20091117

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20091130

R150 Certificate of patent (=grant) or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121218

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees