JP2006179733A - Multilayer wiring board and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form simply a dig-out which an electronic part, such as a semiconductor chip, etc. is inserted, and an improvement in productivity is aimed at, and to enable it to carry the electronic part in the dig-out part good. <P>SOLUTION: Since the dig-out 27 which the semiconductor chip 26 inserts in the second substrate 21 is formed and this second substrate 21 is located on the first substrate 20, the hollowed-out 27 can be formed beforehand in the second substrate 21. For this sake, since the hollowed-out 27 can be formed in the second substrate 21 simply and corrected without using a special cutting unit, the productivity can be improved. Moreover, since a building-up part 28 is formed in the shape of a frame along with the peripheral side of a chip loading region E on the first substrate 20, an insulating adhesive layer 29 is formed in the first substrate 20 located in the peripheral side of this building-up part 28 and the first and second substrates 20 and 21 are joined, the entering of the insulating adhesive layer 29 into the hollowed-out 27 can be stopped by the building-up part 28 at the time of the bonding. Consequently, the semiconductor chip 26 can be carried in the hollowed-out 27 good. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a multilayer wiring board used for an electronic device such as an electronic wristwatch and a method for manufacturing the same.

  In an electronic device such as an electronic wristwatch, a multilayer wiring board on which electronic components are mounted at a high density is used in order to reduce the size and thickness. In such a multilayer wiring board, a plurality of substrates having wiring patterns formed on the front and back surfaces are sequentially laminated by an insulating adhesive layer, and an electronic circuit such as a semiconductor chip is formed on the uppermost surface and the lowermost surface of the laminated substrates. It has a configuration with parts mounted. In this multilayer wiring board, since electronic components such as semiconductor chips are mounted on the uppermost surface and the lowermost surface, there is a problem that the thickness of the entire substrate becomes thick.

Therefore, in order to avoid such a problem, in the conventional multilayer wiring board, as described in Patent Document 1, an electronic component such as a semiconductor chip is incorporated on the inner side where a plurality of base materials are stacked. The whole substrate is made thinner. In such a multilayer wiring board of Patent Document 1, a plurality of base materials having wiring patterns formed on the front and back surfaces are laminated with an insulating adhesive layer, respectively, and then the outer layer base material is cut out using a high frequency spindle. Thus, the wiring formed on the base material on the inner layer side is exposed, and the electronic component is mounted in the cut-out recess.
JP 2003-179180 A

  However, in such a conventional multilayer wiring board, a plurality of base materials having wiring formed on the front and back surfaces are laminated and laminated, and then the outer layer base material is cut out to be formed on the inner layer side base material. Since the wiring must be exposed without being damaged, a high cutting technique is required. That is, in such a cutting work, a plurality of points on the wiring provided on the base material on the inner layer side are measured in advance, and the positional relationship in the height direction of each measured point is calculated to calculate a virtual surface. Then, it is necessary to cut out along the virtual plane while controlling the cutting blade. For this reason, there is a problem that not only the cutting operation is complicated and troublesome, but also the cutting operation takes time, resulting in poor productivity.

  The problem to be solved by the present invention is to provide a multilayer wiring that can easily form a hollow portion into which an electronic component such as a semiconductor chip is inserted to improve productivity and can be mounted on the hollow portion satisfactorily. It is to provide a substrate and a manufacturing method thereof.

In order to solve the above problems, the present invention includes the following components.
In addition, the reference numerals of the drawings attached to the respective elements described in the section of each embodiment described later are attached to the respective constituent elements together with parentheses.

As shown in FIGS. 1 to 19, the invention according to claim 1 is a plurality of base materials (first and second) in which wirings (first to fourth wirings 22 to 25) are respectively formed on the front and back surfaces. A multilayer wiring board in which base materials 20 and 21) are stacked one above the other and electronic components (semiconductor chips 26, 45, 48, and 50) are mounted inside the stacked layers;
A cutout portion (27) into which the electronic component is inserted is formed in the base material (second base material 21) located on the upper layer side, and the lower base material (first surface) on which the upper layer base material is disposed. A frame-like built-up portion (28, 41) surrounding the outer periphery of the component mounting region (chip mounting region E) on which the electronic component is arranged is formed on the upper surface of the base material 20), and the outer peripheral side of this built-up portion An insulating adhesive layer (29) is provided on one of the base material on the lower layer side of the portion located on the upper side and the base material on the upper layer side facing this portion, and the lower side of the lower layer side is provided by this insulating adhesive layer. The multilayer wiring board (13, 40) is characterized in that a base material and the base material on the upper layer side are joined and the electronic component is inserted and mounted in the cut-out portion in this state.

  In the invention according to claim 2, as shown in FIGS. 2 to 9 and FIGS. 17 to 19, the build-up portion (28) is formed thicker than the thickness of the insulating adhesive layer (29). The multilayer wiring board according to claim 1, wherein the multilayer wiring board is provided.

  As shown in FIG. 2 to FIG. 9 and FIG. 17 to FIG. 19, the cut-out portion (27) has the built-up portion (28) and the electronic component (semiconductor chips 26, 45). 48, 50). The multi-layer wiring board according to claim 2, wherein the multi-layer wiring board is formed in a size to be inserted together with the multi-layer wiring board.

  In the invention according to claim 4, as shown in FIGS. 10 to 16, the build-up portion (41) is the base material on the lower layer side (41) located on the outer periphery of the component mounting area (chip mounting area E). It is formed over the upper surface of the first base material 20) and the inner peripheral surface of the cut-out portion (27) provided on the upper layer side base material (second base material 21). A multilayer wiring board according to claim 1.

In the invention according to claim 5, as shown in FIGS. 3 to 9 and FIGS. 17 to 19, wirings (first to fourth wirings 22 to 25) are patterned on the upper and lower surfaces, respectively, and stacked on the upper and lower sides. Electronic components (semiconductor chips 26, 45, 48, 50) are inserted into the base material (second base material 21) located on the upper layer side among the plurality of base materials (first, second base materials 20, 21) Forming a hollowed portion (27);
An outer periphery of a component mounting region (chip mounting region E) where the electronic component is disposed on the upper surface of the lower layer side substrate (first substrate 20) on which the upper layer side substrate is disposed. And forming an insulating adhesive layer (29) on the upper surface of the base material on the lower layer located on the outer peripheral side of the build-up part,
The upper layer side base material is overlapped on the lower layer side base material via the insulating adhesive layer and thermocompression bonded, thereby softening the insulating adhesive layer and the upper layer side base material. Bonding the base material on the lower layer side;
And a step of inserting and mounting the electronic component on the cut-out portion of the bonded base material on the upper layer side.

  As shown in FIGS. 3 to 9 and FIGS. 17 to 19, the invention according to claim 6 is configured such that the build-up portion (28) is formed by printing or plating more than the thickness of the insulating adhesive layer (29). The method for manufacturing a multilayer wiring board according to claim 5, wherein the multilayer wiring board is formed thick.

As shown in FIGS. 10 to 16, the invention according to claim 7 includes a plurality of base materials in which wirings (first to fourth wirings 22 to 25) are respectively formed in a pattern on the upper and lower surfaces and stacked vertically. Forming a hollow portion (27) into which the electronic component (semiconductor chip 26) is inserted into the base material (second base material 21) located on the upper layer side of the first and second base materials 20, 21);
An insulating adhesive layer (29) is provided on the upper surface of the lower layer side base material (first base material 20) on which the upper layer side base material is disposed, except for the portion corresponding to the cut-out portion, and this insulating adhesion A step of superimposing and temporarily fixing the upper layer side substrate on the lower layer side substrate via an agent layer;
The build-up portion (41) is formed in a frame shape along the outer periphery of the component mounting area (chip mounting area E) where the electronic component is arranged on the lower layer side base material exposed through the hollowed portion of the upper layer side base material. Forming the step,
The step of softening the insulating adhesive layer by thermocompression bonding the upper layer side substrate and the lower layer side substrate to join the lower layer side substrate and the upper layer side substrate; ,
And a step of inserting and mounting the electronic component on the cut-out portion of the bonded base material on the upper layer side.

  In the invention according to claim 8, as shown in FIGS. 10 to 16, the build-up portion (41) is disposed on the lower layer side located on the outer periphery of the component mounting area (chip mounting area E) by a dispenser. It forms over the upper surface of a base material (1st base material 20), and the internal peripheral surface of the said hollow part (27) provided in the said base material (2nd base material 21) of the upper layer side, It is characterized by the above-mentioned. A method for manufacturing a multilayer wiring board according to claim 7.

  According to the first aspect of the present invention, there is provided a multilayer wiring board in which a plurality of base materials each having a wiring pattern formed on the front and back surfaces are stacked one above the other, and electronic components are mounted inside the stacked layers. A hollow part for inserting electronic components is formed on the base material on the upper layer side, and the base material on the upper layer side is placed on the base material on the lower layer side, so the base material on the upper layer side is placed on the base material on the lower layer side Before cutting, a cut-out portion can be formed in advance on the upper layer side base material. For this reason, it is possible to easily and accurately form the cut-out portion on the upper layer-side base material without using a special cutting device, thereby improving productivity.

  In this case, a frame-shaped built-up portion surrounding the outer periphery of the component mounting area where the electronic component is arranged is formed on the upper surface of the base material on the lower layer side, and the lower layer side of the portion located on the outer peripheral side of the built-up portion is formed. An insulating adhesive layer is provided on one of the base material and the upper base material facing this portion, and the lower base material and the upper base material are joined by the insulating adhesive layer. Therefore, even if the cut-out portion is formed in advance on the upper layer side base material, when the lower layer side base material and the upper layer side base material are joined with the insulating adhesive layer, the insulating adhesive layer is formed by the built-up portion. Intrusion into the cut-out portion can be blocked, so that an electronic component can be inserted into the cut-out portion and can be mounted satisfactorily and reliably.

  According to the invention described in claim 2, since the build-up portion is formed thicker than the thickness of the insulating adhesive layer, the lower layer side substrate and the upper layer side substrate are joined by thermocompression bonding. Sometimes, even when the insulating adhesive layer is melted, the melted insulating adhesive layer can be prevented from getting over the built-up portion. For this reason, it is possible to reliably prevent the insulating adhesive layer from entering the hollowed portion of the base material on the upper layer side by the built-up portion, thereby inserting the electronic component into the hollowed portion and mounting it accurately and accurately. can do.

  According to the invention described in claim 3, the cut-out portion is formed to have a size that allows the built-up portion to be inserted together with the electronic component, thereby forming the built-up portion sufficiently thicker than the thickness of the insulating adhesive layer. However, when the base material on the lower layer side is overlapped with the base material on the upper layer side, the built-up portion is inserted into the cut-out portion, so that it is ensured that the insulating adhesive layer penetrates into the cut-out portion. In addition to being able to prevent the entire substrate from being particularly thickened by the built-up portion, the lower layer side base material and the upper layer side base material can be reliably and satisfactorily joined.

  According to the invention described in claim 4, the build-up part is formed on the upper surface of the lower layer side base material located on the outer periphery of the component mounting region and the inner peripheral surface of the cutout part provided on the upper side base material. By being formed over the gap, the gap between the base material on the lower layer side and the base material on the upper layer side generated along the inner peripheral surface of the cutout portion provided on the base material on the upper layer side is surely blocked by the built-up portion. be able to. For this reason, when the base material on the lower layer side and the base material on the upper layer side are joined by thermocompression bonding, even if the insulating adhesive layer melts, the insulating adhesive layer penetrates into the cut-out portion by the built-up portion. Thus, the electronic component can be inserted into the cut-out portion and mounted accurately and accurately.

  According to the fifth aspect of the present invention, a hollow portion for inserting an electronic component is formed in a base material located on the upper layer side among a plurality of base materials stacked in a vertical direction with wiring patterns formed on the upper and lower surfaces. Since the upper layer side substrate formed with the cut-out portion is bonded to the lower layer side substrate, before bonding the upper layer side substrate and the lower layer side substrate to the upper layer side substrate in advance. A hollow portion into which the electronic component is inserted can be formed. For this reason, similarly to the first aspect of the invention, the cut-out portion can be easily and accurately formed on the base material on the upper layer side without using a special cutting device, thereby improving productivity. be able to.

  In this case, in particular, the lower layer side located on the outer peripheral side of the built-up portion is formed on the upper surface of the base material on the lower layer side in a frame shape along the outer periphery of the component mounting area where the electronic component is arranged Since the insulating adhesive layer is provided on the upper surface of the base material, the upper layer side base material is superimposed on the lower layer side base material even if the cut-out portion into which the electronic component is inserted is previously formed in the upper layer base material. When the thermocompression bonding is performed, the insulative adhesive layer can be prevented from entering the cut-out portion by the built-up portion. For this reason, even if the cutout part is formed in the upper layer base material in advance and the upper layer base material and the lower layer base material are joined with the insulating adhesive layer, the electronic component is inserted into the cutout part. Good and reliable mounting is possible.

  According to the sixth aspect of the present invention, the build-up portion is formed easily and easily by printing or plating by forming the build-up portion thicker than the thickness of the insulating adhesive layer by printing or plating. Since the build-up part is formed thicker than the thickness of the insulating adhesive layer, the insulating adhesive layer is melted when the lower layer side substrate and the upper layer side substrate are thermocompression bonded. However, the insulating adhesive layer can be prevented from getting over the built-up portion. For this reason, it is possible to reliably prevent the insulating adhesive layer from entering the cut-out portion of the upper-layer base material, and thus it is possible to insert the electronic component into the cut-out portion and mount it reliably and accurately. .

  According to the invention of claim 7, among the plurality of base materials that are vertically patterned with wirings formed on the upper and lower surfaces, a hollow portion is formed into which the electronic component is inserted into the upper base material, Since the base material on the upper layer side in which the cut-out portion is formed is joined to the base material on the lower layer side, before joining the base material on the lower layer side and the base material on the upper layer side as in the invention described in claim 5, A cut-out portion into which an electronic component is inserted can be formed in advance on the upper layer side base material. For this reason, it is possible to easily and accurately form the cut-out portion on the upper layer-side base material without using a special cutting device, thereby improving productivity.

  In this case, in particular, an insulating adhesive layer is provided on the upper surface of the lower layer side substrate located on the outer peripheral side of the component mounting area where the electronic component is arranged, and the lower layer side substrate is interposed through this insulating adhesive layer. Overlay the upper base material on the material and temporarily fix it, and in this state, build up the overlay on the lower base material exposed through the hollowed out portion of the upper base material along the outer periphery of the component mounting area Therefore, even if the cut-out part into which the electronic component is inserted in the base material on the upper layer side is formed in advance, when the base material on the lower layer side and the base material on the upper layer side are joined by thermocompression bonding, Can prevent the insulative adhesive layer from penetrating into the cut-out portion, thereby forming a cut-out portion in the upper-layer base material in advance to insulate the upper-layer base material from the lower-layer base material. Even if it is joined with an adhesive layer, it is possible to insert electronic components in the cut-out part and mount it well and securely Kill.

  According to the invention described in claim 8, by using the dispenser, the upper surface of the lower layer-side base material located on the outer periphery of the component mounting region and the inner peripheral surface of the hollow portion provided on the upper layer side base material are dispensed by the dispenser. Thus, even when the lower layer side base material and the upper layer side base material are superposed and temporarily fixed, the overlay portion can be easily and easily formed by the dispenser. In particular, since the built-up portion is formed across the upper surface of the base material on the lower layer side located on the outer periphery of the component mounting region and the inner peripheral surface of the cutout portion provided on the base material on the upper layer side, A gap between the base material on the lower layer side and the base material on the upper layer side generated along the peripheral surface can be reliably closed by the built-up portion. For this reason, even when the insulating adhesive layer is melted when the base material on the lower layer side and the base material on the upper layer side are melted, the melted insulating adhesive layer penetrates into the cut-out portion by the built-up portion. Thus, the electronic component can be inserted into the cut-out portion and mounted accurately and accurately.

(Embodiment 1)
A first embodiment in which the multilayer wiring board of the present invention is used in an electronic wristwatch will be described below with reference to FIGS.
FIG. 1 is an enlarged cross-sectional view of a main part showing an electronic wristwatch to which the present invention is applied, and FIG. 2 is an enlarged cross-sectional view showing the main part of a multilayer wiring board incorporated in the electronic watch.
As shown in FIG. 1, the electronic wristwatch includes a wristwatch case 1. A watch glass 2 is attached to the upper part of the watch case 1, and a solar panel 3 formed in a ring shape is provided on the outer periphery of the lower surface of the watch glass 2. A watch module 4 is housed inside the watch case 1, and a back cover 5 is attached to the lower portion of the watch case 1 via a waterproof ring 6.

  As shown in FIG. 1, the timepiece module 4 includes an upper housing 7 and a lower housing 8. Above the upper housing 7, a liquid crystal display panel 10 is supported by an interconnector 11, and a backlight panel 12 is disposed on the upper surface of the upper housing 7 positioned below the liquid crystal display panel 10. . In addition, a multilayer wiring board 13 described later is disposed between the upper housing 7 and the lower housing 8, and the upper housing 7 and the lower housing 8 are separated by a ground plane 14 disposed on the lower surface of the lower housing 8. They are attached to each other with the multilayer wiring board 13 sandwiched therebetween. Further, the battery 15 is accommodated in the lower housing 8 while being pressed by the battery pressing plate 16. An insulating sheet 16 a for preventing conduction with the piezoelectric element 17 provided on the back cover 5 is attached to the lower surface of the battery pressing plate 16.

  In this case, the solar panel 3 receives external light and generates an electromotive force, and is electrically connected to the multilayer wiring board 13 by a connection member (not shown) such as a spring. The liquid crystal display panel 10 displays information such as time in an electro-optical manner, and is electrically connected to the multilayer wiring board 13 by an interconnector 11. The backlight panel 12 illuminates the liquid crystal display panel 10 and is composed of a planar light emitting element such as an EL element (electroluminescence element), and is connected to the multilayer wiring board 13 by a connecting member (not shown) such as a spring. Electrically connected. The battery 15 supplies power to the entire circuit of the timepiece module 4, and is electrically connected to the multilayer wiring board 13 by an electrode plate (not shown).

  By the way, as shown in FIG. 2, the multilayer wiring board 13 has first to fourth wirings 22 to 25 formed on the upper and lower surfaces of the first and second base materials 20 and 21, respectively. The substrates 20 and 21 are stacked one above the other, and a semiconductor chip 26 such as an LSI is mounted inside the stacked layers. That is, the first wiring 22 obtained by patterning the copper foil into a predetermined shape is provided on the lower surface of the first base material 20 located on the lower layer side, and the copper foil is also patterned into a predetermined shape on the upper surface. A second wiring 23 is provided. Moreover, the 3rd wiring 24 which patterned copper foil in the predetermined shape is provided in the lower surface of the 2nd base material 21 located in an upper layer side, and copper foil was patterned in the predetermined shape also on the upper surface. A fourth wiring 25 is provided.

  Further, a hollow portion 27 into which the semiconductor chip 26 is inserted is formed in the second base material 21 on the upper layer side. A chip mounting area E on which the semiconductor chip 26 is placed is provided on the upper surface of the first base material 20 on the lower layer side, and the built-up portion 28 surrounds the outer periphery of the chip mounting area E in a frame shape. Is provided. An insulating adhesive layer 29 made of a semi-cured insulating adhesive sheet such as a prepreg is provided on the upper surface of the first base material 20 on the lower layer side located on the outer peripheral side of the built-up portion 28. The first base material 20 on the lower layer side and the second base material 21 on the upper layer side are joined by the insulating adhesive layer 29. In this case, the build-up portion 28 is formed thicker than the thickness of the insulating adhesive layer 29, and the cut-out portion 27 is formed in a size that allows the build-up portion 28 to be inserted together with the semiconductor chip 26.

  On the chip mounting region E of the first base material 20 on the lower layer side, as shown in FIG. 2, the semiconductor chip 26 is inserted into a cutout portion 27 provided on the second base material 21 on the upper layer side. The conductive adhesive 30 is bonded in a state of being connected to the ground. In the semiconductor chip 26, a plurality of pad electrodes 26a provided on the upper surface thereof are connected to the connection electrodes 25a of the fourth wiring 25 provided on the upper surface of the second base 21 on the upper layer side by bonding wires 31 (FIG. 6). And is sealed with the mold resin 32 in this state. The first to fourth wirings 22 to 25 formed on the upper and lower surfaces of the first and second base materials 20 and 21 are not shown, but are IVHs (interstitial vias) provided between layers requiring connection. Hall).

Next, a method for manufacturing such a multilayer wiring board 13 will be described with reference to FIGS.
Of the first and second base materials 20 and 21 stacked one above the other, as shown in FIG. 3, first, a first wiring 22 is formed by patterning a copper foil on the lower surface of the first base material 20. At the same time, the second wiring 23 formed by patterning the copper foil is also formed on the upper surface of the first base material 20. Thereafter, as shown in FIG. 4, the overlaying portion 28 that surrounds the outer periphery of the chip mounting region E on which the semiconductor chip 26 is placed is printed on the second wiring 23 formed on the upper surface of the first base material 20. Or it forms in frame shape by plating. And as shown in FIG. 5, the insulating adhesive layer 29 which consists of semi-hardened insulating adhesive sheets, such as a prepreg, is provided in the upper surface of the 1st base material 20 located in the outer peripheral side of the build-up part 28. As shown in FIG. In this case, the built-up portion 28 is formed sufficiently thicker than the thickness of the insulating adhesive layer 29.

  Thereafter, as shown in FIG. 6, the second base material 21 is disposed on the first base material 20. At this time, the third wiring 24 formed by patterning the copper foil on the lower surface of the second base material 21 is formed in advance, and the fourth wiring formed by patterning the copper foil on the upper surface of the second base material 21 in advance. 25 is formed, and a cutout portion 27 into which the semiconductor chip 26 is inserted is formed. In this case, the cutout portion 27 is formed in a size that allows the built-up portion 28 formed on the first base material 20 to be inserted together with the semiconductor chip 26. And when arrange | positioning this 2nd base material 21 on the 1st base material 20, the 2nd wiring 23 of the 1st base material 20 and the 3rd wiring 24 of the 2nd base material 21 are made to oppose up and down. The built-up portion 28 formed on the first base material 20 is inserted into the cutout portion 27 of the second base material 21, and the second base material 21 is disposed on the first base material 20 in this state. .

  Then, as shown in FIG. 7, the first base material 20 on the lower layer side and the second base material 21 on the upper layer side are joined by softening the insulating adhesive layer 29 by thermocompression bonding. Thereafter, the conductive adhesive 30 is applied onto the second wiring 23 of the first base material 20 exposed through the cutout portion 27 of the second base material 21. In this state, as shown in FIG. 8, the semiconductor chip 26 is inserted into the cutout portion 27 of the second base material 21, and the inserted semiconductor chip 26 is bonded onto the first base material 20 with the conductive adhesive 30. . Then, the pad electrode 26 a provided on the upper surface of the semiconductor chip 26 and each connection electrode 25 a of the fourth wiring 25 provided on the upper surface of the second base material 21 are electrically connected by the bonding wire 31. Thereafter, as shown in FIG. 9, the semiconductor chip 26 exposed from the cutout portion 27 of the second base 21 and the connection electrodes 25 a of the fourth wiring 25 of the second base 21 are bonded together with the bonding wires 31 by the mold resin 32. Seal.

  As described above, according to the multilayer wiring substrate 13, the first and second base materials 20 and 21 in which the first to fourth wirings 22 and 25 are respectively patterned on the upper and lower surfaces and stacked vertically, A cutout portion 27 into which the semiconductor chip 26 is inserted is formed on the second base material 21 located on the upper layer side, and the second base material 21 on which the cutout portion 27 is formed is disposed on the first base material 20 on the lower layer side. Therefore, before joining the second base material 21 on the upper layer side and the first base material 20 on the lower layer side, a cutout portion 27 into which the semiconductor chip 26 is inserted in the second base material 21 on the upper layer side is formed in advance. can do. For this reason, it is possible to easily and accurately form the cutout portion 27 on the second base material 21 on the upper layer side without using a special cutting device as in the conventional example, thereby improving productivity. Can do.

  In this case, the built-up portion 28 is formed in a frame shape along the outer periphery of the chip mounting region E on which the semiconductor chip 26 is placed, particularly on the upper surface of the first base material 20 on the lower layer side. Since the insulating adhesive layer 29 is provided on the upper surface of the first base material 20 located on the outer peripheral side, even if the cutout portion 27 into which the semiconductor chip 26 is inserted is formed in advance on the second base material 21 on the upper layer side, When the second base material 21 is superimposed on the first base material 20 and thermocompression bonded, it is possible to prevent the insulating adhesive layer 29 from entering the cut-out part 27 by the build-up part 28. For this reason, even if the cutout portion 27 is formed in advance on the second base material 21 on the upper layer side and the second base material 21 and the first base material 20 are joined with the insulating adhesive layer 29, the cutout portion 27 is formed. The semiconductor chip 26 can be inserted and mounted reliably and accurately.

  At this time, since the build-up portion 28 is formed thicker than the thickness of the insulating adhesive layer 29 by printing or plating, the build-up portion 28 is easily formed on the first substrate 20 by printing or plating. It can be formed easily. In particular, since the built-up portion 28 is formed sufficiently thicker than the thickness of the insulating adhesive layer 29, when the first base material 20 on the lower layer side and the second base material 21 on the upper layer side are subjected to thermocompression bonding. Even if the insulating adhesive layer 29 is melted, the melted insulating adhesive layer 29 can be prevented from getting over the built-up portion 28. For this reason, it is possible to reliably prevent the insulating adhesive layer 29 from entering the cutout portion 27 provided in the second base material 21 on the upper layer side, thereby inserting the semiconductor chip 26 into the cutout portion 27. Can be mounted reliably and accurately.

(Embodiment 2)
Next, a second embodiment of the multilayer wiring board according to the present invention will be described with reference to FIGS. In addition, the same code | symbol is attached | subjected and demonstrated to the same part as Embodiment 1 shown by FIGS.
In the method of manufacturing the multilayer wiring board 40, first, as shown in FIG. 10, the first wiring 22 formed by patterning the copper foil is formed on the lower surface of the first base material 20, and the first base material 20 A second wiring 23 formed by patterning a copper foil is also formed on the upper surface. Thereafter, as shown in FIG. 11, an insulating adhesive layer 29 such as a prepreg is provided on a portion located on the outer peripheral side of the chip mounting region E on which the semiconductor chip 26 is placed on the upper surface of the first base material 20. .

  Then, as shown in FIG. 12, the 2nd base material 21 is arrange | positioned on the 1st base material 20 via the insulating adhesive layer 29, and it fixes temporarily to such an extent that the insulating adhesive layer 29 does not soften. At this time, the third wiring 24 formed by patterning the copper foil on the lower surface of the second base material 21 is formed in advance, and the fourth wiring formed by patterning the copper foil on the upper surface of the second base material 21 in advance. 25 is formed, and a cutout portion 27 into which the semiconductor chip 26 is inserted is formed. In this state, as shown in FIG. 13, the built-up portion 41 is formed in a frame shape along the outer periphery of the chip mounting region E on the upper surface of the first base material 20 on the lower layer side exposed through the cutout portion 27. As shown in FIG. 13, the build-up portion 41 is formed by the dispenser on the upper surface of the first base material 20 on the lower layer side located on the outer periphery of the chip mounting region E and the second base material 21 on the upper layer side. It is formed over the inner peripheral surface of the cutout portion 27.

  Then, as shown in FIG. 14, the first base material 20 on the lower layer side and the second base material 21 on the upper layer side are joined by softening the insulating adhesive layer 29 by thermocompression bonding. Thereafter, the conductive adhesive 30 is applied onto the second wiring 23 of the first base material 20 exposed through the cutout portion 27 of the second base material 21. In this state, as shown in FIG. 15, the semiconductor chip 26 is inserted into the cutout portion 27 of the second base material 21 and bonded to the first base material 20 with the conductive adhesive 30. Then, the pad electrode 26 a provided on the upper surface of the semiconductor chip 26 and each connection electrode 25 a of the fourth wiring 25 provided on the upper surface of the second base material 21 are electrically connected by the bonding wire 31. Thereafter, as shown in FIG. 16, the semiconductor chip 26 exposed from the cutout portion 27 of the second base material 21 and the connection electrodes 25 a of the fourth wiring 25 of the second base material 21 are bonded together with the bonding wires 31 by the mold resin 32. Seal.

  As described above, according to the method for manufacturing the multilayer wiring board 40, the first to fourth base materials 20 and 21 in which the first to fourth wirings 22 to 25 are patterned on the upper and lower surfaces and stacked vertically. Then, a cutout portion 27 into which the semiconductor chip 26 is inserted is formed in the second base material 21 on the upper layer side, and the second base material 21 on the upper layer side formed with the cutout portion 27 is joined to the first base material 20 on the lower layer side. Therefore, similarly to the first embodiment, before joining the lower-layer-side first base material 20 and the upper-layer-side second base material 21, the semiconductor chip 26 is inserted into the upper-layer-side second base material 21 in advance. A portion 27 can be formed. For this reason, it is possible to easily and accurately form the cutout portion 27 on the second base material 21 on the upper layer side without using a special cutting device, thereby improving the productivity.

  In this case, in particular, an insulating adhesive layer 29 is provided on a portion located on the outer peripheral side of the chip mounting region E of the semiconductor chip 26 on the upper surface of the first base material 20 on the lower layer side, and the insulating adhesive layer 29 is interposed therebetween. The second base material 21 is superposed and temporarily fixed on the first base material 20, and the build-up portion 41 is formed on the first base material 20 on the lower layer side exposed through the cutout portion 27 of the second base material 21 in this state. Since it is formed in a frame shape along the outer periphery of the chip mounting area E, the first base material 20 and the second base material 21 are formed even if the cutout portion 27 into which the semiconductor chip 26 is inserted is formed in the second base material 21 in advance. It is possible to prevent the insulating adhesive layer 29 from entering the cut-out portion 27 by the build-up portion 41 when joining by thermocompression bonding. For this reason, even if the cutout portion 27 is formed in the second base material 21 in advance and the second base material 21 and the first base material 20 are joined by the insulating adhesive layer 29, the semiconductor chip 26 is attached to the cutout portion 27. It can be inserted and mounted accurately and reliably. .

  Further, at this time, the built-up portion 41 is dispensed by the dispenser with the upper surface of the first base material 20 on the lower layer side located on the outer periphery of the chip mounting region E and the cutout portion 27 provided on the second base material 21 on the upper layer side. Since it forms over an inner peripheral surface, even if the 1st base material 20 and the 2nd base material 21 are piled up and temporarily fixed, the build-up part 41 can be formed easily and easily with a dispenser. . In particular, since the built-up portion 41 is formed across the upper surface of the first base material 20 located on the outer periphery of the chip mounting region E and the inner peripheral surface of the cutout portion 27 of the second base material 21, The gap between the first base material 20 and the second base material 21 generated along the inner peripheral surface of the portion 27 can be reliably closed by the built-up portion 41. Therefore, when the first base material 20 and the second base material 21 are thermocompression bonded, even if the insulating adhesive layer 29 is melted, the melted insulating adhesive layer 29 is cut out by the built-up portion 41. Intrusion into the portion 27 can be reliably prevented, whereby the semiconductor chip 26 can be inserted into the cutout portion 27 and can be reliably and accurately mounted.

  In the first and second embodiments, each pad electrode 26a of the semiconductor chip 26 is connected to each connection electrode 25a of the fourth wiring 25 formed on the upper surface of the second base material 21 on the upper layer side by wire bonding. Although described, it is not restricted to this, For example, the structure connected as shown in FIGS. 17-19 may be sufficient, for example.

  That is, in the first modification shown in FIG. 17, each pad electrode (not shown) is provided on the lower surface of the semiconductor chip 45, and the semiconductor chip 45 is inserted into the cutout portion 27 of the second base material 21. In this state, each connection electrode 23a of the second wiring 23 formed in the chip mounting region E of the first base material 20 and each pad electrode of the semiconductor chip 45 are connected by solder balls 46 by a BGA (ball grid array) method. ing. In this case, each connection electrode 23 a of the second wiring 23 of the first base material 20 is electrically connected to the first wiring 22 on the lower surface side by IVH 47.

  In the second modification shown in FIG. 18, each connection lead 48 a extending from the side surface of the semiconductor chip 48 is connected to each connection electrode of the second wiring 23 formed in the chip mounting region E of the first base material 20. 23b is connected with solder 49 respectively. In the third modification shown in FIG. 19, each pad electrode (not shown) provided on the side surface of the semiconductor chip 50 is formed on the second wiring 23 formed in the chip mounting region E of the first base material 20. Each connection electrode 23b is connected by solder 51. Also in the first to third modified examples, by forming the built-up portion 28 in a frame shape along the outer periphery of the chip mounting region E on the upper surface of the first base material 20, the same operation as that of the first embodiment is achieved. effective.

  In the first and second embodiments and the modifications thereof, the multilayer wiring boards 13 and 40 having the two-layer structure in which the first and second base materials 20 and 21 are stacked one above the other have been described. Alternatively, a configuration in which three or more base materials are sequentially laminated by the insulating adhesive layer 29 may be used. Such a multilayer wiring board enables further high-density mounting.

  Further, in the first and second embodiments and the modifications thereof, the case where the multilayer wiring boards 13 and 40 are used for an electronic watch has been described. However, the present invention is not limited to this, and for example, an electronic watch such as a travel watch, a table clock, a wall clock, etc. In addition to being applicable, it is not necessarily an electronic timepiece, and can be widely used in various electronic devices such as a mobile phone, an electronic dictionary, an electronic camera, a PDA (personal digital assistant), and a personal computer.

It is the expanded sectional view which showed the principal part of the electronic wristwatch to which this invention is applied. (Embodiment 1) FIG. 2 is an enlarged cross-sectional view showing a main part of a multilayer wiring board incorporated in the electronic wristwatch of FIG. 1. FIG. 3 is a cross-sectional view of a state in which wiring is formed on the upper and lower surfaces of the first base material on the lower layer side in the method for manufacturing the multilayer wiring board of FIG. 2. It is sectional drawing of the state which formed the build-up part on the 1st base material of FIG. It is sectional drawing of the state which provided the insulating adhesive bond layer on the upper surface of the 1st base material located in the outer peripheral side of the build-up part of FIG. It is sectional drawing of the state which has arrange | positioned the 2nd base material on the 1st base material of FIG. It is sectional drawing of the state which joined the 1st, 2nd base material of FIG. 6 by thermocompression bonding. It is sectional drawing of the state which has arrange | positioned the semiconductor chip in the hollow part of the 2nd base material of FIG. 7, and was wire-bonded. It is sectional drawing of the state which sealed the semiconductor chip of FIG. 8 with mold resin. It is sectional drawing of the state which formed the wiring in the upper and lower surfaces of the 1st base material of the lower layer side in the manufacturing method of the multilayer wiring board of this invention. (Embodiment 2) It is sectional drawing of the state which provided the insulating adhesive layer on the upper surface of the 1st base material of FIG. It is sectional drawing of the state which temporarily fixed the 2nd base material on the 1st base material of FIG. It is sectional drawing of the state which formed the build-up part on the 1st base material of FIG. It is sectional drawing of the state which joined the 1st, 2nd base material of FIG. 13 by thermocompression bonding, and inserted the semiconductor chip in the hollow part. It is sectional drawing of the state which carried out the wire bonding of the semiconductor chip of FIG. It is sectional drawing of the state which sealed the semiconductor chip of FIG. 15 with mold resin. It is sectional drawing which showed the 1st modification of the connection structure of the semiconductor chip integrated in the multilayer wiring board of this invention. It is sectional drawing which showed the 2nd modification of the connection structure of the semiconductor chip integrated in the multilayer wiring board of this invention. It is sectional drawing which showed the 3rd modification of the connection structure of the semiconductor chip integrated in the multilayer wiring board of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 13, 40 Multilayer wiring board 20 1st base material 21 2nd base material 22-25 1st-4th wiring 26, 45, 48, 50 Semiconductor chip 27 Cut-out part 28, 41 Overlay part 29 Insulating adhesive layer

Claims (8)

A multilayer wiring board in which a plurality of base materials each having a wiring pattern formed on the front and back surfaces are stacked one above the other, and electronic components are mounted inside the stacked layers,
A component mounting in which a cut-out portion for inserting the electronic component is formed in the base material positioned on the upper layer side, and the electronic component is disposed on the upper surface of the base material on the lower layer side on which the base material on the upper layer side is disposed A frame-shaped built-up portion surrounding the outer periphery of the region is formed, and insulated from one of the base material on the lower layer side of the portion located on the outer peripheral side of the built-up portion and the base material on the upper layer side facing this portion An adhesive layer is provided, and the base material on the lower layer side and the base material on the upper layer side are joined by the insulating adhesive layer, and the electronic component is inserted and mounted in the cut-out portion in this state. A multilayer wiring board characterized by comprising:   The multilayer wiring board according to claim 1, wherein the build-up portion is formed thicker than a thickness of the insulating adhesive layer.   3. The multilayer wiring board according to claim 2, wherein the cut-out portion is formed in a size such that the build-up portion is inserted together with the electronic component.   The build-up portion is formed across the upper surface of the lower layer side base material located on the outer periphery of the component mounting region and the inner peripheral surface of the cutout portion provided on the upper layer side base material. The multilayer wiring board according to claim 1. A step of forming a hollow portion into which an electronic component is inserted into a base material located on the upper layer side among a plurality of base materials that are respectively patterned on the upper and lower surfaces and stacked vertically,
A built-up portion is formed in a frame shape on the upper surface of the lower-layer side substrate on which the upper-layer side substrate is disposed, along the outer periphery of the component mounting region on which the electronic component is disposed, and the outer periphery of the built-up portion Providing an insulating adhesive layer on the upper surface of the base material on the lower layer side located on the side;
The upper layer side base material is overlapped on the lower layer side base material via the insulating adhesive layer and thermocompression bonded, thereby softening the insulating adhesive layer and the upper layer side base material. Bonding the base material on the lower layer side;
And a step of inserting and mounting the electronic component on the cut-out portion of the bonded upper-layer base material.   The method for manufacturing a multilayer wiring board according to claim 5, wherein the build-up portion is formed thicker than the insulating adhesive layer by printing or plating. A step of forming a hollow portion into which an electronic component is inserted into a base material located on the upper layer side among a plurality of base materials that are respectively patterned on the upper and lower surfaces and stacked vertically,
An insulating adhesive layer is provided on the upper surface of the lower layer side substrate on which the upper layer side substrate is disposed, excluding a portion corresponding to the cut-out portion, and the upper layer side base is interposed through the insulating adhesive layer. A step of superimposing and temporarily fixing the material on the base material on the lower layer side;
Forming a built-up portion in a frame shape along the outer periphery of a component mounting area where the electronic component is disposed on the upper surface of the lower-layer base material exposed through the cut-out portion of the upper-layer base material;
The step of softening the insulating adhesive layer by thermocompression bonding the upper layer side substrate and the lower layer side substrate to join the lower layer side substrate and the upper layer side substrate; ,
And a step of inserting and mounting the electronic component on the cut-out portion of the bonded upper-layer base material. The build-up portion is formed by a dispenser across the upper surface of the base material on the lower layer side located on the outer periphery of the component mounting region and the inner peripheral surface of the cutout portion provided on the base material on the upper layer side. The method for producing a multilayer wiring board according to claim 7, wherein:

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